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804a5dd6 JE |
1 | /* |
2 | * Common base for NXP LPC18xx and LPC43xx devices. | |
3 | * | |
4 | * Copyright 2015 Joachim Eastwood <manabian@gmail.com> | |
5 | * | |
6 | * This code is released using a dual license strategy: BSD/GPL | |
7 | * You can choose the licence that better fits your requirements. | |
8 | * | |
9 | * Released under the terms of 3-clause BSD License | |
10 | * Released under the terms of GNU General Public License Version 2.0 | |
11 | * | |
12 | */ | |
13 | ||
14 | #include "armv7-m.dtsi" | |
15 | ||
ba2db535 JE |
16 | #include "dt-bindings/clock/lpc18xx-cgu.h" |
17 | #include "dt-bindings/clock/lpc18xx-ccu.h" | |
18 | ||
7836dce4 JE |
19 | #define LPC_PIN(port, pin) (0x##port * 32 + pin) |
20 | #define LPC_GPIO(port, pin) (port * 32 + pin) | |
21 | ||
804a5dd6 JE |
22 | / { |
23 | cpus { | |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | ||
27 | cpu@0 { | |
28 | compatible = "arm,cortex-m3"; | |
29 | device_type = "cpu"; | |
30 | reg = <0x0>; | |
ba2db535 | 31 | clocks = <&ccu1 CLK_CPU_CORE>; |
804a5dd6 JE |
32 | }; |
33 | }; | |
34 | ||
35 | clocks { | |
36 | xtal: xtal { | |
37 | compatible = "fixed-clock"; | |
38 | #clock-cells = <0>; | |
39 | clock-frequency = <12000000>; | |
40 | }; | |
41 | ||
ba2db535 JE |
42 | xtal32: xtal32 { |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <32768>; | |
46 | }; | |
47 | ||
48 | enet_rx_clk: enet_rx_clk { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | clock-frequency = <0>; | |
52 | clock-output-names = "enet_rx_clk"; | |
53 | }; | |
54 | ||
55 | enet_tx_clk: enet_tx_clk { | |
56 | compatible = "fixed-clock"; | |
57 | #clock-cells = <0>; | |
58 | clock-frequency = <0>; | |
59 | clock-output-names = "enet_tx_clk"; | |
60 | }; | |
61 | ||
62 | gp_clkin: gp_clkin { | |
63 | compatible = "fixed-clock"; | |
804a5dd6 | 64 | #clock-cells = <0>; |
ba2db535 JE |
65 | clock-frequency = <0>; |
66 | clock-output-names = "gp_clkin"; | |
804a5dd6 JE |
67 | }; |
68 | }; | |
69 | ||
70 | soc { | |
ba2db535 JE |
71 | cgu: clock-controller@40050000 { |
72 | compatible = "nxp,lpc1850-cgu"; | |
73 | reg = <0x40050000 0x1000>; | |
74 | #clock-cells = <1>; | |
75 | clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; | |
76 | }; | |
77 | ||
78 | ccu1: clock-controller@40051000 { | |
79 | compatible = "nxp,lpc1850-ccu"; | |
80 | reg = <0x40051000 0x1000>; | |
81 | #clock-cells = <1>; | |
82 | clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, | |
83 | <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, | |
84 | <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, | |
85 | <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; | |
86 | clock-names = "base_apb3_clk", "base_apb1_clk", | |
87 | "base_spifi_clk", "base_cpu_clk", | |
88 | "base_periph_clk", "base_usb0_clk", | |
89 | "base_usb1_clk", "base_spi_clk"; | |
90 | }; | |
91 | ||
92 | ccu2: clock-controller@40052000 { | |
93 | compatible = "nxp,lpc1850-ccu"; | |
94 | reg = <0x40052000 0x1000>; | |
95 | #clock-cells = <1>; | |
96 | clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, | |
97 | <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, | |
98 | <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, | |
99 | <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; | |
100 | clock-names = "base_audio_clk", "base_uart3_clk", | |
101 | "base_uart2_clk", "base_uart1_clk", | |
102 | "base_uart0_clk", "base_ssp1_clk", | |
103 | "base_ssp0_clk", "base_sdio_clk"; | |
104 | }; | |
105 | ||
804a5dd6 | 106 | uart0: serial@40081000 { |
f2b1c507 | 107 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
108 | reg = <0x40081000 0x1000>; |
109 | reg-shift = <2>; | |
110 | interrupts = <24>; | |
ba2db535 | 111 | clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; |
f2b1c507 | 112 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
113 | status = "disabled"; |
114 | }; | |
115 | ||
116 | uart1: serial@40082000 { | |
f2b1c507 | 117 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
118 | reg = <0x40082000 0x1000>; |
119 | reg-shift = <2>; | |
120 | interrupts = <25>; | |
ba2db535 | 121 | clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; |
f2b1c507 | 122 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
123 | status = "disabled"; |
124 | }; | |
125 | ||
5d2ea79c JE |
126 | ssp0: spi@40083000 { |
127 | compatible = "arm,pl022", "arm,primecell"; | |
128 | reg = <0x40083000 0x1000>; | |
129 | interrupts = <22>; | |
130 | clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; | |
131 | clock-names = "sspclk", "apb_pclk"; | |
132 | #address-cells = <1>; | |
133 | #size-cells = <0>; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
804a5dd6 JE |
137 | timer0: timer@40084000 { |
138 | compatible = "nxp,lpc3220-timer"; | |
139 | reg = <0x40084000 0x1000>; | |
140 | interrupts = <12>; | |
ba2db535 | 141 | clocks = <&ccu1 CLK_CPU_TIMER0>; |
804a5dd6 JE |
142 | clock-names = "timerclk"; |
143 | }; | |
144 | ||
145 | timer1: timer@40085000 { | |
146 | compatible = "nxp,lpc3220-timer"; | |
147 | reg = <0x40085000 0x1000>; | |
148 | interrupts = <13>; | |
ba2db535 | 149 | clocks = <&ccu1 CLK_CPU_TIMER1>; |
804a5dd6 JE |
150 | clock-names = "timerclk"; |
151 | }; | |
152 | ||
d881f5e2 JE |
153 | pinctrl: pinctrl@40086000 { |
154 | compatible = "nxp,lpc1850-scu"; | |
155 | reg = <0x40086000 0x1000>; | |
156 | clocks = <&ccu1 CLK_CPU_SCU>; | |
157 | }; | |
158 | ||
7e6c8376 JE |
159 | can1: can@400a4000 { |
160 | compatible = "bosch,c_can"; | |
161 | reg = <0x400a4000 0x1000>; | |
162 | interrupts = <43>; | |
163 | clocks = <&ccu1 CLK_APB1_CAN1>; | |
164 | status = "disabled"; | |
165 | }; | |
166 | ||
804a5dd6 | 167 | uart2: serial@400c1000 { |
f2b1c507 | 168 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
169 | reg = <0x400c1000 0x1000>; |
170 | reg-shift = <2>; | |
171 | interrupts = <26>; | |
ba2db535 | 172 | clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; |
f2b1c507 | 173 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
174 | status = "disabled"; |
175 | }; | |
176 | ||
177 | uart3: serial@400c2000 { | |
f2b1c507 | 178 | compatible = "nxp,lpc1850-uart", "ns16550a"; |
804a5dd6 JE |
179 | reg = <0x400c2000 0x1000>; |
180 | reg-shift = <2>; | |
181 | interrupts = <27>; | |
ba2db535 | 182 | clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; |
f2b1c507 | 183 | clock-names = "uartclk", "reg"; |
804a5dd6 JE |
184 | status = "disabled"; |
185 | }; | |
186 | ||
187 | timer2: timer@400c3000 { | |
188 | compatible = "nxp,lpc3220-timer"; | |
189 | reg = <0x400c3000 0x1000>; | |
190 | interrupts = <14>; | |
ba2db535 | 191 | clocks = <&ccu1 CLK_CPU_TIMER2>; |
804a5dd6 JE |
192 | clock-names = "timerclk"; |
193 | }; | |
194 | ||
195 | timer3: timer@400c4000 { | |
196 | compatible = "nxp,lpc3220-timer"; | |
197 | reg = <0x400c4000 0x1000>; | |
198 | interrupts = <15>; | |
ba2db535 | 199 | clocks = <&ccu1 CLK_CPU_TIMER3>; |
804a5dd6 JE |
200 | clock-names = "timerclk"; |
201 | }; | |
7836dce4 | 202 | |
5d2ea79c JE |
203 | ssp1: spi@400c5000 { |
204 | compatible = "arm,pl022", "arm,primecell"; | |
205 | reg = <0x400c5000 0x1000>; | |
206 | interrupts = <23>; | |
207 | clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; | |
208 | clock-names = "sspclk", "apb_pclk"; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <0>; | |
211 | status = "disabled"; | |
212 | }; | |
213 | ||
7e6c8376 JE |
214 | can0: can@400e2000 { |
215 | compatible = "bosch,c_can"; | |
216 | reg = <0x400e2000 0x1000>; | |
217 | interrupts = <51>; | |
218 | clocks = <&ccu1 CLK_APB3_CAN0>; | |
219 | status = "disabled"; | |
220 | }; | |
221 | ||
7836dce4 JE |
222 | gpio: gpio@400f4000 { |
223 | compatible = "nxp,lpc1850-gpio"; | |
224 | reg = <0x400f4000 0x4000>; | |
225 | clocks = <&ccu1 CLK_CPU_GPIO>; | |
226 | gpio-controller; | |
227 | #gpio-cells = <2>; | |
228 | gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, | |
229 | <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, | |
230 | <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, | |
231 | <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, | |
232 | <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, | |
233 | <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, | |
234 | <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, | |
235 | <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, | |
236 | <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, | |
237 | <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, | |
238 | <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, | |
239 | <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, | |
240 | <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, | |
241 | <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, | |
242 | <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, | |
243 | <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, | |
244 | <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, | |
245 | <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, | |
246 | <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, | |
247 | <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, | |
248 | <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, | |
249 | <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, | |
250 | <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, | |
251 | <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, | |
252 | <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, | |
253 | <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, | |
254 | <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, | |
255 | <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, | |
256 | <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, | |
257 | <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, | |
258 | <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, | |
259 | <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, | |
260 | <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, | |
261 | <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, | |
262 | <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, | |
263 | <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, | |
264 | <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, | |
265 | <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, | |
266 | <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, | |
267 | <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; | |
268 | }; | |
804a5dd6 JE |
269 | }; |
270 | }; |