projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 804a5dd6 JE |
1 | /* |
| 2 | * Common base for NXP LPC18xx and LPC43xx devices. | |
| 3 | * | |
| 4 | * Copyright 2015 Joachim Eastwood <manabian@gmail.com> | |
| 5 | * | |
| 6 | * This code is released using a dual license strategy: BSD/GPL | |
| 7 | * You can choose the licence that better fits your requirements. | |
| 8 | * | |
| 9 | * Released under the terms of 3-clause BSD License | |
| 10 | * Released under the terms of GNU General Public License Version 2.0 | |
| 11 | * | |
| 12 | */ | |
| 13 | ||
| 14 | #include "armv7-m.dtsi" | |
| 15 | ||
| ba2db535 JE |
16 | #include "dt-bindings/clock/lpc18xx-cgu.h" |
| 17 | #include "dt-bindings/clock/lpc18xx-ccu.h" | |
| 18 | ||
| 804a5dd6 JE |
19 | / { |
| 20 | cpus { | |
| 21 | #address-cells = <1>; | |
| 22 | #size-cells = <0>; | |
| 23 | ||
| 24 | cpu@0 { | |
| 25 | compatible = "arm,cortex-m3"; | |
| 26 | device_type = "cpu"; | |
| 27 | reg = <0x0>; | |
| ba2db535 | 28 | clocks = <&ccu1 CLK_CPU_CORE>; |
| 804a5dd6 JE |
29 | }; |
| 30 | }; | |
| 31 | ||
| 32 | clocks { | |
| 33 | xtal: xtal { | |
| 34 | compatible = "fixed-clock"; | |
| 35 | #clock-cells = <0>; | |
| 36 | clock-frequency = <12000000>; | |
| 37 | }; | |
| 38 | ||
| ba2db535 JE |
39 | xtal32: xtal32 { |
| 40 | compatible = "fixed-clock"; | |
| 41 | #clock-cells = <0>; | |
| 42 | clock-frequency = <32768>; | |
| 43 | }; | |
| 44 | ||
| 45 | enet_rx_clk: enet_rx_clk { | |
| 46 | compatible = "fixed-clock"; | |
| 47 | #clock-cells = <0>; | |
| 48 | clock-frequency = <0>; | |
| 49 | clock-output-names = "enet_rx_clk"; | |
| 50 | }; | |
| 51 | ||
| 52 | enet_tx_clk: enet_tx_clk { | |
| 53 | compatible = "fixed-clock"; | |
| 54 | #clock-cells = <0>; | |
| 55 | clock-frequency = <0>; | |
| 56 | clock-output-names = "enet_tx_clk"; | |
| 57 | }; | |
| 58 | ||
| 59 | gp_clkin: gp_clkin { | |
| 60 | compatible = "fixed-clock"; | |
| 804a5dd6 | 61 | #clock-cells = <0>; |
| ba2db535 JE |
62 | clock-frequency = <0>; |
| 63 | clock-output-names = "gp_clkin"; | |
| 804a5dd6 JE |
64 | }; |
| 65 | }; | |
| 66 | ||
| 67 | soc { | |
| ba2db535 JE |
68 | cgu: clock-controller@40050000 { |
| 69 | compatible = "nxp,lpc1850-cgu"; | |
| 70 | reg = <0x40050000 0x1000>; | |
| 71 | #clock-cells = <1>; | |
| 72 | clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; | |
| 73 | }; | |
| 74 | ||
| 75 | ccu1: clock-controller@40051000 { | |
| 76 | compatible = "nxp,lpc1850-ccu"; | |
| 77 | reg = <0x40051000 0x1000>; | |
| 78 | #clock-cells = <1>; | |
| 79 | clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, | |
| 80 | <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, | |
| 81 | <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, | |
| 82 | <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; | |
| 83 | clock-names = "base_apb3_clk", "base_apb1_clk", | |
| 84 | "base_spifi_clk", "base_cpu_clk", | |
| 85 | "base_periph_clk", "base_usb0_clk", | |
| 86 | "base_usb1_clk", "base_spi_clk"; | |
| 87 | }; | |
| 88 | ||
| 89 | ccu2: clock-controller@40052000 { | |
| 90 | compatible = "nxp,lpc1850-ccu"; | |
| 91 | reg = <0x40052000 0x1000>; | |
| 92 | #clock-cells = <1>; | |
| 93 | clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, | |
| 94 | <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, | |
| 95 | <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, | |
| 96 | <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>; | |
| 97 | clock-names = "base_audio_clk", "base_uart3_clk", | |
| 98 | "base_uart2_clk", "base_uart1_clk", | |
| 99 | "base_uart0_clk", "base_ssp1_clk", | |
| 100 | "base_ssp0_clk", "base_sdio_clk"; | |
| 101 | }; | |
| 102 | ||
| 804a5dd6 JE |
103 | uart0: serial@40081000 { |
| 104 | compatible = "ns16550a"; | |
| 105 | reg = <0x40081000 0x1000>; | |
| 106 | reg-shift = <2>; | |
| 107 | interrupts = <24>; | |
| ba2db535 | 108 | clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>; |
| 804a5dd6 JE |
109 | status = "disabled"; |
| 110 | }; | |
| 111 | ||
| 112 | uart1: serial@40082000 { | |
| 113 | compatible = "ns16550a"; | |
| 114 | reg = <0x40082000 0x1000>; | |
| 115 | reg-shift = <2>; | |
| 116 | interrupts = <25>; | |
| ba2db535 | 117 | clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>; |
| 804a5dd6 JE |
118 | status = "disabled"; |
| 119 | }; | |
| 120 | ||
| 121 | timer0: timer@40084000 { | |
| 122 | compatible = "nxp,lpc3220-timer"; | |
| 123 | reg = <0x40084000 0x1000>; | |
| 124 | interrupts = <12>; | |
| ba2db535 | 125 | clocks = <&ccu1 CLK_CPU_TIMER0>; |
| 804a5dd6 JE |
126 | clock-names = "timerclk"; |
| 127 | }; | |
| 128 | ||
| 129 | timer1: timer@40085000 { | |
| 130 | compatible = "nxp,lpc3220-timer"; | |
| 131 | reg = <0x40085000 0x1000>; | |
| 132 | interrupts = <13>; | |
| ba2db535 | 133 | clocks = <&ccu1 CLK_CPU_TIMER1>; |
| 804a5dd6 JE |
134 | clock-names = "timerclk"; |
| 135 | }; | |
| 136 | ||
| 137 | uart2: serial@400c1000 { | |
| 138 | compatible = "ns16550a"; | |
| 139 | reg = <0x400c1000 0x1000>; | |
| 140 | reg-shift = <2>; | |
| 141 | interrupts = <26>; | |
| ba2db535 | 142 | clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>; |
| 804a5dd6 JE |
143 | status = "disabled"; |
| 144 | }; | |
| 145 | ||
| 146 | uart3: serial@400c2000 { | |
| 147 | compatible = "ns16550a"; | |
| 148 | reg = <0x400c2000 0x1000>; | |
| 149 | reg-shift = <2>; | |
| 150 | interrupts = <27>; | |
| ba2db535 | 151 | clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>; |
| 804a5dd6 JE |
152 | status = "disabled"; |
| 153 | }; | |
| 154 | ||
| 155 | timer2: timer@400c3000 { | |
| 156 | compatible = "nxp,lpc3220-timer"; | |
| 157 | reg = <0x400c3000 0x1000>; | |
| 158 | interrupts = <14>; | |
| ba2db535 | 159 | clocks = <&ccu1 CLK_CPU_TIMER2>; |
| 804a5dd6 JE |
160 | clock-names = "timerclk"; |
| 161 | }; | |
| 162 | ||
| 163 | timer3: timer@400c4000 { | |
| 164 | compatible = "nxp,lpc3220-timer"; | |
| 165 | reg = <0x400c4000 0x1000>; | |
| 166 | interrupts = <15>; | |
| ba2db535 | 167 | clocks = <&ccu1 CLK_CPU_TIMER3>; |
| 804a5dd6 JE |
168 | clock-names = "timerclk"; |
| 169 | }; | |
| 170 | }; | |
| 171 | }; |