[deliverable/linux.git] / arch / arm / boot / dts / lpc18xx.dtsi

/*
 * Common base for NXP LPC18xx and LPC43xx devices.
 *
 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
 *
 * This code is released using a dual license strategy: BSD/GPL
 * You can choose the licence that better fits your requirements.
 *
 * Released under the terms of 3-clause BSD License
 * Released under the terms of GNU General Public License Version 2.0
 *
 */

#include "armv7-m.dtsi"

#include "dt-bindings/clock/lpc18xx-cgu.h"
#include "dt-bindings/clock/lpc18xx-ccu.h"

#define LPC_PIN(port, pin)	(0x##port * 32 + pin)
#define LPC_GPIO(port, pin)	(port * 32 + pin)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-m3";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <&ccu1 CLK_CPU_CORE>;
		};
	};

	clocks {
		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		xtal32: xtal32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		enet_rx_clk: enet_rx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_rx_clk";
		};

		enet_tx_clk: enet_tx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_tx_clk";
		};

		gp_clkin: gp_clkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "gp_clkin";
		};
	};

	soc {
		mmcsd: mmcsd@40004000 {
			compatible = "snps,dw-mshc";
			reg = <0x40004000 0x1000>;
			interrupts = <6>;
			num-slots = <1>;
			clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
			clock-names = "ciu", "biu";
			status = "disabled";
		};

		cgu: clock-controller@40050000 {
			compatible = "nxp,lpc1850-cgu";
			reg = <0x40050000 0x1000>;
			#clock-cells = <1>;
			clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
		};

		ccu1: clock-controller@40051000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40051000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
				 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
				 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
				 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
			clock-names = "base_apb3_clk",   "base_apb1_clk",
				      "base_spifi_clk",  "base_cpu_clk",
				      "base_periph_clk", "base_usb0_clk",
				      "base_usb1_clk",   "base_spi_clk";
		};

		ccu2: clock-controller@40052000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40052000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
				 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
				 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
				 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
			clock-names = "base_audio_clk", "base_uart3_clk",
				      "base_uart2_clk", "base_uart1_clk",
				      "base_uart0_clk", "base_ssp1_clk",
				      "base_ssp0_clk",  "base_sdio_clk";
		};

		uart0: serial@40081000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40081000 0x1000>;
			reg-shift = <2>;
			interrupts = <24>;
			clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		uart1: serial@40082000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40082000 0x1000>;
			reg-shift = <2>;
			interrupts = <25>;
			clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		ssp0: spi@40083000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x40083000 0x1000>;
			interrupts = <22>;
			clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
			clock-names = "sspclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		timer0: timer@40084000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40084000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu1 CLK_CPU_TIMER0>;
			clock-names = "timerclk";
		};

		timer1: timer@40085000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40085000 0x1000>;
			interrupts = <13>;
			clocks = <&ccu1 CLK_CPU_TIMER1>;
			clock-names = "timerclk";
		};

		pinctrl: pinctrl@40086000 {
			compatible = "nxp,lpc1850-scu";
			reg = <0x40086000 0x1000>;
			clocks = <&ccu1 CLK_CPU_SCU>;
		};

		can1: can@400a4000 {
			compatible = "bosch,c_can";
			reg = <0x400a4000 0x1000>;
			interrupts = <43>;
			clocks = <&ccu1 CLK_APB1_CAN1>;
			status = "disabled";
		};

		uart2: serial@400c1000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c1000 0x1000>;
			reg-shift = <2>;
			interrupts = <26>;
			clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		uart3: serial@400c2000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c2000 0x1000>;
			reg-shift = <2>;
			interrupts = <27>;
			clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
			clock-names = "uartclk", "reg";
			status = "disabled";
		};

		timer2: timer@400c3000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c3000 0x1000>;
			interrupts = <14>;
			clocks = <&ccu1 CLK_CPU_TIMER2>;
			clock-names = "timerclk";
		};

		timer3: timer@400c4000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c4000 0x1000>;
			interrupts = <15>;
			clocks = <&ccu1 CLK_CPU_TIMER3>;
			clock-names = "timerclk";
		};

		ssp1: spi@400c5000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x400c5000 0x1000>;
			interrupts = <23>;
			clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
			clock-names = "sspclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@400e2000 {
			compatible = "bosch,c_can";
			reg = <0x400e2000 0x1000>;
			interrupts = <51>;
			clocks = <&ccu1 CLK_APB3_CAN0>;
			status = "disabled";
		};

		gpio: gpio@400f4000 {
			compatible = "nxp,lpc1850-gpio";
			reg = <0x400f4000 0x4000>;
			clocks = <&ccu1 CLK_CPU_GPIO>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
					<&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
					<&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
					<&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
					<&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
					<&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
					<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
					<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
					<&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
					<&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
					<&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
					<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
					<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
					<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
					<&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
					<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
					<&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
					<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
					<&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
					<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
					<&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
					<&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
					<&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
					<&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
					<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
					<&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
					<&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
					<&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
					<&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
					<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
					<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
					<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
					<&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
					<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
					<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
					<&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
					<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
					<&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
					<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
					<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
		};
	};
};
Commit	Line	Data
804a5dd6 JE	1	/*
	2	* Common base for NXP LPC18xx and LPC43xx devices.
	3	*
	4	* Copyright 2015 Joachim Eastwood <manabian@gmail.com>
	5	*
	6	* This code is released using a dual license strategy: BSD/GPL
	7	* You can choose the licence that better fits your requirements.
	8	*
	9	* Released under the terms of 3-clause BSD License
	10	* Released under the terms of GNU General Public License Version 2.0
	11	*
	12	*/
	13
	14	#include "armv7-m.dtsi"
	15
ba2db535 JE	16	#include "dt-bindings/clock/lpc18xx-cgu.h"
	17	#include "dt-bindings/clock/lpc18xx-ccu.h"
	18
7836dce4 JE	19	#define LPC_PIN(port, pin) (0x##port * 32 + pin)
	20	#define LPC_GPIO(port, pin) (port * 32 + pin)
	21
804a5dd6 JE	22	/ {
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	cpu@0 {
	28	compatible = "arm,cortex-m3";
	29	device_type = "cpu";
	30	reg = <0x0>;
ba2db535	31	clocks = <&ccu1 CLK_CPU_CORE>;
804a5dd6 JE	32	};
	33	};
	34
	35	clocks {
	36	xtal: xtal {
	37	compatible = "fixed-clock";
	38	#clock-cells = <0>;
	39	clock-frequency = <12000000>;
	40	};
	41
ba2db535 JE	42	xtal32: xtal32 {
	43	compatible = "fixed-clock";
	44	#clock-cells = <0>;
	45	clock-frequency = <32768>;
	46	};
	47
	48	enet_rx_clk: enet_rx_clk {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	clock-frequency = <0>;
	52	clock-output-names = "enet_rx_clk";
	53	};
	54
	55	enet_tx_clk: enet_tx_clk {
	56	compatible = "fixed-clock";
	57	#clock-cells = <0>;
	58	clock-frequency = <0>;
	59	clock-output-names = "enet_tx_clk";
	60	};
	61
	62	gp_clkin: gp_clkin {
	63	compatible = "fixed-clock";
804a5dd6	64	#clock-cells = <0>;
ba2db535 JE	65	clock-frequency = <0>;
ba2db535 JE	66	clock-output-names = "gp_clkin";
804a5dd6 JE	67	};
	68	};
	69
	70	soc {
cd07154f JE	71	mmcsd: mmcsd@40004000 {
	72	compatible = "snps,dw-mshc";
	73	reg = <0x40004000 0x1000>;
	74	interrupts = <6>;
	75	num-slots = <1>;
	76	clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
	77	clock-names = "ciu", "biu";
	78	status = "disabled";
	79	};
	80
ba2db535 JE	81	cgu: clock-controller@40050000 {
	82	compatible = "nxp,lpc1850-cgu";
	83	reg = <0x40050000 0x1000>;
	84	#clock-cells = <1>;
	85	clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
	86	};
	87
	88	ccu1: clock-controller@40051000 {
	89	compatible = "nxp,lpc1850-ccu";
	90	reg = <0x40051000 0x1000>;
	91	#clock-cells = <1>;
	92	clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
	93	<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
	94	<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
	95	<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
	96	clock-names = "base_apb3_clk", "base_apb1_clk",
	97	"base_spifi_clk", "base_cpu_clk",
	98	"base_periph_clk", "base_usb0_clk",
	99	"base_usb1_clk", "base_spi_clk";
	100	};
	101
	102	ccu2: clock-controller@40052000 {
	103	compatible = "nxp,lpc1850-ccu";
	104	reg = <0x40052000 0x1000>;
	105	#clock-cells = <1>;
	106	clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
	107	<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
	108	<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
	109	<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
	110	clock-names = "base_audio_clk", "base_uart3_clk",
	111	"base_uart2_clk", "base_uart1_clk",
	112	"base_uart0_clk", "base_ssp1_clk",
	113	"base_ssp0_clk", "base_sdio_clk";
	114	};
	115
804a5dd6	116	uart0: serial@40081000 {
f2b1c507	117	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	118	reg = <0x40081000 0x1000>;
	119	reg-shift = <2>;
	120	interrupts = <24>;
ba2db535	121	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
f2b1c507	122	clock-names = "uartclk", "reg";
804a5dd6 JE	123	status = "disabled";
	124	};
	125
	126	uart1: serial@40082000 {
f2b1c507	127	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	128	reg = <0x40082000 0x1000>;
	129	reg-shift = <2>;
	130	interrupts = <25>;
ba2db535	131	clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
f2b1c507	132	clock-names = "uartclk", "reg";
804a5dd6 JE	133	status = "disabled";
	134	};
	135
5d2ea79c JE	136	ssp0: spi@40083000 {
	137	compatible = "arm,pl022", "arm,primecell";
	138	reg = <0x40083000 0x1000>;
	139	interrupts = <22>;
	140	clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
	141	clock-names = "sspclk", "apb_pclk";
	142	#address-cells = <1>;
	143	#size-cells = <0>;
	144	status = "disabled";
	145	};
	146
804a5dd6 JE	147	timer0: timer@40084000 {
	148	compatible = "nxp,lpc3220-timer";
	149	reg = <0x40084000 0x1000>;
	150	interrupts = <12>;
ba2db535	151	clocks = <&ccu1 CLK_CPU_TIMER0>;
804a5dd6 JE	152	clock-names = "timerclk";
	153	};
	154
	155	timer1: timer@40085000 {
	156	compatible = "nxp,lpc3220-timer";
	157	reg = <0x40085000 0x1000>;
	158	interrupts = <13>;
ba2db535	159	clocks = <&ccu1 CLK_CPU_TIMER1>;
804a5dd6 JE	160	clock-names = "timerclk";
	161	};
	162
d881f5e2 JE	163	pinctrl: pinctrl@40086000 {
	164	compatible = "nxp,lpc1850-scu";
	165	reg = <0x40086000 0x1000>;
	166	clocks = <&ccu1 CLK_CPU_SCU>;
	167	};
	168
7e6c8376 JE	169	can1: can@400a4000 {
	170	compatible = "bosch,c_can";
	171	reg = <0x400a4000 0x1000>;
	172	interrupts = <43>;
	173	clocks = <&ccu1 CLK_APB1_CAN1>;
	174	status = "disabled";
	175	};
	176
804a5dd6	177	uart2: serial@400c1000 {
f2b1c507	178	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	179	reg = <0x400c1000 0x1000>;
	180	reg-shift = <2>;
	181	interrupts = <26>;
ba2db535	182	clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
f2b1c507	183	clock-names = "uartclk", "reg";
804a5dd6 JE	184	status = "disabled";
	185	};
	186
	187	uart3: serial@400c2000 {
f2b1c507	188	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	189	reg = <0x400c2000 0x1000>;
	190	reg-shift = <2>;
	191	interrupts = <27>;
ba2db535	192	clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
f2b1c507	193	clock-names = "uartclk", "reg";
804a5dd6 JE	194	status = "disabled";
	195	};
	196
	197	timer2: timer@400c3000 {
	198	compatible = "nxp,lpc3220-timer";
	199	reg = <0x400c3000 0x1000>;
	200	interrupts = <14>;
ba2db535	201	clocks = <&ccu1 CLK_CPU_TIMER2>;
804a5dd6 JE	202	clock-names = "timerclk";
	203	};
	204
	205	timer3: timer@400c4000 {
	206	compatible = "nxp,lpc3220-timer";
	207	reg = <0x400c4000 0x1000>;
	208	interrupts = <15>;
ba2db535	209	clocks = <&ccu1 CLK_CPU_TIMER3>;
804a5dd6 JE	210	clock-names = "timerclk";
804a5dd6 JE	211	};
7836dce4	212
5d2ea79c JE	213	ssp1: spi@400c5000 {
	214	compatible = "arm,pl022", "arm,primecell";
	215	reg = <0x400c5000 0x1000>;
	216	interrupts = <23>;
	217	clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
	218	clock-names = "sspclk", "apb_pclk";
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221	status = "disabled";
	222	};
	223
7e6c8376 JE	224	can0: can@400e2000 {
	225	compatible = "bosch,c_can";
	226	reg = <0x400e2000 0x1000>;
	227	interrupts = <51>;
	228	clocks = <&ccu1 CLK_APB3_CAN0>;
	229	status = "disabled";
	230	};
	231
7836dce4 JE	232	gpio: gpio@400f4000 {
	233	compatible = "nxp,lpc1850-gpio";
	234	reg = <0x400f4000 0x4000>;
	235	clocks = <&ccu1 CLK_CPU_GPIO>;
	236	gpio-controller;
	237	#gpio-cells = <2>;
	238	gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
	239	<&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
	240	<&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
	241	<&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
	242	<&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
	243	<&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
	244	<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
	245	<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
	246	<&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
	247	<&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
	248	<&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
	249	<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
	250	<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
	251	<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
	252	<&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
	253	<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
	254	<&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
	255	<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
	256	<&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
	257	<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
	258	<&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
	259	<&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
	260	<&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
	261	<&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
	262	<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
	263	<&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
	264	<&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
	265	<&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
	266	<&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
	267	<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
	268	<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
	269	<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
	270	<&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
	271	<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
	272	<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
	273	<&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
	274	<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
	275	<&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
	276	<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
	277	<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
	278	};
804a5dd6 JE	279	};
804a5dd6 JE	280	};