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e04920d9 RS |
1 | /* |
2 | * NXP LPC32xx SoC | |
3 | * | |
4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
1a24edd2 | 14 | #include "skeleton.dtsi" |
e04920d9 RS |
15 | |
16 | / { | |
17 | compatible = "nxp,lpc3220"; | |
18 | interrupt-parent = <&mic>; | |
19 | ||
20 | cpus { | |
246d8fc3 | 21 | #address-cells = <1>; |
73158b77 LP |
22 | #size-cells = <0>; |
23 | ||
246d8fc3 | 24 | cpu@0 { |
73158b77 LP |
25 | compatible = "arm,arm926ej-s"; |
26 | device_type = "cpu"; | |
246d8fc3 | 27 | reg = <0x0>; |
e04920d9 RS |
28 | }; |
29 | }; | |
30 | ||
31 | ahb { | |
32 | #address-cells = <1>; | |
33 | #size-cells = <1>; | |
34 | compatible = "simple-bus"; | |
f83ee67f VZ |
35 | ranges = <0x20000000 0x20000000 0x30000000>, |
36 | <0xe0000000 0xe0000000 0x04000000>; | |
e04920d9 RS |
37 | |
38 | /* | |
39 | * Enable either SLC or MLC | |
40 | */ | |
41 | slc: flash@20020000 { | |
42 | compatible = "nxp,lpc3220-slc"; | |
43 | reg = <0x20020000 0x1000>; | |
cb85a9e5 | 44 | status = "disabled"; |
e04920d9 RS |
45 | }; |
46 | ||
6d1c3e93 | 47 | mlc: flash@200a8000 { |
e04920d9 | 48 | compatible = "nxp,lpc3220-mlc"; |
6d1c3e93 RS |
49 | reg = <0x200a8000 0x11000>; |
50 | interrupts = <11 0>; | |
cb85a9e5 | 51 | status = "disabled"; |
e04920d9 RS |
52 | }; |
53 | ||
25de7c96 | 54 | dma: dma@31000000 { |
e04920d9 RS |
55 | compatible = "arm,pl080", "arm,primecell"; |
56 | reg = <0x31000000 0x1000>; | |
57 | interrupts = <0x1c 0>; | |
58 | }; | |
59 | ||
60 | /* | |
61 | * Enable either ohci or usbd (gadget)! | |
62 | */ | |
25de7c96 | 63 | ohci: ohci@31020000 { |
e04920d9 RS |
64 | compatible = "nxp,ohci-nxp", "usb-ohci"; |
65 | reg = <0x31020000 0x300>; | |
66 | interrupts = <0x3b 0>; | |
cb85a9e5 | 67 | status = "disabled"; |
e04920d9 RS |
68 | }; |
69 | ||
25de7c96 | 70 | usbd: usbd@31020000 { |
e04920d9 RS |
71 | compatible = "nxp,lpc3220-udc"; |
72 | reg = <0x31020000 0x300>; | |
73 | interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; | |
cb85a9e5 | 74 | status = "disabled"; |
e04920d9 RS |
75 | }; |
76 | ||
25de7c96 | 77 | clcd: clcd@31040000 { |
e04920d9 RS |
78 | compatible = "arm,pl110", "arm,primecell"; |
79 | reg = <0x31040000 0x1000>; | |
80 | interrupts = <0x0e 0>; | |
cb85a9e5 | 81 | status = "disabled"; |
e04920d9 RS |
82 | }; |
83 | ||
84 | mac: ethernet@31060000 { | |
85 | compatible = "nxp,lpc-eth"; | |
86 | reg = <0x31060000 0x1000>; | |
87 | interrupts = <0x1d 0>; | |
88 | }; | |
89 | ||
f83ee67f VZ |
90 | emc: memory-controller@31080000 { |
91 | compatible = "arm,pl175", "arm,primecell"; | |
92 | reg = <0x31080000 0x1000>; | |
93 | #address-cells = <1>; | |
94 | #size-cells = <1>; | |
95 | ||
96 | ranges = <0 0xe0000000 0x01000000>, | |
97 | <1 0xe1000000 0x01000000>, | |
98 | <2 0xe2000000 0x01000000>, | |
99 | <3 0xe3000000 0x01000000>; | |
100 | status = "disabled"; | |
101 | }; | |
102 | ||
e04920d9 RS |
103 | apb { |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | compatible = "simple-bus"; | |
107 | ranges = <0x20000000 0x20000000 0x30000000>; | |
108 | ||
109 | ssp0: ssp@20084000 { | |
110 | compatible = "arm,pl022", "arm,primecell"; | |
111 | reg = <0x20084000 0x1000>; | |
112 | interrupts = <0x14 0>; | |
113 | }; | |
114 | ||
115 | spi1: spi@20088000 { | |
116 | compatible = "nxp,lpc3220-spi"; | |
117 | reg = <0x20088000 0x1000>; | |
118 | }; | |
119 | ||
120 | ssp1: ssp@2008c000 { | |
121 | compatible = "arm,pl022", "arm,primecell"; | |
122 | reg = <0x2008c000 0x1000>; | |
123 | interrupts = <0x15 0>; | |
124 | }; | |
125 | ||
126 | spi2: spi@20090000 { | |
127 | compatible = "nxp,lpc3220-spi"; | |
128 | reg = <0x20090000 0x1000>; | |
129 | }; | |
130 | ||
131 | i2s0: i2s@20094000 { | |
132 | compatible = "nxp,lpc3220-i2s"; | |
133 | reg = <0x20094000 0x1000>; | |
134 | }; | |
135 | ||
25de7c96 | 136 | sd: sd@20098000 { |
2c7fa286 | 137 | compatible = "arm,pl18x", "arm,primecell"; |
e04920d9 RS |
138 | reg = <0x20098000 0x1000>; |
139 | interrupts = <0x0f 0>, <0x0d 0>; | |
2c7fa286 | 140 | status = "disabled"; |
e04920d9 RS |
141 | }; |
142 | ||
143 | i2s1: i2s@2009C000 { | |
144 | compatible = "nxp,lpc3220-i2s"; | |
145 | reg = <0x2009C000 0x1000>; | |
146 | }; | |
147 | ||
c70426f1 RS |
148 | /* UART5 first since it is the default console, ttyS0 */ |
149 | uart5: serial@40090000 { | |
150 | /* actually, ns16550a w/ 64 byte fifos! */ | |
151 | compatible = "nxp,lpc3220-uart"; | |
152 | reg = <0x40090000 0x1000>; | |
153 | interrupts = <9 0>; | |
154 | clock-frequency = <13000000>; | |
155 | reg-shift = <2>; | |
156 | status = "disabled"; | |
157 | }; | |
158 | ||
e04920d9 | 159 | uart3: serial@40080000 { |
c70426f1 | 160 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 161 | reg = <0x40080000 0x1000>; |
c70426f1 RS |
162 | interrupts = <7 0>; |
163 | clock-frequency = <13000000>; | |
164 | reg-shift = <2>; | |
165 | status = "disabled"; | |
e04920d9 RS |
166 | }; |
167 | ||
168 | uart4: serial@40088000 { | |
c70426f1 | 169 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 170 | reg = <0x40088000 0x1000>; |
c70426f1 RS |
171 | interrupts = <8 0>; |
172 | clock-frequency = <13000000>; | |
173 | reg-shift = <2>; | |
174 | status = "disabled"; | |
e04920d9 RS |
175 | }; |
176 | ||
177 | uart6: serial@40098000 { | |
c70426f1 | 178 | compatible = "nxp,lpc3220-uart"; |
e04920d9 | 179 | reg = <0x40098000 0x1000>; |
c70426f1 RS |
180 | interrupts = <10 0>; |
181 | clock-frequency = <13000000>; | |
182 | reg-shift = <2>; | |
183 | status = "disabled"; | |
e04920d9 RS |
184 | }; |
185 | ||
186 | i2c1: i2c@400A0000 { | |
187 | compatible = "nxp,pnx-i2c"; | |
188 | reg = <0x400A0000 0x100>; | |
189 | interrupts = <0x33 0>; | |
190 | #address-cells = <1>; | |
191 | #size-cells = <0>; | |
192 | pnx,timeout = <0x64>; | |
193 | }; | |
194 | ||
195 | i2c2: i2c@400A8000 { | |
196 | compatible = "nxp,pnx-i2c"; | |
197 | reg = <0x400A8000 0x100>; | |
198 | interrupts = <0x32 0>; | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | pnx,timeout = <0x64>; | |
202 | }; | |
203 | ||
b7d41c93 AB |
204 | mpwm: mpwm@400E8000 { |
205 | compatible = "nxp,lpc3220-motor-pwm"; | |
206 | reg = <0x400E8000 0x78>; | |
207 | status = "disabled"; | |
208 | #pwm-cells = <2>; | |
209 | }; | |
210 | ||
e04920d9 RS |
211 | i2cusb: i2c@31020300 { |
212 | compatible = "nxp,pnx-i2c"; | |
213 | reg = <0x31020300 0x100>; | |
214 | interrupts = <0x3f 0>; | |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
217 | pnx,timeout = <0x64>; | |
218 | }; | |
219 | }; | |
220 | ||
221 | fab { | |
222 | #address-cells = <1>; | |
223 | #size-cells = <1>; | |
224 | compatible = "simple-bus"; | |
225 | ranges = <0x20000000 0x20000000 0x30000000>; | |
226 | ||
227 | /* | |
228 | * MIC Interrupt controller includes: | |
229 | * MIC @40008000 | |
230 | * SIC1 @4000C000 | |
231 | * SIC2 @40010000 | |
232 | */ | |
233 | mic: interrupt-controller@40008000 { | |
234 | compatible = "nxp,lpc3220-mic"; | |
235 | interrupt-controller; | |
236 | reg = <0x40008000 0xC000>; | |
237 | #interrupt-cells = <2>; | |
238 | }; | |
239 | ||
240 | uart1: serial@40014000 { | |
ac5ced91 | 241 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 242 | reg = <0x40014000 0x1000>; |
ac5ced91 RS |
243 | interrupts = <26 0>; |
244 | status = "disabled"; | |
e04920d9 RS |
245 | }; |
246 | ||
247 | uart2: serial@40018000 { | |
ac5ced91 | 248 | compatible = "nxp,lpc3220-hsuart"; |
e04920d9 | 249 | reg = <0x40018000 0x1000>; |
ac5ced91 RS |
250 | interrupts = <25 0>; |
251 | status = "disabled"; | |
e04920d9 RS |
252 | }; |
253 | ||
ac5ced91 RS |
254 | uart7: serial@4001c000 { |
255 | compatible = "nxp,lpc3220-hsuart"; | |
256 | reg = <0x4001c000 0x1000>; | |
257 | interrupts = <24 0>; | |
258 | status = "disabled"; | |
e04920d9 RS |
259 | }; |
260 | ||
25de7c96 | 261 | rtc: rtc@40024000 { |
e04920d9 RS |
262 | compatible = "nxp,lpc3220-rtc"; |
263 | reg = <0x40024000 0x1000>; | |
264 | interrupts = <0x34 0>; | |
265 | }; | |
266 | ||
267 | gpio: gpio@40028000 { | |
268 | compatible = "nxp,lpc3220-gpio"; | |
269 | reg = <0x40028000 0x1000>; | |
a035254a RS |
270 | gpio-controller; |
271 | #gpio-cells = <3>; /* bank, pin, flags */ | |
e04920d9 RS |
272 | }; |
273 | ||
25de7c96 | 274 | watchdog: watchdog@4003C000 { |
e04920d9 RS |
275 | compatible = "nxp,pnx4008-wdt"; |
276 | reg = <0x4003C000 0x1000>; | |
277 | }; | |
278 | ||
279 | /* | |
280 | * TSC vs. ADC: Since those two share the same | |
281 | * hardware, you need to choose from one of the | |
282 | * following two and do 'status = "okay";' for one of | |
283 | * them | |
284 | */ | |
285 | ||
25de7c96 | 286 | adc: adc@40048000 { |
e04920d9 RS |
287 | compatible = "nxp,lpc3220-adc"; |
288 | reg = <0x40048000 0x1000>; | |
289 | interrupts = <0x27 0>; | |
cb85a9e5 | 290 | status = "disabled"; |
e04920d9 RS |
291 | }; |
292 | ||
25de7c96 | 293 | tsc: tsc@40048000 { |
e04920d9 RS |
294 | compatible = "nxp,lpc3220-tsc"; |
295 | reg = <0x40048000 0x1000>; | |
296 | interrupts = <0x27 0>; | |
cb85a9e5 | 297 | status = "disabled"; |
e04920d9 RS |
298 | }; |
299 | ||
25de7c96 | 300 | key: key@40050000 { |
e04920d9 RS |
301 | compatible = "nxp,lpc3220-key"; |
302 | reg = <0x40050000 0x1000>; | |
a6d1be0e RS |
303 | interrupts = <54 0>; |
304 | status = "disabled"; | |
e04920d9 RS |
305 | }; |
306 | ||
2a6c6563 | 307 | pwm1: pwm@4005C000 { |
de639854 | 308 | compatible = "nxp,lpc3220-pwm"; |
2a6c6563 VZ |
309 | reg = <0x4005C000 0x4>; |
310 | status = "disabled"; | |
311 | }; | |
312 | ||
313 | pwm2: pwm@4005C004 { | |
314 | compatible = "nxp,lpc3220-pwm"; | |
315 | reg = <0x4005C004 0x4>; | |
de639854 APS |
316 | status = "disabled"; |
317 | }; | |
e04920d9 RS |
318 | }; |
319 | }; | |
320 | }; |