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ARM: dts: lpc4350-hitex-eval: add i2c0 and devices
[deliverable/linux.git] / arch / arm / boot / dts / lpc4350-hitex-eval.dts
CommitLineData
7dfc6358
AA		 1/*
2 * Hitex LPC4350 Evaluation Board
3 *
4 * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
5 *
6 * This code is released using a dual license strategy: BSD/GPL
7 * You can choose the licence that better fits your requirements.
8 *
9 * Released under the terms of 3-clause BSD License
10 * Released under the terms of GNU General Public License Version 2.0
11 *
12 */
13/dts-v1/;
14
15#include "lpc18xx.dtsi"
16#include "lpc4350.dtsi"
17
18/ {
19 model = "Hitex LPC4350 Evaluation Board";
20 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
21
22 aliases {
23 serial0 = &uart0;
24 serial1 = &uart1;
25 serial2 = &uart2;
26 serial3 = &uart3;
27 };
28
29 chosen {
30 stdout-path = &uart0;
31 };
32
33 memory {
34 device_type = "memory";
35 reg = <0x28000000 0x800000>; /* 8 MB */
36 };
37};
38
5e647200 39&pinctrl {
027b4a6d
JE		 40 emc_pins: emc-pins {
41 emc_addr0_23_cfg {
42 pins = "p2_9", "p2_10", "p2_11", "p2_12",
43 "p2_13", "p1_0", "p1_1", "p1_2",
44 "p2_8", "p2_7", "p2_6", "p2_2",
45 "p2_1", "p2_0", "p6_8", "p6_7",
46 "pd_16", "pd_15", "pe_0", "pe_1",
47 "pe_2", "pe_3", "pe_4", "pa_4";
48 function = "emc";
49 slew-rate = <1>;
50 bias-disable;
51 input-enable;
52 input-schmitt-disable;
53 };
54
55 emc_data0_15_cfg {
56 pins = "p1_7", "p1_8", "p1_9", "p1_10",
57 "p1_11", "p1_12", "p1_13", "p1_14",
58 "p5_4", "p5_5", "p5_6", "p5_7",
59 "p5_0", "p5_1", "p5_2", "p5_3";
60 function = "emc";
61 slew-rate = <1>;
62 bias-disable;
63 input-enable;
64 input-schmitt-disable;
65 };
66
67 emc_we_oe_cfg {
68 pins = "p1_6", "p1_3";
69 function = "emc";
70 slew-rate = <1>;
71 bias-disable;
72 input-enable;
73 input-schmitt-disable;
74 };
75
76 emc_bls0_3_cfg {
77 pins = "p1_4", "p6_6", "pd_13", "pd_10";
78 function = "emc";
79 slew-rate = <1>;
80 bias-disable;
81 input-enable;
82 input-schmitt-disable;
83 };
84
85 emc_cs0_cs2_cfg {
86 pins = "p1_5", "pd_12";
87 function = "emc";
88 slew-rate = <1>;
89 bias-disable;
90 input-enable;
91 input-schmitt-disable;
92 };
93
94 emc_sdram_dqm0_3_cfg {
95 pins = "p6_12", "p6_10", "pd_0", "pe_13";
96 function = "emc";
97 slew-rate = <1>;
98 bias-disable;
99 input-enable;
100 input-schmitt-disable;
101 };
102
103 emc_sdram_ras_cas_cfg {
104 pins = "p6_5", "p6_4";
105 function = "emc";
106 slew-rate = <1>;
107 bias-disable;
108 input-enable;
109 input-schmitt-disable;
110 };
111
112 emc_sdram_dycs0_cfg {
113 pins = "p6_9";
114 function = "emc";
115 slew-rate = <1>;
116 bias-disable;
117 input-enable;
118 input-schmitt-disable;
119 };
120
121 emc_sdram_cke_cfg {
122 pins = "p6_11";
123 function = "emc";
124 slew-rate = <1>;
125 bias-disable;
126 input-enable;
127 input-schmitt-disable;
128 };
129
130 emc_sdram_clock_cfg {
131 pins = "clk0", "clk1", "clk2", "clk3";
132 function = "emc";
133 slew-rate = <1>;
134 bias-disable;
135 input-enable;
136 input-schmitt-disable;
137 };
138 };
139
aceacfa6
AA		 140 enet_mii_pins: enet-mii-pins {
141 enet_mii_rxd0_3_cfg {
142 pins = "p1_15", "p0_0", "p9_3", "p9_2";
143 function = "enet";
144 bias-disable;
145 input-enable;
146 };
147
148 enet_mii_txd0_3_cfg {
149 pins = "p1_18", "p1_20", "p9_4", "p9_5";
150 function = "enet";
151 bias-disable;
152 };
153
154 enet_mii_crs_col_cfg {
155 pins = "p9_0", "p9_6";
156 function = "enet";
157 bias-disable;
158 input-enable;
159 };
160
161 enet_mii_rx_clk_dv_er_cfg {
162 pins = "pc_0", "p1_16", "p9_1";
163 function = "enet";
164 bias-disable;
165 input-enable;
166 };
167
168 enet_mii_tx_clk_en_cfg {
169 pins = "p1_19", "p0_1";
170 function = "enet";
171 bias-disable;
172 input-enable;
173 };
174
175 enet_mdio_cfg {
176 pins = "p1_17";
177 function = "enet";
178 bias-disable;
179 input-enable;
180 };
181
182 enet_mdc_cfg {
183 pins = "pc_1";
184 function = "enet";
185 bias-disable;
186 };
187 };
188
67b17a11
AA		 189 i2c0_pins: i2c0-pins {
190 i2c0_pins_cfg {
191 pins = "i2c0_scl", "i2c0_sda";
192 function = "i2c0";
193 input-enable;
194 };
195 };
196
474ae430
JE		 197 spifi_pins: spifi-pins {
198 spifi_clk_cfg {
199 pins = "p3_3";
200 function = "spifi";
201 slew-rate = <1>;
202 bias-disable;
203 input-enable;
204 input-schmitt-disable;
205 };
206
207 spifi_mosi_miso_sio2_3_cfg {
208 pins = "p3_7", "p3_6", "p3_5", "p3_4";
209 function = "spifi";
210 slew-rate = <1>;
211 bias-disable;
212 input-enable;
213 input-schmitt-disable;
214 };
215
216 spifi_cs_cfg {
217 pins = "p3_8";
218 function = "spifi";
219 slew-rate = <1>;
220 bias-disable;
221 input-enable;
222 input-schmitt-disable;
223 };
224 };
225
5e647200
AA		 226 uart0_pins: uart0-pins {
227 uart0_rx_cfg {
228 pins = "pf_11";
229 function = "uart0";
230 input-schmitt-disable;
231 bias-disable;
232 input-enable;
233 };
234
235 uart0_tx_cfg {
236 pins = "pf_10";
237 function = "uart0";
238 bias-pull-down;
239 };
240 };
241};
242
027b4a6d
JE		 243&emc {
244 status = "okay";
245 pinctrl-names = "default";
246 pinctrl-0 = <&emc_pins>;
247
248 cs0 {
249 #address-cells = <2>;
250 #size-cells = <1>;
251 ranges;
252
253 mpmc,cs = <0>;
254 mpmc,memory-width = <16>;
255 mpmc,byte-lane-low;
256 mpmc,write-enable-delay = <0>;
257 mpmc,output-enable-delay = <0>;
258 mpmc,read-access-delay = <70>;
259 mpmc,page-mode-read-delay = <70>;
260
261 flash@0,0 {
262 compatible = "sst,sst39vf320", "cfi-flash";
263 reg = <0 0 0x400000>;
264 bank-width = <2>;
265 #address-cells = <1>;
266 #size-cells = <1>;
267
268 partition@0 {
269 label = "bootloader";
270 reg = <0x000000 0x040000>; /* 256 KiB */
271 };
272
273 partition@1 {
274 label = "kernel";
275 reg = <0x040000 0x2C0000>; /* 2.75 MiB */
276 };
277
278 partition@2 {
279 label = "rootfs";
280 reg = <0x300000 0x100000>; /* 1 MiB */
281 };
282 };
283 };
284
285 cs2 {
286 #address-cells = <2>;
287 #size-cells = <1>;
288 ranges;
289
290 mpmc,cs = <2>;
291 mpmc,memory-width = <16>;
292 mpmc,byte-lane-low;
293 mpmc,write-enable-delay = <0>;
294 mpmc,output-enable-delay = <30>;
295 mpmc,read-access-delay = <90>;
296 mpmc,page-mode-read-delay = <55>;
297 mpmc,write-access-delay = <55>;
298 mpmc,turn-round-delay = <55>;
299
300 ext_sram: sram@2,0 {
301 compatible = "mmio-sram";
302 reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
303 };
304 };
305};
306
aceacfa6
AA		 307&enet_tx_clk {
308 clock-frequency = <25000000>;
309};
310
67b17a11
AA		 311&i2c0 {
312 status = "okay";
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c0_pins>;
315 clock-frequency = <400000>;
316
317 /* NXP SE97BTP with temperature sensor + eeprom */
318 sensor@18 {
319 compatible = "nxp,jc42";
320 reg = <0x18>;
321 };
322
323 eeprom@50 {
324 compatible = "nxp,24c02";
325 reg = <0x50>;
326 };
327
328 pca_gpio: gpio@24 {
329 compatible = "nxp,pca9673";
330 reg = <0x24>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 };
334};
335
aceacfa6
AA		 336&mac {
337 status = "okay";
338 phy-mode = "mii";
339 pinctrl-names = "default";
340 pinctrl-0 = <&enet_mii_pins>;
341};
342
474ae430
JE		 343&spifi {
344 status = "okay";
345 pinctrl-names = "default";
346 pinctrl-0 = <&spifi_pins>;
347
348 flash@0 {
349 compatible = "jedec,spi-nor";
350 spi-rx-bus-width = <4>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353
354 partition@0 {
355 label = "bootloader";
356 reg = <0x000000 0x040000>; /* 256 KiB */
357 };
358
359 partition@1 {
360 label = "kernel";
361 reg = <0x040000 0x2c0000>; /* 2.75 MiB */
362 };
363
364 partition@2 {
365 label = "rootfs";
366 reg = <0x300000 0x500000>; /* 5 MiB */
367 };
368 };
369};
370
7dfc6358
AA		 371&uart0 {
372 status = "okay";
5e647200
AA		 373 pinctrl-names = "default";
374 pinctrl-0 = <&uart0_pins>;
7dfc6358 375};
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