projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7dfc6358 AA |
1 | /* |
| 2 | * Hitex LPC4350 Evaluation Board | |
| 3 | * | |
| 4 | * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> | |
| 5 | * | |
| 6 | * This code is released using a dual license strategy: BSD/GPL | |
| 7 | * You can choose the licence that better fits your requirements. | |
| 8 | * | |
| 9 | * Released under the terms of 3-clause BSD License | |
| 10 | * Released under the terms of GNU General Public License Version 2.0 | |
| 11 | * | |
| 12 | */ | |
| 13 | /dts-v1/; | |
| 14 | ||
| 15 | #include "lpc18xx.dtsi" | |
| 16 | #include "lpc4350.dtsi" | |
| 17 | ||
| 18 | / { | |
| 19 | model = "Hitex LPC4350 Evaluation Board"; | |
| 20 | compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350"; | |
| 21 | ||
| 22 | aliases { | |
| 23 | serial0 = &uart0; | |
| 24 | serial1 = &uart1; | |
| 25 | serial2 = &uart2; | |
| 26 | serial3 = &uart3; | |
| 27 | }; | |
| 28 | ||
| 29 | chosen { | |
| 30 | stdout-path = &uart0; | |
| 31 | }; | |
| 32 | ||
| 33 | memory { | |
| 34 | device_type = "memory"; | |
| 35 | reg = <0x28000000 0x800000>; /* 8 MB */ | |
| 36 | }; | |
| 37 | }; | |
| 38 | ||
| 5e647200 | 39 | &pinctrl { |
| aceacfa6 AA |
40 | enet_mii_pins: enet-mii-pins { |
| 41 | enet_mii_rxd0_3_cfg { | |
| 42 | pins = "p1_15", "p0_0", "p9_3", "p9_2"; | |
| 43 | function = "enet"; | |
| 44 | bias-disable; | |
| 45 | input-enable; | |
| 46 | }; | |
| 47 | ||
| 48 | enet_mii_txd0_3_cfg { | |
| 49 | pins = "p1_18", "p1_20", "p9_4", "p9_5"; | |
| 50 | function = "enet"; | |
| 51 | bias-disable; | |
| 52 | }; | |
| 53 | ||
| 54 | enet_mii_crs_col_cfg { | |
| 55 | pins = "p9_0", "p9_6"; | |
| 56 | function = "enet"; | |
| 57 | bias-disable; | |
| 58 | input-enable; | |
| 59 | }; | |
| 60 | ||
| 61 | enet_mii_rx_clk_dv_er_cfg { | |
| 62 | pins = "pc_0", "p1_16", "p9_1"; | |
| 63 | function = "enet"; | |
| 64 | bias-disable; | |
| 65 | input-enable; | |
| 66 | }; | |
| 67 | ||
| 68 | enet_mii_tx_clk_en_cfg { | |
| 69 | pins = "p1_19", "p0_1"; | |
| 70 | function = "enet"; | |
| 71 | bias-disable; | |
| 72 | input-enable; | |
| 73 | }; | |
| 74 | ||
| 75 | enet_mdio_cfg { | |
| 76 | pins = "p1_17"; | |
| 77 | function = "enet"; | |
| 78 | bias-disable; | |
| 79 | input-enable; | |
| 80 | }; | |
| 81 | ||
| 82 | enet_mdc_cfg { | |
| 83 | pins = "pc_1"; | |
| 84 | function = "enet"; | |
| 85 | bias-disable; | |
| 86 | }; | |
| 87 | }; | |
| 88 | ||
| 5e647200 AA |
89 | uart0_pins: uart0-pins { |
| 90 | uart0_rx_cfg { | |
| 91 | pins = "pf_11"; | |
| 92 | function = "uart0"; | |
| 93 | input-schmitt-disable; | |
| 94 | bias-disable; | |
| 95 | input-enable; | |
| 96 | }; | |
| 97 | ||
| 98 | uart0_tx_cfg { | |
| 99 | pins = "pf_10"; | |
| 100 | function = "uart0"; | |
| 101 | bias-pull-down; | |
| 102 | }; | |
| 103 | }; | |
| 104 | }; | |
| 105 | ||
| aceacfa6 AA |
106 | &enet_tx_clk { |
| 107 | clock-frequency = <25000000>; | |
| 108 | }; | |
| 109 | ||
| 110 | &mac { | |
| 111 | status = "okay"; | |
| 112 | phy-mode = "mii"; | |
| 113 | pinctrl-names = "default"; | |
| 114 | pinctrl-0 = <&enet_mii_pins>; | |
| 115 | }; | |
| 116 | ||
| 7dfc6358 AA |
117 | &uart0 { |
| 118 | status = "okay"; | |
| 5e647200 AA |
119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&uart0_pins>; | |
| 7dfc6358 | 121 | }; |