[deliverable/linux.git] / arch / arm / boot / dts / mt2701.dtsi

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Erin.Lo <erin.lo@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"

/ {
	compatible = "mediatek,mt2701";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	pio: pinctrl@10005000 {
		compatible = "mediatek,mt2701-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt2701-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt2701-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt2701-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x1000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};
};
Commit	Line	Data
74d25721 EL	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Erin.Lo <erin.lo@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <dt-bindings/interrupt-controller/irq.h>
	16	#include <dt-bindings/interrupt-controller/arm-gic.h>
	17	#include "skeleton64.dtsi"
8369337e	18	#include "mt2701-pinfunc.h"
74d25721 EL	19
	20	/ {
	21	compatible = "mediatek,mt2701";
	22	interrupt-parent = <&sysirq>;
	23
	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
dfb89528	27	enable-method = "mediatek,mt81xx-tz-smp";
74d25721 EL	28
	29	cpu@0 {
	30	device_type = "cpu";
	31	compatible = "arm,cortex-a7";
	32	reg = <0x0>;
	33	};
	34	cpu@1 {
	35	device_type = "cpu";
	36	compatible = "arm,cortex-a7";
	37	reg = <0x1>;
	38	};
	39	cpu@2 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a7";
	42	reg = <0x2>;
	43	};
	44	cpu@3 {
	45	device_type = "cpu";
	46	compatible = "arm,cortex-a7";
	47	reg = <0x3>;
	48	};
	49	};
	50
dfb89528 LY	51	reserved-memory {
	52	#address-cells = <2>;
	53	#size-cells = <2>;
	54	ranges;
	55
	56	trustzone-bootinfo@80002000 {
	57	compatible = "mediatek,trustzone-bootinfo";
	58	reg = <0 0x80002000 0 0x1000>;
	59	};
	60	};
	61
74d25721 EL	62	system_clk: dummy13m {
	63	compatible = "fixed-clock";
	64	clock-frequency = <13000000>;
	65	#clock-cells = <0>;
	66	};
	67
	68	rtc_clk: dummy32k {
	69	compatible = "fixed-clock";
	70	clock-frequency = <32000>;
	71	#clock-cells = <0>;
	72	};
	73
	74	uart_clk: dummy26m {
	75	compatible = "fixed-clock";
	76	clock-frequency = <26000000>;
	77	#clock-cells = <0>;
	78	};
	79
	80	timer {
	81	compatible = "arm,armv7-timer";
	82	interrupt-parent = <&gic>;
	83	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	84	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	85	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	86	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	87	};
	88
8369337e BH	89	pio: pinctrl@10005000 {
	90	compatible = "mediatek,mt2701-pinctrl";
	91	reg = <0 0x1000b000 0 0x1000>;
	92	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	93	pins-are-numbered;
	94	gpio-controller;
	95	#gpio-cells = <2>;
	96	interrupt-controller;
	97	#interrupt-cells = <2>;
	98	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	99	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	100	};
	101
	102	syscfg_pctl_a: syscfg@10005000 {
	103	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	104	reg = <0 0x10005000 0 0x1000>;
	105	};
	106
74d25721 EL	107	watchdog: watchdog@10007000 {
	108	compatible = "mediatek,mt2701-wdt",
	109	"mediatek,mt6589-wdt";
	110	reg = <0 0x10007000 0 0x100>;
	111	};
	112
	113	timer: timer@10008000 {
	114	compatible = "mediatek,mt2701-timer",
	115	"mediatek,mt6577-timer";
	116	reg = <0 0x10008000 0 0x80>;
	117	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	118	clocks = <&system_clk>, <&rtc_clk>;
	119	clock-names = "system-clk", "rtc-clk";
	120	};
	121
	122	sysirq: interrupt-controller@10200100 {
	123	compatible = "mediatek,mt2701-sysirq",
	124	"mediatek,mt6577-sysirq";
	125	interrupt-controller;
	126	#interrupt-cells = <3>;
	127	interrupt-parent = <&gic>;
	128	reg = <0 0x10200100 0 0x1c>;
	129	};
	130
	131	gic: interrupt-controller@10211000 {
	132	compatible = "arm,cortex-a7-gic";
	133	interrupt-controller;
	134	#interrupt-cells = <3>;
	135	interrupt-parent = <&gic>;
	136	reg = <0 0x10211000 0 0x1000>,
	137	<0 0x10212000 0 0x1000>,
	138	<0 0x10214000 0 0x2000>,
	139	<0 0x10216000 0 0x2000>;
	140	};
	141
	142	uart0: serial@11002000 {
	143	compatible = "mediatek,mt2701-uart",
	144	"mediatek,mt6577-uart";
	145	reg = <0 0x11002000 0 0x400>;
	146	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	147	clocks = <&uart_clk>;
	148	status = "disabled";
	149	};
	150
	151	uart1: serial@11003000 {
	152	compatible = "mediatek,mt2701-uart",
	153	"mediatek,mt6577-uart";
	154	reg = <0 0x11003000 0 0x400>;
	155	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	156	clocks = <&uart_clk>;
	157	status = "disabled";
	158	};
	159
	160	uart2: serial@11004000 {
	161	compatible = "mediatek,mt2701-uart",
	162	"mediatek,mt6577-uart";
	163	reg = <0 0x11004000 0 0x400>;
	164	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
	165	clocks = <&uart_clk>;
	166	status = "disabled";
	167	};
	168
	169	uart3: serial@11005000 {
	170	compatible = "mediatek,mt2701-uart",
171	"mediatek,mt6577-uart";
172	reg = <0 0x11005000 0 0x400>;
173	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
174	clocks = <&uart_clk>;
175	status = "disabled";
176	};
177	};