projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0c3fb203 J |
1 | /* |
| 2 | * Copyright (c) 2014 MediaTek Inc. | |
| 3 | * Author: Joe.C <yingjoe.chen@mediatek.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License version 2 as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 17 | #include "skeleton64.dtsi" | |
| 18 | ||
| 19 | / { | |
| 20 | compatible = "mediatek,mt8135"; | |
| e0bed077 | 21 | interrupt-parent = <&sysirq>; |
| 0c3fb203 J |
22 | |
| 23 | cpu-map { | |
| 24 | cluster0 { | |
| 25 | core0 { | |
| 26 | cpu = <&cpu0>; | |
| 27 | }; | |
| 28 | core1 { | |
| 29 | cpu = <&cpu1>; | |
| 30 | }; | |
| 31 | }; | |
| 32 | ||
| 33 | cluster1 { | |
| 34 | core0 { | |
| 35 | cpu = <&cpu2>; | |
| 36 | }; | |
| 37 | core1 { | |
| 38 | cpu = <&cpu3>; | |
| 39 | }; | |
| 40 | }; | |
| 41 | }; | |
| 42 | ||
| 43 | cpus { | |
| 44 | #address-cells = <1>; | |
| 45 | #size-cells = <0>; | |
| 46 | ||
| 47 | cpu0: cpu@0 { | |
| 48 | device_type = "cpu"; | |
| 49 | compatible = "arm,cortex-a7"; | |
| 50 | reg = <0x000>; | |
| 51 | }; | |
| 52 | ||
| 53 | cpu1: cpu@1 { | |
| 54 | device_type = "cpu"; | |
| 55 | compatible = "arm,cortex-a7"; | |
| 56 | reg = <0x001>; | |
| 57 | }; | |
| 58 | ||
| 59 | cpu2: cpu@100 { | |
| 60 | device_type = "cpu"; | |
| 61 | compatible = "arm,cortex-a15"; | |
| 62 | reg = <0x100>; | |
| 63 | }; | |
| 64 | ||
| 65 | cpu3: cpu@101 { | |
| 66 | device_type = "cpu"; | |
| 67 | compatible = "arm,cortex-a15"; | |
| 68 | reg = <0x101>; | |
| 69 | }; | |
| 70 | }; | |
| 71 | ||
| 72 | clocks { | |
| 73 | #address-cells = <2>; | |
| 74 | #size-cells = <2>; | |
| 75 | compatible = "simple-bus"; | |
| 76 | ranges; | |
| 77 | ||
| 78 | system_clk: dummy13m { | |
| 79 | compatible = "fixed-clock"; | |
| 80 | clock-frequency = <13000000>; | |
| 81 | #clock-cells = <0>; | |
| 82 | }; | |
| 83 | ||
| 84 | rtc_clk: dummy32k { | |
| 85 | compatible = "fixed-clock"; | |
| 86 | clock-frequency = <32000>; | |
| 87 | #clock-cells = <0>; | |
| 88 | }; | |
| 07149473 EH |
89 | |
| 90 | uart_clk: dummy26m { | |
| 91 | compatible = "fixed-clock"; | |
| 92 | clock-frequency = <26000000>; | |
| 93 | #clock-cells = <0>; | |
| 94 | }; | |
| 95 | ||
| 0c3fb203 J |
96 | }; |
| 97 | ||
| 98 | soc { | |
| 99 | #address-cells = <2>; | |
| 100 | #size-cells = <2>; | |
| 101 | compatible = "simple-bus"; | |
| 102 | ranges; | |
| 103 | ||
| 104 | timer: timer@10008000 { | |
| 105 | compatible = "mediatek,mt8135-timer", | |
| 106 | "mediatek,mt6577-timer"; | |
| 107 | reg = <0 0x10008000 0 0x80>; | |
| e0bed077 | 108 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; |
| 0c3fb203 J |
109 | clocks = <&system_clk>, <&rtc_clk>; |
| 110 | clock-names = "system-clk", "rtc-clk"; | |
| 111 | }; | |
| 112 | ||
| e0bed077 YC |
113 | sysirq: interrupt-controller@10200030 { |
| 114 | compatible = "mediatek,mt8135-sysirq", | |
| 115 | "mediatek,mt6577-sysirq"; | |
| 116 | interrupt-controller; | |
| 117 | #interrupt-cells = <3>; | |
| 118 | interrupt-parent = <&gic>; | |
| 119 | reg = <0 0x10200030 0 0x1c>; | |
| 120 | }; | |
| 121 | ||
| 0c3fb203 J |
122 | gic: interrupt-controller@10211000 { |
| 123 | compatible = "arm,cortex-a15-gic"; | |
| 124 | interrupt-controller; | |
| 125 | #interrupt-cells = <3>; | |
| e0bed077 | 126 | interrupt-parent = <&gic>; |
| 0c3fb203 J |
127 | reg = <0 0x10211000 0 0x1000>, |
| 128 | <0 0x10212000 0 0x1000>, | |
| 129 | <0 0x10214000 0 0x2000>, | |
| 130 | <0 0x10216000 0 0x2000>; | |
| 131 | }; | |
| 07149473 EH |
132 | |
| 133 | uart0: serial@11006000 { | |
| 134 | compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; | |
| 135 | reg = <0 0x11006000 0 0x400>; | |
| 136 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | |
| 137 | clocks = <&uart_clk>; | |
| 138 | status = "disabled"; | |
| 139 | }; | |
| 140 | ||
| 141 | uart1: serial@11007000 { | |
| 142 | compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; | |
| 143 | reg = <0 0x11007000 0 0x400>; | |
| 144 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; | |
| 145 | clocks = <&uart_clk>; | |
| 146 | status = "disabled"; | |
| 147 | }; | |
| 148 | ||
| 149 | uart2: serial@11008000 { | |
| 150 | compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; | |
| 151 | reg = <0 0x11008000 0 0x400>; | |
| 152 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; | |
| 153 | clocks = <&uart_clk>; | |
| 154 | status = "disabled"; | |
| 155 | }; | |
| 156 | ||
| 157 | uart3: serial@11009000 { | |
| 158 | compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart"; | |
| 159 | reg = <0 0x11009000 0 0x400>; | |
| 160 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; | |
| 161 | clocks = <&uart_clk>; | |
| 162 | status = "disabled"; | |
| 163 | }; | |
| 164 | ||
| 0c3fb203 J |
165 | }; |
| 166 | }; |