Commit | Line | Data |
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3f187f82 PU |
1 | /* |
2 | * Device Tree Source for OMAP2420 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
98ef7957 | 11 | #include "omap2.dtsi" |
3f187f82 PU |
12 | |
13 | / { | |
14 | compatible = "ti,omap2420", "ti,omap2"; | |
15 | ||
16 | ocp { | |
510c0ffd JH |
17 | counter32k: counter@48004000 { |
18 | compatible = "ti,omap-counter32k"; | |
19 | reg = <0x48004000 0x20>; | |
20 | ti,hwmods = "counter_32k"; | |
21 | }; | |
22 | ||
679e3310 TL |
23 | omap2420_pmx: pinmux@48000030 { |
24 | compatible = "ti,omap2420-padconf", "pinctrl-single"; | |
25 | reg = <0x48000030 0x0113>; | |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | pinctrl-single,register-width = <8>; | |
29 | pinctrl-single,function-mask = <0x3f>; | |
30 | }; | |
31 | ||
423182e3 JH |
32 | gpio1: gpio@48018000 { |
33 | compatible = "ti,omap2-gpio"; | |
34 | reg = <0x48018000 0x200>; | |
35 | interrupts = <29>; | |
36 | ti,hwmods = "gpio1"; | |
e4b9b9f3 | 37 | ti,gpio-always-on; |
423182e3 JH |
38 | #gpio-cells = <2>; |
39 | gpio-controller; | |
40 | #interrupt-cells = <2>; | |
41 | interrupt-controller; | |
42 | }; | |
43 | ||
44 | gpio2: gpio@4801a000 { | |
45 | compatible = "ti,omap2-gpio"; | |
46 | reg = <0x4801a000 0x200>; | |
47 | interrupts = <30>; | |
48 | ti,hwmods = "gpio2"; | |
e4b9b9f3 | 49 | ti,gpio-always-on; |
423182e3 JH |
50 | #gpio-cells = <2>; |
51 | gpio-controller; | |
52 | #interrupt-cells = <2>; | |
53 | interrupt-controller; | |
54 | }; | |
55 | ||
56 | gpio3: gpio@4801c000 { | |
57 | compatible = "ti,omap2-gpio"; | |
58 | reg = <0x4801c000 0x200>; | |
59 | interrupts = <31>; | |
60 | ti,hwmods = "gpio3"; | |
e4b9b9f3 | 61 | ti,gpio-always-on; |
423182e3 JH |
62 | #gpio-cells = <2>; |
63 | gpio-controller; | |
64 | #interrupt-cells = <2>; | |
65 | interrupt-controller; | |
66 | }; | |
67 | ||
68 | gpio4: gpio@4801e000 { | |
69 | compatible = "ti,omap2-gpio"; | |
70 | reg = <0x4801e000 0x200>; | |
71 | interrupts = <32>; | |
72 | ti,hwmods = "gpio4"; | |
e4b9b9f3 | 73 | ti,gpio-always-on; |
423182e3 JH |
74 | #gpio-cells = <2>; |
75 | gpio-controller; | |
76 | #interrupt-cells = <2>; | |
77 | interrupt-controller; | |
78 | }; | |
79 | ||
1c7dbb55 JH |
80 | gpmc: gpmc@6800a000 { |
81 | compatible = "ti,omap2420-gpmc"; | |
82 | reg = <0x6800a000 0x1000>; | |
83 | #address-cells = <2>; | |
84 | #size-cells = <1>; | |
85 | interrupts = <20>; | |
86 | gpmc,num-cs = <8>; | |
87 | gpmc,num-waitpins = <4>; | |
88 | ti,hwmods = "gpmc"; | |
89 | }; | |
90 | ||
3f187f82 PU |
91 | mcbsp1: mcbsp@48074000 { |
92 | compatible = "ti,omap2420-mcbsp"; | |
93 | reg = <0x48074000 0xff>; | |
94 | reg-names = "mpu"; | |
95 | interrupts = <59>, /* TX interrupt */ | |
96 | <60>; /* RX interrupt */ | |
97 | interrupt-names = "tx", "rx"; | |
3f187f82 | 98 | ti,hwmods = "mcbsp1"; |
4e4ead73 SG |
99 | dmas = <&sdma 31>, |
100 | <&sdma 32>; | |
101 | dma-names = "tx", "rx"; | |
3f187f82 PU |
102 | }; |
103 | ||
104 | mcbsp2: mcbsp@48076000 { | |
105 | compatible = "ti,omap2420-mcbsp"; | |
106 | reg = <0x48076000 0xff>; | |
107 | reg-names = "mpu"; | |
108 | interrupts = <62>, /* TX interrupt */ | |
109 | <63>; /* RX interrupt */ | |
110 | interrupt-names = "tx", "rx"; | |
3f187f82 | 111 | ti,hwmods = "mcbsp2"; |
4e4ead73 SG |
112 | dmas = <&sdma 33>, |
113 | <&sdma 34>; | |
114 | dma-names = "tx", "rx"; | |
3f187f82 | 115 | }; |
fab8ad0b JH |
116 | |
117 | timer1: timer@48028000 { | |
002e1ec5 | 118 | compatible = "ti,omap2420-timer"; |
fab8ad0b JH |
119 | reg = <0x48028000 0x400>; |
120 | interrupts = <37>; | |
121 | ti,hwmods = "timer1"; | |
122 | ti,timer-alwon; | |
123 | }; | |
3f187f82 PU |
124 | }; |
125 | }; |