Commit | Line | Data |
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3f187f82 PU |
1 | /* |
2 | * Device Tree Source for OMAP243x SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
98ef7957 | 11 | #include "omap2.dtsi" |
3f187f82 PU |
12 | |
13 | / { | |
14 | compatible = "ti,omap2430", "ti,omap2"; | |
15 | ||
16 | ocp { | |
bc797691 TK |
17 | prcm: prcm@49006000 { |
18 | compatible = "ti,omap2-prcm"; | |
19 | reg = <0x49006000 0x1000>; | |
20 | ||
21 | prcm_clocks: clocks { | |
22 | #address-cells = <1>; | |
23 | #size-cells = <0>; | |
24 | }; | |
25 | ||
26 | prcm_clockdomains: clockdomains { | |
27 | }; | |
28 | }; | |
29 | ||
30 | scrm: scrm@49002000 { | |
31 | compatible = "ti,omap2-scrm"; | |
32 | reg = <0x49002000 0x1000>; | |
33 | ||
34 | scrm_clocks: clocks { | |
35 | #address-cells = <1>; | |
36 | #size-cells = <0>; | |
37 | }; | |
38 | ||
39 | scrm_clockdomains: clockdomains { | |
40 | }; | |
41 | }; | |
42 | ||
510c0ffd JH |
43 | counter32k: counter@49020000 { |
44 | compatible = "ti,omap-counter32k"; | |
45 | reg = <0x49020000 0x20>; | |
46 | ti,hwmods = "counter_32k"; | |
47 | }; | |
48 | ||
679e3310 TL |
49 | omap2430_pmx: pinmux@49002030 { |
50 | compatible = "ti,omap2430-padconf", "pinctrl-single"; | |
51 | reg = <0x49002030 0x0154>; | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | pinctrl-single,register-width = <8>; | |
55 | pinctrl-single,function-mask = <0x3f>; | |
56 | }; | |
57 | ||
cd042fe5 B |
58 | omap2_scm_general: tisyscon@49002270 { |
59 | compatible = "syscon"; | |
60 | reg = <0x49002270 0x240>; | |
61 | }; | |
62 | ||
63 | pbias_regulator: pbias_regulator { | |
64 | compatible = "ti,pbias-omap"; | |
65 | reg = <0x230 0x4>; | |
66 | syscon = <&omap2_scm_general>; | |
67 | pbias_mmc_reg: pbias_mmc_omap2430 { | |
68 | regulator-name = "pbias_mmc_omap2430"; | |
69 | regulator-min-microvolt = <1800000>; | |
70 | regulator-max-microvolt = <3000000>; | |
71 | }; | |
72 | }; | |
73 | ||
423182e3 JH |
74 | gpio1: gpio@4900c000 { |
75 | compatible = "ti,omap2-gpio"; | |
76 | reg = <0x4900c000 0x200>; | |
77 | interrupts = <29>; | |
78 | ti,hwmods = "gpio1"; | |
e4b9b9f3 | 79 | ti,gpio-always-on; |
423182e3 JH |
80 | #gpio-cells = <2>; |
81 | gpio-controller; | |
82 | #interrupt-cells = <2>; | |
83 | interrupt-controller; | |
84 | }; | |
85 | ||
86 | gpio2: gpio@4900e000 { | |
87 | compatible = "ti,omap2-gpio"; | |
88 | reg = <0x4900e000 0x200>; | |
89 | interrupts = <30>; | |
90 | ti,hwmods = "gpio2"; | |
e4b9b9f3 | 91 | ti,gpio-always-on; |
423182e3 JH |
92 | #gpio-cells = <2>; |
93 | gpio-controller; | |
94 | #interrupt-cells = <2>; | |
95 | interrupt-controller; | |
96 | }; | |
97 | ||
98 | gpio3: gpio@49010000 { | |
99 | compatible = "ti,omap2-gpio"; | |
100 | reg = <0x49010000 0x200>; | |
101 | interrupts = <31>; | |
102 | ti,hwmods = "gpio3"; | |
e4b9b9f3 | 103 | ti,gpio-always-on; |
423182e3 JH |
104 | #gpio-cells = <2>; |
105 | gpio-controller; | |
106 | #interrupt-cells = <2>; | |
107 | interrupt-controller; | |
108 | }; | |
109 | ||
110 | gpio4: gpio@49012000 { | |
111 | compatible = "ti,omap2-gpio"; | |
112 | reg = <0x49012000 0x200>; | |
113 | interrupts = <32>; | |
114 | ti,hwmods = "gpio4"; | |
e4b9b9f3 | 115 | ti,gpio-always-on; |
423182e3 JH |
116 | #gpio-cells = <2>; |
117 | gpio-controller; | |
118 | #interrupt-cells = <2>; | |
119 | interrupt-controller; | |
120 | }; | |
121 | ||
122 | gpio5: gpio@480b6000 { | |
123 | compatible = "ti,omap2-gpio"; | |
124 | reg = <0x480b6000 0x200>; | |
125 | interrupts = <33>; | |
126 | ti,hwmods = "gpio5"; | |
127 | #gpio-cells = <2>; | |
128 | gpio-controller; | |
129 | #interrupt-cells = <2>; | |
130 | interrupt-controller; | |
131 | }; | |
132 | ||
1c7dbb55 JH |
133 | gpmc: gpmc@6e000000 { |
134 | compatible = "ti,omap2430-gpmc"; | |
135 | reg = <0x6e000000 0x1000>; | |
136 | #address-cells = <2>; | |
137 | #size-cells = <1>; | |
138 | interrupts = <20>; | |
139 | gpmc,num-cs = <8>; | |
140 | gpmc,num-waitpins = <4>; | |
141 | ti,hwmods = "gpmc"; | |
142 | }; | |
143 | ||
3f187f82 PU |
144 | mcbsp1: mcbsp@48074000 { |
145 | compatible = "ti,omap2430-mcbsp"; | |
146 | reg = <0x48074000 0xff>; | |
147 | reg-names = "mpu"; | |
148 | interrupts = <64>, /* OCP compliant interrupt */ | |
149 | <59>, /* TX interrupt */ | |
150 | <60>, /* RX interrupt */ | |
151 | <61>; /* RX overflow interrupt */ | |
152 | interrupt-names = "common", "tx", "rx", "rx_overflow"; | |
3f187f82 PU |
153 | ti,buffer-size = <128>; |
154 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
155 | dmas = <&sdma 31>, |
156 | <&sdma 32>; | |
157 | dma-names = "tx", "rx"; | |
faa00deb | 158 | status = "disabled"; |
3f187f82 PU |
159 | }; |
160 | ||
161 | mcbsp2: mcbsp@48076000 { | |
162 | compatible = "ti,omap2430-mcbsp"; | |
163 | reg = <0x48076000 0xff>; | |
164 | reg-names = "mpu"; | |
165 | interrupts = <16>, /* OCP compliant interrupt */ | |
166 | <62>, /* TX interrupt */ | |
167 | <63>; /* RX interrupt */ | |
168 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
169 | ti,buffer-size = <128>; |
170 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
171 | dmas = <&sdma 33>, |
172 | <&sdma 34>; | |
173 | dma-names = "tx", "rx"; | |
faa00deb | 174 | status = "disabled"; |
3f187f82 PU |
175 | }; |
176 | ||
177 | mcbsp3: mcbsp@4808c000 { | |
178 | compatible = "ti,omap2430-mcbsp"; | |
179 | reg = <0x4808c000 0xff>; | |
180 | reg-names = "mpu"; | |
181 | interrupts = <17>, /* OCP compliant interrupt */ | |
182 | <89>, /* TX interrupt */ | |
183 | <90>; /* RX interrupt */ | |
184 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
185 | ti,buffer-size = <128>; |
186 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
187 | dmas = <&sdma 17>, |
188 | <&sdma 18>; | |
189 | dma-names = "tx", "rx"; | |
faa00deb | 190 | status = "disabled"; |
3f187f82 PU |
191 | }; |
192 | ||
193 | mcbsp4: mcbsp@4808e000 { | |
194 | compatible = "ti,omap2430-mcbsp"; | |
195 | reg = <0x4808e000 0xff>; | |
196 | reg-names = "mpu"; | |
197 | interrupts = <18>, /* OCP compliant interrupt */ | |
198 | <54>, /* TX interrupt */ | |
199 | <55>; /* RX interrupt */ | |
200 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
201 | ti,buffer-size = <128>; |
202 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
203 | dmas = <&sdma 19>, |
204 | <&sdma 20>; | |
205 | dma-names = "tx", "rx"; | |
faa00deb | 206 | status = "disabled"; |
3f187f82 PU |
207 | }; |
208 | ||
209 | mcbsp5: mcbsp@48096000 { | |
210 | compatible = "ti,omap2430-mcbsp"; | |
211 | reg = <0x48096000 0xff>; | |
212 | reg-names = "mpu"; | |
213 | interrupts = <19>, /* OCP compliant interrupt */ | |
214 | <81>, /* TX interrupt */ | |
215 | <82>; /* RX interrupt */ | |
216 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
217 | ti,buffer-size = <128>; |
218 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
219 | dmas = <&sdma 21>, |
220 | <&sdma 22>; | |
221 | dma-names = "tx", "rx"; | |
faa00deb | 222 | status = "disabled"; |
3f187f82 | 223 | }; |
fab8ad0b | 224 | |
467f4bd2 TL |
225 | mmc1: mmc@4809c000 { |
226 | compatible = "ti,omap2-hsmmc"; | |
227 | reg = <0x4809c000 0x200>; | |
228 | interrupts = <83>; | |
229 | ti,hwmods = "mmc1"; | |
230 | ti,dual-volt; | |
231 | dmas = <&sdma 61>, <&sdma 62>; | |
232 | dma-names = "tx", "rx"; | |
cd042fe5 | 233 | pbias-supply = <&pbias_mmc_reg>; |
467f4bd2 TL |
234 | }; |
235 | ||
236 | mmc2: mmc@480b4000 { | |
237 | compatible = "ti,omap2-hsmmc"; | |
238 | reg = <0x480b4000 0x200>; | |
239 | interrupts = <86>; | |
240 | ti,hwmods = "mmc2"; | |
241 | dmas = <&sdma 47>, <&sdma 48>; | |
242 | dma-names = "tx", "rx"; | |
243 | }; | |
244 | ||
4fe5bd5d SA |
245 | mailbox: mailbox@48094000 { |
246 | compatible = "ti,omap2-mailbox"; | |
247 | reg = <0x48094000 0x200>; | |
248 | interrupts = <26>; | |
249 | ti,hwmods = "mailbox"; | |
24df0453 | 250 | #mbox-cells = <1>; |
41ffada1 SA |
251 | ti,mbox-num-users = <4>; |
252 | ti,mbox-num-fifos = <6>; | |
d27704d1 SA |
253 | mbox_dsp: dsp { |
254 | ti,mbox-tx = <0 0 0>; | |
255 | ti,mbox-rx = <1 0 0>; | |
256 | }; | |
4fe5bd5d SA |
257 | }; |
258 | ||
fab8ad0b | 259 | timer1: timer@49018000 { |
002e1ec5 | 260 | compatible = "ti,omap2420-timer"; |
fab8ad0b JH |
261 | reg = <0x49018000 0x400>; |
262 | interrupts = <37>; | |
263 | ti,hwmods = "timer1"; | |
264 | ti,timer-alwon; | |
265 | }; | |
467f4bd2 TL |
266 | |
267 | mcspi3: mcspi@480b8000 { | |
268 | compatible = "ti,omap2-mcspi"; | |
269 | ti,hwmods = "mcspi3"; | |
270 | reg = <0x480b8000 0x100>; | |
271 | interrupts = <91>; | |
272 | dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; | |
273 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
274 | }; | |
275 | ||
276 | usb_otg_hs: usb_otg_hs@480ac000 { | |
277 | compatible = "ti,omap2-musb"; | |
278 | ti,hwmods = "usb_otg_hs"; | |
279 | reg = <0x480ac000 0x1000>; | |
280 | interrupts = <93>; | |
281 | }; | |
282 | ||
283 | wd_timer2: wdt@49016000 { | |
284 | compatible = "ti,omap2-wdt"; | |
285 | ti,hwmods = "wd_timer2"; | |
286 | reg = <0x49016000 0x80>; | |
287 | }; | |
3f187f82 PU |
288 | }; |
289 | }; | |
467f4bd2 TL |
290 | |
291 | &i2c1 { | |
292 | compatible = "ti,omap2430-i2c"; | |
293 | }; | |
294 | ||
295 | &i2c2 { | |
296 | compatible = "ti,omap2430-i2c"; | |
297 | }; | |
69a1e7a1 TK |
298 | |
299 | /include/ "omap24xx-clocks.dtsi" | |
300 | /include/ "omap2430-clocks.dtsi" |