Commit | Line | Data |
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3f187f82 PU |
1 | /* |
2 | * Device Tree Source for OMAP243x SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
98ef7957 | 11 | #include "omap2.dtsi" |
3f187f82 PU |
12 | |
13 | / { | |
14 | compatible = "ti,omap2430", "ti,omap2"; | |
15 | ||
16 | ocp { | |
72b10ac0 TK |
17 | l4_wkup: l4_wkup@49000000 { |
18 | compatible = "ti,omap2-l4-wkup", "simple-bus"; | |
19 | #address-cells = <1>; | |
20 | #size-cells = <1>; | |
21 | ranges = <0 0x49000000 0x31000>; | |
bc797691 | 22 | |
72b10ac0 TK |
23 | prcm: prcm@6000 { |
24 | compatible = "ti,omap2-prcm"; | |
25 | reg = <0x6000 0x1000>; | |
bc797691 | 26 | |
72b10ac0 TK |
27 | prcm_clocks: clocks { |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | }; | |
bc797691 | 31 | |
72b10ac0 TK |
32 | prcm_clockdomains: clockdomains { |
33 | }; | |
34 | }; | |
bc797691 | 35 | |
72b10ac0 TK |
36 | scm: scm@2000 { |
37 | compatible = "ti,omap2-scm", "simple-bus"; | |
38 | reg = <0x2000 0x1000>; | |
bc797691 | 39 | #address-cells = <1>; |
72b10ac0 TK |
40 | #size-cells = <1>; |
41 | ranges = <0 0x2000 0x1000>; | |
bc797691 | 42 | |
72b10ac0 TK |
43 | omap2430_pmx: pinmux@30 { |
44 | compatible = "ti,omap2430-padconf", | |
45 | "pinctrl-single"; | |
46 | reg = <0x30 0x0154>; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <0>; | |
49 | pinctrl-single,register-width = <8>; | |
50 | pinctrl-single,function-mask = <0x3f>; | |
51 | }; | |
bc797691 | 52 | |
72b10ac0 | 53 | scm_conf: scm_conf@270 { |
4317c8c9 KVA |
54 | compatible = "syscon", |
55 | "simple-bus"; | |
72b10ac0 TK |
56 | reg = <0x270 0x240>; |
57 | #address-cells = <1>; | |
58 | #size-cells = <1>; | |
510c0ffd | 59 | |
72b10ac0 TK |
60 | scm_clocks: clocks { |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | }; | |
679e3310 | 64 | |
72b10ac0 TK |
65 | pbias_regulator: pbias_regulator { |
66 | compatible = "ti,pbias-omap"; | |
67 | reg = <0x230 0x4>; | |
68 | syscon = <&scm_conf>; | |
69 | pbias_mmc_reg: pbias_mmc_omap2430 { | |
70 | regulator-name = "pbias_mmc_omap2430"; | |
71 | regulator-min-microvolt = <1800000>; | |
72 | regulator-max-microvolt = <3000000>; | |
73 | }; | |
74 | }; | |
75 | }; | |
76 | ||
77 | scm_clockdomains: clockdomains { | |
78 | }; | |
79 | }; | |
cd042fe5 | 80 | |
72b10ac0 TK |
81 | counter32k: counter@20000 { |
82 | compatible = "ti,omap-counter32k"; | |
83 | reg = <0x20000 0x20>; | |
84 | ti,hwmods = "counter_32k"; | |
cd042fe5 B |
85 | }; |
86 | }; | |
87 | ||
423182e3 JH |
88 | gpio1: gpio@4900c000 { |
89 | compatible = "ti,omap2-gpio"; | |
90 | reg = <0x4900c000 0x200>; | |
91 | interrupts = <29>; | |
92 | ti,hwmods = "gpio1"; | |
e4b9b9f3 | 93 | ti,gpio-always-on; |
423182e3 JH |
94 | #gpio-cells = <2>; |
95 | gpio-controller; | |
96 | #interrupt-cells = <2>; | |
97 | interrupt-controller; | |
98 | }; | |
99 | ||
100 | gpio2: gpio@4900e000 { | |
101 | compatible = "ti,omap2-gpio"; | |
102 | reg = <0x4900e000 0x200>; | |
103 | interrupts = <30>; | |
104 | ti,hwmods = "gpio2"; | |
e4b9b9f3 | 105 | ti,gpio-always-on; |
423182e3 JH |
106 | #gpio-cells = <2>; |
107 | gpio-controller; | |
108 | #interrupt-cells = <2>; | |
109 | interrupt-controller; | |
110 | }; | |
111 | ||
112 | gpio3: gpio@49010000 { | |
113 | compatible = "ti,omap2-gpio"; | |
114 | reg = <0x49010000 0x200>; | |
115 | interrupts = <31>; | |
116 | ti,hwmods = "gpio3"; | |
e4b9b9f3 | 117 | ti,gpio-always-on; |
423182e3 JH |
118 | #gpio-cells = <2>; |
119 | gpio-controller; | |
120 | #interrupt-cells = <2>; | |
121 | interrupt-controller; | |
122 | }; | |
123 | ||
124 | gpio4: gpio@49012000 { | |
125 | compatible = "ti,omap2-gpio"; | |
126 | reg = <0x49012000 0x200>; | |
127 | interrupts = <32>; | |
128 | ti,hwmods = "gpio4"; | |
e4b9b9f3 | 129 | ti,gpio-always-on; |
423182e3 JH |
130 | #gpio-cells = <2>; |
131 | gpio-controller; | |
132 | #interrupt-cells = <2>; | |
133 | interrupt-controller; | |
134 | }; | |
135 | ||
136 | gpio5: gpio@480b6000 { | |
137 | compatible = "ti,omap2-gpio"; | |
138 | reg = <0x480b6000 0x200>; | |
139 | interrupts = <33>; | |
140 | ti,hwmods = "gpio5"; | |
141 | #gpio-cells = <2>; | |
142 | gpio-controller; | |
143 | #interrupt-cells = <2>; | |
144 | interrupt-controller; | |
145 | }; | |
146 | ||
1c7dbb55 JH |
147 | gpmc: gpmc@6e000000 { |
148 | compatible = "ti,omap2430-gpmc"; | |
149 | reg = <0x6e000000 0x1000>; | |
150 | #address-cells = <2>; | |
151 | #size-cells = <1>; | |
152 | interrupts = <20>; | |
153 | gpmc,num-cs = <8>; | |
154 | gpmc,num-waitpins = <4>; | |
155 | ti,hwmods = "gpmc"; | |
156 | }; | |
157 | ||
3f187f82 PU |
158 | mcbsp1: mcbsp@48074000 { |
159 | compatible = "ti,omap2430-mcbsp"; | |
160 | reg = <0x48074000 0xff>; | |
161 | reg-names = "mpu"; | |
162 | interrupts = <64>, /* OCP compliant interrupt */ | |
163 | <59>, /* TX interrupt */ | |
164 | <60>, /* RX interrupt */ | |
165 | <61>; /* RX overflow interrupt */ | |
166 | interrupt-names = "common", "tx", "rx", "rx_overflow"; | |
3f187f82 PU |
167 | ti,buffer-size = <128>; |
168 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
169 | dmas = <&sdma 31>, |
170 | <&sdma 32>; | |
171 | dma-names = "tx", "rx"; | |
faa00deb | 172 | status = "disabled"; |
3f187f82 PU |
173 | }; |
174 | ||
175 | mcbsp2: mcbsp@48076000 { | |
176 | compatible = "ti,omap2430-mcbsp"; | |
177 | reg = <0x48076000 0xff>; | |
178 | reg-names = "mpu"; | |
179 | interrupts = <16>, /* OCP compliant interrupt */ | |
180 | <62>, /* TX interrupt */ | |
181 | <63>; /* RX interrupt */ | |
182 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
183 | ti,buffer-size = <128>; |
184 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
185 | dmas = <&sdma 33>, |
186 | <&sdma 34>; | |
187 | dma-names = "tx", "rx"; | |
faa00deb | 188 | status = "disabled"; |
3f187f82 PU |
189 | }; |
190 | ||
191 | mcbsp3: mcbsp@4808c000 { | |
192 | compatible = "ti,omap2430-mcbsp"; | |
193 | reg = <0x4808c000 0xff>; | |
194 | reg-names = "mpu"; | |
195 | interrupts = <17>, /* OCP compliant interrupt */ | |
196 | <89>, /* TX interrupt */ | |
197 | <90>; /* RX interrupt */ | |
198 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
199 | ti,buffer-size = <128>; |
200 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
201 | dmas = <&sdma 17>, |
202 | <&sdma 18>; | |
203 | dma-names = "tx", "rx"; | |
faa00deb | 204 | status = "disabled"; |
3f187f82 PU |
205 | }; |
206 | ||
207 | mcbsp4: mcbsp@4808e000 { | |
208 | compatible = "ti,omap2430-mcbsp"; | |
209 | reg = <0x4808e000 0xff>; | |
210 | reg-names = "mpu"; | |
211 | interrupts = <18>, /* OCP compliant interrupt */ | |
212 | <54>, /* TX interrupt */ | |
213 | <55>; /* RX interrupt */ | |
214 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
215 | ti,buffer-size = <128>; |
216 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
217 | dmas = <&sdma 19>, |
218 | <&sdma 20>; | |
219 | dma-names = "tx", "rx"; | |
faa00deb | 220 | status = "disabled"; |
3f187f82 PU |
221 | }; |
222 | ||
223 | mcbsp5: mcbsp@48096000 { | |
224 | compatible = "ti,omap2430-mcbsp"; | |
225 | reg = <0x48096000 0xff>; | |
226 | reg-names = "mpu"; | |
227 | interrupts = <19>, /* OCP compliant interrupt */ | |
228 | <81>, /* TX interrupt */ | |
229 | <82>; /* RX interrupt */ | |
230 | interrupt-names = "common", "tx", "rx"; | |
3f187f82 PU |
231 | ti,buffer-size = <128>; |
232 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
233 | dmas = <&sdma 21>, |
234 | <&sdma 22>; | |
235 | dma-names = "tx", "rx"; | |
faa00deb | 236 | status = "disabled"; |
3f187f82 | 237 | }; |
fab8ad0b | 238 | |
467f4bd2 TL |
239 | mmc1: mmc@4809c000 { |
240 | compatible = "ti,omap2-hsmmc"; | |
241 | reg = <0x4809c000 0x200>; | |
242 | interrupts = <83>; | |
243 | ti,hwmods = "mmc1"; | |
244 | ti,dual-volt; | |
245 | dmas = <&sdma 61>, <&sdma 62>; | |
246 | dma-names = "tx", "rx"; | |
cd042fe5 | 247 | pbias-supply = <&pbias_mmc_reg>; |
467f4bd2 TL |
248 | }; |
249 | ||
250 | mmc2: mmc@480b4000 { | |
251 | compatible = "ti,omap2-hsmmc"; | |
252 | reg = <0x480b4000 0x200>; | |
253 | interrupts = <86>; | |
254 | ti,hwmods = "mmc2"; | |
255 | dmas = <&sdma 47>, <&sdma 48>; | |
256 | dma-names = "tx", "rx"; | |
257 | }; | |
258 | ||
4fe5bd5d SA |
259 | mailbox: mailbox@48094000 { |
260 | compatible = "ti,omap2-mailbox"; | |
261 | reg = <0x48094000 0x200>; | |
262 | interrupts = <26>; | |
263 | ti,hwmods = "mailbox"; | |
24df0453 | 264 | #mbox-cells = <1>; |
41ffada1 SA |
265 | ti,mbox-num-users = <4>; |
266 | ti,mbox-num-fifos = <6>; | |
d27704d1 SA |
267 | mbox_dsp: dsp { |
268 | ti,mbox-tx = <0 0 0>; | |
269 | ti,mbox-rx = <1 0 0>; | |
270 | }; | |
4fe5bd5d SA |
271 | }; |
272 | ||
fab8ad0b | 273 | timer1: timer@49018000 { |
002e1ec5 | 274 | compatible = "ti,omap2420-timer"; |
fab8ad0b JH |
275 | reg = <0x49018000 0x400>; |
276 | interrupts = <37>; | |
277 | ti,hwmods = "timer1"; | |
278 | ti,timer-alwon; | |
279 | }; | |
467f4bd2 TL |
280 | |
281 | mcspi3: mcspi@480b8000 { | |
282 | compatible = "ti,omap2-mcspi"; | |
283 | ti,hwmods = "mcspi3"; | |
284 | reg = <0x480b8000 0x100>; | |
285 | interrupts = <91>; | |
286 | dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; | |
287 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
288 | }; | |
289 | ||
290 | usb_otg_hs: usb_otg_hs@480ac000 { | |
291 | compatible = "ti,omap2-musb"; | |
292 | ti,hwmods = "usb_otg_hs"; | |
293 | reg = <0x480ac000 0x1000>; | |
294 | interrupts = <93>; | |
295 | }; | |
296 | ||
297 | wd_timer2: wdt@49016000 { | |
298 | compatible = "ti,omap2-wdt"; | |
299 | ti,hwmods = "wd_timer2"; | |
300 | reg = <0x49016000 0x80>; | |
301 | }; | |
3f187f82 PU |
302 | }; |
303 | }; | |
467f4bd2 TL |
304 | |
305 | &i2c1 { | |
306 | compatible = "ti,omap2430-i2c"; | |
307 | }; | |
308 | ||
309 | &i2c2 { | |
310 | compatible = "ti,omap2430-i2c"; | |
311 | }; | |
69a1e7a1 TK |
312 | |
313 | /include/ "omap24xx-clocks.dtsi" | |
314 | /include/ "omap2430-clocks.dtsi" |