[deliverable/linux.git] / arch / arm / boot / dts / omap3-cm-t3x30.dtsi

/*
 * Common support for CompuLab CM-T3x30 CoMs
 */

#include "omap3-cm-t3x.dtsi"

/ {
	cpus {
		cpu@0 {
			cpu0-supply = <&vcc>;
		};
	};
};

&omap3_pmx_core {

	smsc1_pins: pinmux_smsc1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT | MUX_MODE0)	/* gpmc_ncs5.gpmc_ncs5 */
			OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4)	/* uart3_cts_rctx.gpio_163 */
		>;
	};

 	hsusb0_pins: pinmux_hsusb0_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0)		/* hsusb0_clk.hsusb0_clk */
			OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)		/* hsusb0_stp.hsusb0_stp */
			OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_dir.hsusb0_dir */
			OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_nxt.hsusb0_nxt */
			OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data0.hsusb2_data0 */
			OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data1.hsusb0_data1 */
			OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data2.hsusb0_data2 */
			OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data7.hsusb0_data3 */
			OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data7.hsusb0_data4 */
			OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data7.hsusb0_data5 */
			OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data7.hsusb0_data6 */
			OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* hsusb0_data7.hsusb0_data7 */
		>;
	};
};

#include "omap-gpmc-smsc911x.dtsi"

&gpmc {
	ranges = <5 0 0x2c000000 0x01000000>;

	smsc1: ethernet@gpmc {
		compatible = "smsc,lan9221", "smsc,lan9115";
		pinctrl-names = "default";
		pinctrl-0 = <&smsc1_pins>;
		interrupt-parent = <&gpio6>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		reg = <5 0 0xff>;
	};
};

&i2c1 {
	twl: twl@48 {
		reg = <0x48>;
		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
		interrupt-parent = <&intc>;
	};
};

#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
#include <dt-bindings/input/input.h>

&mmc1 {
	vmmc-supply = <&vmmc1>;
};

&twl_gpio {
	ti,use-leds;
	/* pullups: BIT(0) */
	ti,pullups = <0x000001>;
};

&twl_keypad {
	linux,keymap = <
				MATRIX_KEY(0x00, 0x01, KEY_A)
				MATRIX_KEY(0x00, 0x02, KEY_B)
				MATRIX_KEY(0x00, 0x03, KEY_LEFT)

				MATRIX_KEY(0x01, 0x01, KEY_UP)
				MATRIX_KEY(0x01, 0x02, KEY_ENTER)
				MATRIX_KEY(0x01, 0x03, KEY_DOWN)

				MATRIX_KEY(0x02, 0x01, KEY_RIGHT)
				MATRIX_KEY(0x02, 0x02, KEY_C)
				MATRIX_KEY(0x02, 0x03, KEY_D)
			>;
};

&hsusb1_phy {
	reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
};

&hsusb2_phy {
	reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
};

&usb_otg_hs {
	pinctrl-names = "default";
	pinctrl-0 = <&hsusb0_pins>;
	interface-type = <0>;
	usb-phy = <&usb2_phy>;
	phys = <&usb2_phy>;
	phy-names = "usb2-phy";
	mode = <3>;
	power = <50>;
};
Commit	Line	Data
0f0cfc69	1	/*
d234e423	2	* Common support for CompuLab CM-T3x30 CoMs
0f0cfc69 TL	3	*/
0f0cfc69 TL	4
d234e423	5	#include "omap3-cm-t3x.dtsi"
0f0cfc69	6
d234e423	7	/ {
0f0cfc69 TL	8	cpus {
	9	cpu@0 {
	10	cpu0-supply = <&vcc>;
	11	};
	12	};
0f0cfc69 TL	13	};
0f0cfc69 TL	14
d234e423 DL	15	&omap3_pmx_core {
	16
	17	smsc1_pins: pinmux_smsc1_pins {
	18	pinctrl-single,pins = <
	19	OMAP3_CORE1_IOPAD(0x20b8, PIN_OUTPUT \| MUX_MODE0) /* gpmc_ncs5.gpmc_ncs5 */
	20	OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP \| MUX_MODE4) /* uart3_cts_rctx.gpio_163 */
	21	>;
	22	};
dcb27bee DL	23
	24	hsusb0_pins: pinmux_hsusb0_pins {
	25	pinctrl-single,pins = <
20f670dc TL	26	OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT \| MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
	27	OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT \| MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
	28	OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
	29	OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
	30	OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
	31	OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
	32	OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
	33	OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
	34	OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
	35	OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
	36	OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
	37	OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
dcb27bee DL	38	>;
dcb27bee DL	39	};
d234e423 DL	40	};
d234e423 DL	41
de9949a4 TL	42	#include "omap-gpmc-smsc911x.dtsi"
de9949a4 TL	43
0f0cfc69 TL	44	&gpmc {
	45	ranges = <5 0 0x2c000000 0x01000000>;
	46
de9949a4	47	smsc1: ethernet@gpmc {
0f0cfc69	48	compatible = "smsc,lan9221", "smsc,lan9115";
d234e423 DL	49	pinctrl-names = "default";
d234e423 DL	50	pinctrl-0 = <&smsc1_pins>;
0f0cfc69 TL	51	interrupt-parent = <&gpio6>;
	52	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	53	reg = <5 0 0xff>;
0f0cfc69 TL	54	};
	55	};
	56
	57	&i2c1 {
0f0cfc69 TL	58	twl: twl@48 {
	59	reg = <0x48>;
	60	interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	61	interrupt-parent = <&intc>;
	62	};
	63	};
	64
	65	#include "twl4030.dtsi"
	66	#include "twl4030_omap3.dtsi"
828b949f	67	#include <dt-bindings/input/input.h>
0f0cfc69	68
d234e423 DL	69	&mmc1 {
d234e423 DL	70	vmmc-supply = <&vmmc1>;
0f0cfc69 TL	71	};
	72
	73	&twl_gpio {
	74	ti,use-leds;
0cc73cd4 DL	75	/* pullups: BIT(0) */
0cc73cd4 DL	76	ti,pullups = <0x000001>;
0f0cfc69	77	};
ce5abbb8	78
828b949f DL	79	&twl_keypad {
	80	linux,keymap = <
	81	MATRIX_KEY(0x00, 0x01, KEY_A)
	82	MATRIX_KEY(0x00, 0x02, KEY_B)
	83	MATRIX_KEY(0x00, 0x03, KEY_LEFT)
	84
	85	MATRIX_KEY(0x01, 0x01, KEY_UP)
	86	MATRIX_KEY(0x01, 0x02, KEY_ENTER)
	87	MATRIX_KEY(0x01, 0x03, KEY_DOWN)
	88
	89	MATRIX_KEY(0x02, 0x01, KEY_RIGHT)
	90	MATRIX_KEY(0x02, 0x02, KEY_C)
	91	MATRIX_KEY(0x02, 0x03, KEY_D)
	92	>;
	93	};
	94
ce5abbb8 DL	95	&hsusb1_phy {
	96	reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>;
	97	};
	98
	99	&hsusb2_phy {
	100	reset-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
	101	};
dcb27bee DL	102
	103	&usb_otg_hs {
	104	pinctrl-names = "default";
	105	pinctrl-0 = <&hsusb0_pins>;
	106	interface-type = <0>;
	107	usb-phy = <&usb2_phy>;
	108	phys = <&usb2_phy>;
	109	phy-names = "usb2-phy";
	110	mode = <3>;
	111	power = <50>;
	112	};