[deliverable/linux.git] / arch / arm / boot / dts / omap3.dtsi

/*
 * Device Tree Source for OMAP3 SoC
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap3430", "ti,omap3";

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a8";
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};

		iva {
			compatible = "ti,iva2.2";
			ti,hwmods = "iva";

			dsp {
				compatible = "ti,omap3-c64";
			};
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <96>;
			reg = <0x48200000 0x1000>;
		};

		gpio1: gpio@48310000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@49050000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@49052000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@49054000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@49056000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@49058000 {
			compatible = "ti,omap3-gpio";
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@49020000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap3-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap2-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap3-hsmmc";
			ti,hwmods = "mmc1";
			ti,dual-volt;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap3-hsmmc";
			ti,hwmods = "mmc2";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap3-hsmmc";
			ti,hwmods = "mmc3";
		};

		wdt2: wdt@48314000 {
			compatible = "ti,omap3-wdt";
			ti,hwmods = "wd_timer2";
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <16>, /* OCP compliant interrupt */
				     <59>, /* TX interrupt */
				     <60>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			interrupt-parent = <&intc>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@49022000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49022000 0xff>,
			      <0x49028000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <17>, /* OCP compliant interrupt */
				     <62>, /* TX interrupt */
				     <63>, /* RX interrupt */
				     <4>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			interrupt-parent = <&intc>;
			ti,buffer-size = <1280>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@49024000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49024000 0xff>,
			      <0x4902a000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <22>, /* OCP compliant interrupt */
				     <89>, /* TX interrupt */
				     <90>, /* RX interrupt */
				     <5>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			interrupt-parent = <&intc>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};

		mcbsp4: mcbsp@49026000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49026000 0xff>;
			reg-names = "mpu";
			interrupts = <23>, /* OCP compliant interrupt */
				     <54>, /* TX interrupt */
				     <55>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			interrupt-parent = <&intc>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
		};

		mcbsp5: mcbsp@48096000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48096000 0xff>;
			reg-names = "mpu";
			interrupts = <27>, /* OCP compliant interrupt */
				     <81>, /* TX interrupt */
				     <82>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			interrupt-parent = <&intc>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp5";
		};
	};
};
Commit	Line	Data
189892f4 BC	1	/*
	2	* Device Tree Source for OMAP3 SoC
	3	*
	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
	11	/include/ "skeleton.dtsi"
	12
	13	/ {
	14	compatible = "ti,omap3430", "ti,omap3";
	15
cf3c79de RN	16	aliases {
	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
cf3c79de RN	20	};
cf3c79de RN	21
476b679a BC	22	cpus {
	23	cpu@0 {
	24	compatible = "arm,cortex-a8";
	25	};
	26	};
	27
189892f4 BC	28	/*
	29	* The soc node represents the soc top level view. It is uses for IPs
	30	* that are not memory mapped in the MPU view or for the MPU itself.
	31	*/
	32	soc {
	33	compatible = "ti,omap-infra";
476b679a BC	34	mpu {
	35	compatible = "ti,omap3-mpu";
	36	ti,hwmods = "mpu";
	37	};
	38
	39	iva {
	40	compatible = "ti,iva2.2";
	41	ti,hwmods = "iva";
	42
	43	dsp {
	44	compatible = "ti,omap3-c64";
	45	};
	46	};
189892f4 BC	47	};
	48
	49	/*
	50	* XXX: Use a flat representation of the OMAP3 interconnect.
	51	* The real OMAP interconnect network is quite complex.
	52	* Since that will not bring real advantage to represent that in DT for
	53	* the moment, just use a fake OCP bus entry to represent the whole bus
	54	* hierarchy.
	55	*/
	56	ocp {
	57	compatible = "simple-bus";
	58	#address-cells = <1>;
	59	#size-cells = <1>;
	60	ranges;
	61	ti,hwmods = "l3_main";
	62
d65c5423 BC	63	intc: interrupt-controller@48200000 {
d65c5423 BC	64	compatible = "ti,omap2-intc";
189892f4 BC	65	interrupt-controller;
189892f4 BC	66	#interrupt-cells = <1>;
d65c5423 BC	67	ti,intc-size = <96>;
d65c5423 BC	68	reg = <0x48200000 0x1000>;
189892f4	69	};
cf3c79de	70
385a64bb BC	71	gpio1: gpio@48310000 {
	72	compatible = "ti,omap3-gpio";
	73	ti,hwmods = "gpio1";
	74	gpio-controller;
	75	#gpio-cells = <2>;
	76	interrupt-controller;
	77	#interrupt-cells = <1>;
	78	};
	79
	80	gpio2: gpio@49050000 {
	81	compatible = "ti,omap3-gpio";
	82	ti,hwmods = "gpio2";
	83	gpio-controller;
	84	#gpio-cells = <2>;
	85	interrupt-controller;
	86	#interrupt-cells = <1>;
	87	};
	88
	89	gpio3: gpio@49052000 {
	90	compatible = "ti,omap3-gpio";
	91	ti,hwmods = "gpio3";
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94	interrupt-controller;
	95	#interrupt-cells = <1>;
	96	};
	97
	98	gpio4: gpio@49054000 {
	99	compatible = "ti,omap3-gpio";
	100	ti,hwmods = "gpio4";
	101	gpio-controller;
	102	#gpio-cells = <2>;
	103	interrupt-controller;
	104	#interrupt-cells = <1>;
	105	};
	106
	107	gpio5: gpio@49056000 {
	108	compatible = "ti,omap3-gpio";
	109	ti,hwmods = "gpio5";
	110	gpio-controller;
	111	#gpio-cells = <2>;
	112	interrupt-controller;
	113	#interrupt-cells = <1>;
	114	};
	115
	116	gpio6: gpio@49058000 {
	117	compatible = "ti,omap3-gpio";
	118	ti,hwmods = "gpio6";
	119	gpio-controller;
	120	#gpio-cells = <2>;
	121	interrupt-controller;
	122	#interrupt-cells = <1>;
	123	};
	124
19bfb76c	125	uart1: serial@4806a000 {
cf3c79de RN	126	compatible = "ti,omap3-uart";
	127	ti,hwmods = "uart1";
	128	clock-frequency = <48000000>;
	129	};
	130
19bfb76c	131	uart2: serial@4806c000 {
cf3c79de RN	132	compatible = "ti,omap3-uart";
	133	ti,hwmods = "uart2";
	134	clock-frequency = <48000000>;
	135	};
	136
19bfb76c	137	uart3: serial@49020000 {
cf3c79de RN	138	compatible = "ti,omap3-uart";
	139	ti,hwmods = "uart3";
	140	clock-frequency = <48000000>;
	141	};
	142
ca59a5c1 BC	143	i2c1: i2c@48070000 {
	144	compatible = "ti,omap3-i2c";
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147	ti,hwmods = "i2c1";
	148	};
	149
	150	i2c2: i2c@48072000 {
	151	compatible = "ti,omap3-i2c";
	152	#address-cells = <1>;
	153	#size-cells = <0>;
	154	ti,hwmods = "i2c2";
	155	};
	156
	157	i2c3: i2c@48060000 {
	158	compatible = "ti,omap3-i2c";
	159	#address-cells = <1>;
	160	#size-cells = <0>;
	161	ti,hwmods = "i2c3";
	162	};
fc72d248 BC	163
	164	mcspi1: spi@48098000 {
	165	compatible = "ti,omap2-mcspi";
	166	#address-cells = <1>;
	167	#size-cells = <0>;
	168	ti,hwmods = "mcspi1";
	169	ti,spi-num-cs = <4>;
	170	};
	171
	172	mcspi2: spi@4809a000 {
	173	compatible = "ti,omap2-mcspi";
	174	#address-cells = <1>;
	175	#size-cells = <0>;
	176	ti,hwmods = "mcspi2";
	177	ti,spi-num-cs = <2>;
	178	};
	179
	180	mcspi3: spi@480b8000 {
	181	compatible = "ti,omap2-mcspi";
	182	#address-cells = <1>;
	183	#size-cells = <0>;
	184	ti,hwmods = "mcspi3";
	185	ti,spi-num-cs = <2>;
	186	};
	187
	188	mcspi4: spi@480ba000 {
	189	compatible = "ti,omap2-mcspi";
	190	#address-cells = <1>;
	191	#size-cells = <0>;
	192	ti,hwmods = "mcspi4";
	193	ti,spi-num-cs = <1>;
	194	};
b3431f5b RN	195
	196	mmc1: mmc@4809c000 {
	197	compatible = "ti,omap3-hsmmc";
	198	ti,hwmods = "mmc1";
	199	ti,dual-volt;
	200	};
	201
	202	mmc2: mmc@480b4000 {
	203	compatible = "ti,omap3-hsmmc";
	204	ti,hwmods = "mmc2";
	205	};
	206
	207	mmc3: mmc@480ad000 {
	208	compatible = "ti,omap3-hsmmc";
	209	ti,hwmods = "mmc3";
	210	};
94c30732 XJ	211
	212	wdt2: wdt@48314000 {
	213	compatible = "ti,omap3-wdt";
	214	ti,hwmods = "wd_timer2";
	215	};
0be484bf PU	216
	217	mcbsp1: mcbsp@48074000 {
	218	compatible = "ti,omap3-mcbsp";
	219	reg = <0x48074000 0xff>;
	220	reg-names = "mpu";
	221	interrupts = <16>, /* OCP compliant interrupt */
	222	<59>, /* TX interrupt */
	223	<60>; /* RX interrupt */
	224	interrupt-names = "common", "tx", "rx";
	225	interrupt-parent = <&intc>;
	226	ti,buffer-size = <128>;
	227	ti,hwmods = "mcbsp1";
	228	};
	229
	230	mcbsp2: mcbsp@49022000 {
	231	compatible = "ti,omap3-mcbsp";
	232	reg = <0x49022000 0xff>,
	233	<0x49028000 0xff>;
	234	reg-names = "mpu", "sidetone";
	235	interrupts = <17>, /* OCP compliant interrupt */
	236	<62>, /* TX interrupt */
	237	<63>, /* RX interrupt */
	238	<4>; /* Sidetone */
	239	interrupt-names = "common", "tx", "rx", "sidetone";
	240	interrupt-parent = <&intc>;
	241	ti,buffer-size = <1280>;
	242	ti,hwmods = "mcbsp2";
	243	};
	244
	245	mcbsp3: mcbsp@49024000 {
	246	compatible = "ti,omap3-mcbsp";
	247	reg = <0x49024000 0xff>,
	248	<0x4902a000 0xff>;
	249	reg-names = "mpu", "sidetone";
	250	interrupts = <22>, /* OCP compliant interrupt */
	251	<89>, /* TX interrupt */
	252	<90>, /* RX interrupt */
	253	<5>; /* Sidetone */
	254	interrupt-names = "common", "tx", "rx", "sidetone";
	255	interrupt-parent = <&intc>;
	256	ti,buffer-size = <128>;
	257	ti,hwmods = "mcbsp3";
	258	};
	259
	260	mcbsp4: mcbsp@49026000 {
	261	compatible = "ti,omap3-mcbsp";
	262	reg = <0x49026000 0xff>;
	263	reg-names = "mpu";
	264	interrupts = <23>, /* OCP compliant interrupt */
	265	<54>, /* TX interrupt */
	266	<55>; /* RX interrupt */
	267	interrupt-names = "common", "tx", "rx";
	268	interrupt-parent = <&intc>;
	269	ti,buffer-size = <128>;
	270	ti,hwmods = "mcbsp4";
	271	};
	272
	273	mcbsp5: mcbsp@48096000 {
	274	compatible = "ti,omap3-mcbsp";
	275	reg = <0x48096000 0xff>;
	276	reg-names = "mpu";
	277	interrupts = <27>, /* OCP compliant interrupt */
	278	<81>, /* TX interrupt */
	279	<82>; /* RX interrupt */
280	interrupt-names = "common", "tx", "rx";
281	interrupt-parent = <&intc>;
282	ti,buffer-size = <128>;
283	ti,hwmods = "mcbsp5";
284	};
189892f4 BC	285	};
189892f4 BC	286	};