Commit | Line | Data |
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189892f4 BC |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
6d624eab | 11 | #include <dt-bindings/gpio/gpio.h> |
71fdc6e4 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
bcd3cca7 | 13 | #include <dt-bindings/pinctrl/omap.h> |
6d624eab | 14 | |
189892f4 BC |
15 | / { |
16 | compatible = "ti,omap3430", "ti,omap3"; | |
4c94ac29 | 17 | interrupt-parent = <&intc>; |
008a2ebc JMC |
18 | #address-cells = <1>; |
19 | #size-cells = <1>; | |
189892f4 | 20 | |
cf3c79de | 21 | aliases { |
20b80942 NM |
22 | i2c0 = &i2c1; |
23 | i2c1 = &i2c2; | |
24 | i2c2 = &i2c3; | |
cf3c79de RN |
25 | serial0 = &uart1; |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
cf3c79de RN |
28 | }; |
29 | ||
476b679a | 30 | cpus { |
eeb25fd5 LP |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
33 | ||
476b679a BC |
34 | cpu@0 { |
35 | compatible = "arm,cortex-a8"; | |
eeb25fd5 LP |
36 | device_type = "cpu"; |
37 | reg = <0x0>; | |
8d766fa2 NM |
38 | |
39 | clocks = <&dpll1_ck>; | |
40 | clock-names = "cpu"; | |
41 | ||
42 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
476b679a BC |
43 | }; |
44 | }; | |
45 | ||
2995a9e7 | 46 | pmu@54000000 { |
9b07b477 | 47 | compatible = "arm,cortex-a8-pmu"; |
d7c8f259 | 48 | reg = <0x54000000 0x800000>; |
9b07b477 JH |
49 | interrupts = <3>; |
50 | ti,hwmods = "debugss"; | |
51 | }; | |
52 | ||
189892f4 | 53 | /* |
161e89a6 | 54 | * The soc node represents the soc top level view. It is used for IPs |
189892f4 BC |
55 | * that are not memory mapped in the MPU view or for the MPU itself. |
56 | */ | |
57 | soc { | |
58 | compatible = "ti,omap-infra"; | |
476b679a BC |
59 | mpu { |
60 | compatible = "ti,omap3-mpu"; | |
61 | ti,hwmods = "mpu"; | |
62 | }; | |
63 | ||
4c051603 | 64 | iva: iva { |
476b679a BC |
65 | compatible = "ti,iva2.2"; |
66 | ti,hwmods = "iva"; | |
67 | ||
68 | dsp { | |
69 | compatible = "ti,omap3-c64"; | |
70 | }; | |
71 | }; | |
189892f4 BC |
72 | }; |
73 | ||
74 | /* | |
75 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
76 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 77 | * Since it will not bring real advantage to represent that in DT for |
189892f4 BC |
78 | * the moment, just use a fake OCP bus entry to represent the whole bus |
79 | * hierarchy. | |
80 | */ | |
f515f814 | 81 | ocp@68000000 { |
aa25729c | 82 | compatible = "ti,omap3-l3-smx", "simple-bus"; |
d7c8f259 TL |
83 | reg = <0x68000000 0x10000>; |
84 | interrupts = <9 10>; | |
189892f4 BC |
85 | #address-cells = <1>; |
86 | #size-cells = <1>; | |
87 | ranges; | |
88 | ti,hwmods = "l3_main"; | |
89 | ||
b8845074 TK |
90 | l4_core: l4@48000000 { |
91 | compatible = "ti,omap3-l4-core", "simple-bus"; | |
92 | #address-cells = <1>; | |
93 | #size-cells = <1>; | |
94 | ranges = <0 0x48000000 0x1000000>; | |
95 | ||
96 | scm: scm@2000 { | |
97 | compatible = "ti,omap3-scm", "simple-bus"; | |
98 | reg = <0x2000 0x2000>; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | ranges = <0 0x2000 0x2000>; | |
102 | ||
103 | omap3_pmx_core: pinmux@30 { | |
104 | compatible = "ti,omap3-padconf", | |
105 | "pinctrl-single"; | |
106 | reg = <0x30 0x238>; | |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | #interrupt-cells = <1>; | |
110 | interrupt-controller; | |
111 | pinctrl-single,register-width = <16>; | |
112 | pinctrl-single,function-mask = <0xff1f>; | |
113 | }; | |
114 | ||
115 | scm_conf: scm_conf@270 { | |
9a5e3f27 | 116 | compatible = "syscon", "simple-bus"; |
b8845074 TK |
117 | reg = <0x270 0x330>; |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
9a5e3f27 KVA |
120 | ranges = <0 0x270 0x330>; |
121 | ||
308cfdaf | 122 | pbias_regulator: pbias_regulator@2b0 { |
9a5e3f27 KVA |
123 | compatible = "ti,pbias-omap3", "ti,pbias-omap"; |
124 | reg = <0x2b0 0x4>; | |
125 | syscon = <&scm_conf>; | |
126 | pbias_mmc_reg: pbias_mmc_omap2430 { | |
127 | regulator-name = "pbias_mmc_omap2430"; | |
128 | regulator-min-microvolt = <1800000>; | |
129 | regulator-max-microvolt = <3000000>; | |
130 | }; | |
131 | }; | |
b8845074 TK |
132 | |
133 | scm_clocks: clocks { | |
134 | #address-cells = <1>; | |
135 | #size-cells = <0>; | |
136 | }; | |
137 | }; | |
138 | ||
139 | scm_clockdomains: clockdomains { | |
140 | }; | |
141 | ||
142 | omap3_pmx_wkup: pinmux@a00 { | |
143 | compatible = "ti,omap3-padconf", | |
144 | "pinctrl-single"; | |
145 | reg = <0xa00 0x5c>; | |
146 | #address-cells = <1>; | |
147 | #size-cells = <0>; | |
148 | #interrupt-cells = <1>; | |
149 | interrupt-controller; | |
150 | pinctrl-single,register-width = <16>; | |
151 | pinctrl-single,function-mask = <0xff1f>; | |
152 | }; | |
153 | }; | |
154 | }; | |
155 | ||
7ce93f31 TL |
156 | aes: aes@480c5000 { |
157 | compatible = "ti,omap3-aes"; | |
158 | ti,hwmods = "aes"; | |
159 | reg = <0x480c5000 0x50>; | |
160 | interrupts = <0>; | |
d6e5b7cc PR |
161 | dmas = <&sdma 65 &sdma 66>; |
162 | dma-names = "tx", "rx"; | |
7ce93f31 TL |
163 | }; |
164 | ||
657fc11c TK |
165 | prm: prm@48306000 { |
166 | compatible = "ti,omap3-prm"; | |
167 | reg = <0x48306000 0x4000>; | |
5081ce62 | 168 | interrupts = <11>; |
657fc11c TK |
169 | |
170 | prm_clocks: clocks { | |
171 | #address-cells = <1>; | |
172 | #size-cells = <0>; | |
173 | }; | |
174 | ||
175 | prm_clockdomains: clockdomains { | |
176 | }; | |
177 | }; | |
178 | ||
179 | cm: cm@48004000 { | |
180 | compatible = "ti,omap3-cm"; | |
181 | reg = <0x48004000 0x4000>; | |
182 | ||
183 | cm_clocks: clocks { | |
184 | #address-cells = <1>; | |
185 | #size-cells = <0>; | |
186 | }; | |
187 | ||
188 | cm_clockdomains: clockdomains { | |
189 | }; | |
190 | }; | |
191 | ||
510c0ffd JH |
192 | counter32k: counter@48320000 { |
193 | compatible = "ti,omap-counter32k"; | |
194 | reg = <0x48320000 0x20>; | |
195 | ti,hwmods = "counter_32k"; | |
196 | }; | |
197 | ||
d65c5423 | 198 | intc: interrupt-controller@48200000 { |
cab82b76 | 199 | compatible = "ti,omap3-intc"; |
189892f4 BC |
200 | interrupt-controller; |
201 | #interrupt-cells = <1>; | |
d65c5423 | 202 | reg = <0x48200000 0x1000>; |
189892f4 | 203 | }; |
cf3c79de | 204 | |
2c2dc545 JH |
205 | sdma: dma-controller@48056000 { |
206 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; | |
207 | reg = <0x48056000 0x1000>; | |
208 | interrupts = <12>, | |
209 | <13>, | |
210 | <14>, | |
211 | <15>; | |
212 | #dma-cells = <1>; | |
7e8d25d5 PU |
213 | dma-channels = <32>; |
214 | dma-requests = <96>; | |
2c2dc545 JH |
215 | }; |
216 | ||
385a64bb BC |
217 | gpio1: gpio@48310000 { |
218 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
219 | reg = <0x48310000 0x200>; |
220 | interrupts = <29>; | |
385a64bb | 221 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 222 | ti,gpio-always-on; |
385a64bb BC |
223 | gpio-controller; |
224 | #gpio-cells = <2>; | |
225 | interrupt-controller; | |
ff5c9059 | 226 | #interrupt-cells = <2>; |
385a64bb BC |
227 | }; |
228 | ||
229 | gpio2: gpio@49050000 { | |
230 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
231 | reg = <0x49050000 0x200>; |
232 | interrupts = <30>; | |
385a64bb BC |
233 | ti,hwmods = "gpio2"; |
234 | gpio-controller; | |
235 | #gpio-cells = <2>; | |
236 | interrupt-controller; | |
ff5c9059 | 237 | #interrupt-cells = <2>; |
385a64bb BC |
238 | }; |
239 | ||
240 | gpio3: gpio@49052000 { | |
241 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
242 | reg = <0x49052000 0x200>; |
243 | interrupts = <31>; | |
385a64bb BC |
244 | ti,hwmods = "gpio3"; |
245 | gpio-controller; | |
246 | #gpio-cells = <2>; | |
247 | interrupt-controller; | |
ff5c9059 | 248 | #interrupt-cells = <2>; |
385a64bb BC |
249 | }; |
250 | ||
251 | gpio4: gpio@49054000 { | |
252 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
253 | reg = <0x49054000 0x200>; |
254 | interrupts = <32>; | |
385a64bb BC |
255 | ti,hwmods = "gpio4"; |
256 | gpio-controller; | |
257 | #gpio-cells = <2>; | |
258 | interrupt-controller; | |
ff5c9059 | 259 | #interrupt-cells = <2>; |
385a64bb BC |
260 | }; |
261 | ||
262 | gpio5: gpio@49056000 { | |
263 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
264 | reg = <0x49056000 0x200>; |
265 | interrupts = <33>; | |
385a64bb BC |
266 | ti,hwmods = "gpio5"; |
267 | gpio-controller; | |
268 | #gpio-cells = <2>; | |
269 | interrupt-controller; | |
ff5c9059 | 270 | #interrupt-cells = <2>; |
385a64bb BC |
271 | }; |
272 | ||
273 | gpio6: gpio@49058000 { | |
274 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
275 | reg = <0x49058000 0x200>; |
276 | interrupts = <34>; | |
385a64bb BC |
277 | ti,hwmods = "gpio6"; |
278 | gpio-controller; | |
279 | #gpio-cells = <2>; | |
280 | interrupt-controller; | |
ff5c9059 | 281 | #interrupt-cells = <2>; |
385a64bb BC |
282 | }; |
283 | ||
19bfb76c | 284 | uart1: serial@4806a000 { |
cf3c79de | 285 | compatible = "ti,omap3-uart"; |
d7c8f259 | 286 | reg = <0x4806a000 0x2000>; |
31f0820a | 287 | interrupts-extended = <&intc 72>; |
d7c8f259 TL |
288 | dmas = <&sdma 49 &sdma 50>; |
289 | dma-names = "tx", "rx"; | |
cf3c79de RN |
290 | ti,hwmods = "uart1"; |
291 | clock-frequency = <48000000>; | |
292 | }; | |
293 | ||
19bfb76c | 294 | uart2: serial@4806c000 { |
cf3c79de | 295 | compatible = "ti,omap3-uart"; |
d7c8f259 | 296 | reg = <0x4806c000 0x400>; |
31f0820a | 297 | interrupts-extended = <&intc 73>; |
d7c8f259 TL |
298 | dmas = <&sdma 51 &sdma 52>; |
299 | dma-names = "tx", "rx"; | |
cf3c79de RN |
300 | ti,hwmods = "uart2"; |
301 | clock-frequency = <48000000>; | |
302 | }; | |
303 | ||
19bfb76c | 304 | uart3: serial@49020000 { |
cf3c79de | 305 | compatible = "ti,omap3-uart"; |
d7c8f259 | 306 | reg = <0x49020000 0x400>; |
31f0820a | 307 | interrupts-extended = <&intc 74>; |
d7c8f259 TL |
308 | dmas = <&sdma 53 &sdma 54>; |
309 | dma-names = "tx", "rx"; | |
cf3c79de RN |
310 | ti,hwmods = "uart3"; |
311 | clock-frequency = <48000000>; | |
312 | }; | |
313 | ||
ca59a5c1 BC |
314 | i2c1: i2c@48070000 { |
315 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
316 | reg = <0x48070000 0x80>; |
317 | interrupts = <56>; | |
318 | dmas = <&sdma 27 &sdma 28>; | |
319 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
320 | #address-cells = <1>; |
321 | #size-cells = <0>; | |
322 | ti,hwmods = "i2c1"; | |
323 | }; | |
324 | ||
325 | i2c2: i2c@48072000 { | |
326 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
327 | reg = <0x48072000 0x80>; |
328 | interrupts = <57>; | |
329 | dmas = <&sdma 29 &sdma 30>; | |
330 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
331 | #address-cells = <1>; |
332 | #size-cells = <0>; | |
333 | ti,hwmods = "i2c2"; | |
334 | }; | |
335 | ||
336 | i2c3: i2c@48060000 { | |
337 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
338 | reg = <0x48060000 0x80>; |
339 | interrupts = <61>; | |
340 | dmas = <&sdma 25 &sdma 26>; | |
341 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
342 | #address-cells = <1>; |
343 | #size-cells = <0>; | |
344 | ti,hwmods = "i2c3"; | |
345 | }; | |
fc72d248 | 346 | |
7ce93f31 TL |
347 | mailbox: mailbox@48094000 { |
348 | compatible = "ti,omap3-mailbox"; | |
349 | ti,hwmods = "mailbox"; | |
350 | reg = <0x48094000 0x200>; | |
351 | interrupts = <26>; | |
24df0453 | 352 | #mbox-cells = <1>; |
41ffada1 SA |
353 | ti,mbox-num-users = <2>; |
354 | ti,mbox-num-fifos = <2>; | |
d27704d1 SA |
355 | mbox_dsp: dsp { |
356 | ti,mbox-tx = <0 0 0>; | |
357 | ti,mbox-rx = <1 0 0>; | |
358 | }; | |
7ce93f31 TL |
359 | }; |
360 | ||
fc72d248 BC |
361 | mcspi1: spi@48098000 { |
362 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
363 | reg = <0x48098000 0x100>; |
364 | interrupts = <65>; | |
fc72d248 BC |
365 | #address-cells = <1>; |
366 | #size-cells = <0>; | |
367 | ti,hwmods = "mcspi1"; | |
368 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
369 | dmas = <&sdma 35>, |
370 | <&sdma 36>, | |
371 | <&sdma 37>, | |
372 | <&sdma 38>, | |
373 | <&sdma 39>, | |
374 | <&sdma 40>, | |
375 | <&sdma 41>, | |
376 | <&sdma 42>; | |
377 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
378 | "tx2", "rx2", "tx3", "rx3"; | |
fc72d248 BC |
379 | }; |
380 | ||
381 | mcspi2: spi@4809a000 { | |
382 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
383 | reg = <0x4809a000 0x100>; |
384 | interrupts = <66>; | |
fc72d248 BC |
385 | #address-cells = <1>; |
386 | #size-cells = <0>; | |
387 | ti,hwmods = "mcspi2"; | |
388 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
389 | dmas = <&sdma 43>, |
390 | <&sdma 44>, | |
391 | <&sdma 45>, | |
392 | <&sdma 46>; | |
393 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
394 | }; |
395 | ||
396 | mcspi3: spi@480b8000 { | |
397 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
398 | reg = <0x480b8000 0x100>; |
399 | interrupts = <91>; | |
fc72d248 BC |
400 | #address-cells = <1>; |
401 | #size-cells = <0>; | |
402 | ti,hwmods = "mcspi3"; | |
403 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
404 | dmas = <&sdma 15>, |
405 | <&sdma 16>, | |
406 | <&sdma 23>, | |
407 | <&sdma 24>; | |
408 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
409 | }; |
410 | ||
411 | mcspi4: spi@480ba000 { | |
412 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
413 | reg = <0x480ba000 0x100>; |
414 | interrupts = <48>; | |
fc72d248 BC |
415 | #address-cells = <1>; |
416 | #size-cells = <0>; | |
417 | ti,hwmods = "mcspi4"; | |
418 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
419 | dmas = <&sdma 70>, <&sdma 71>; |
420 | dma-names = "tx0", "rx0"; | |
fc72d248 | 421 | }; |
b3431f5b | 422 | |
d7c8f259 TL |
423 | hdqw1w: 1w@480b2000 { |
424 | compatible = "ti,omap3-1w"; | |
425 | reg = <0x480b2000 0x1000>; | |
426 | interrupts = <58>; | |
427 | ti,hwmods = "hdq1w"; | |
428 | }; | |
429 | ||
b3431f5b RN |
430 | mmc1: mmc@4809c000 { |
431 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
432 | reg = <0x4809c000 0x200>; |
433 | interrupts = <83>; | |
b3431f5b RN |
434 | ti,hwmods = "mmc1"; |
435 | ti,dual-volt; | |
2c2dc545 JH |
436 | dmas = <&sdma 61>, <&sdma 62>; |
437 | dma-names = "tx", "rx"; | |
cd042fe5 | 438 | pbias-supply = <&pbias_mmc_reg>; |
b3431f5b RN |
439 | }; |
440 | ||
441 | mmc2: mmc@480b4000 { | |
442 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
443 | reg = <0x480b4000 0x200>; |
444 | interrupts = <86>; | |
b3431f5b | 445 | ti,hwmods = "mmc2"; |
2c2dc545 JH |
446 | dmas = <&sdma 47>, <&sdma 48>; |
447 | dma-names = "tx", "rx"; | |
b3431f5b RN |
448 | }; |
449 | ||
450 | mmc3: mmc@480ad000 { | |
451 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
452 | reg = <0x480ad000 0x200>; |
453 | interrupts = <94>; | |
b3431f5b | 454 | ti,hwmods = "mmc3"; |
2c2dc545 JH |
455 | dmas = <&sdma 77>, <&sdma 78>; |
456 | dma-names = "tx", "rx"; | |
b3431f5b | 457 | }; |
94c30732 | 458 | |
7ce93f31 | 459 | mmu_isp: mmu@480bd400 { |
2055088b | 460 | #iommu-cells = <0>; |
b7cd9597 | 461 | compatible = "ti,omap2-iommu"; |
7ce93f31 | 462 | reg = <0x480bd400 0x80>; |
b7cd9597 FV |
463 | interrupts = <24>; |
464 | ti,hwmods = "mmu_isp"; | |
465 | ti,#tlb-entries = <8>; | |
7ce93f31 TL |
466 | }; |
467 | ||
40ac051d | 468 | mmu_iva: mmu@5d000000 { |
2055088b | 469 | #iommu-cells = <0>; |
40ac051d FV |
470 | compatible = "ti,omap2-iommu"; |
471 | reg = <0x5d000000 0x80>; | |
472 | interrupts = <28>; | |
473 | ti,hwmods = "mmu_iva"; | |
474 | status = "disabled"; | |
475 | }; | |
476 | ||
94c30732 XJ |
477 | wdt2: wdt@48314000 { |
478 | compatible = "ti,omap3-wdt"; | |
d7c8f259 | 479 | reg = <0x48314000 0x80>; |
94c30732 XJ |
480 | ti,hwmods = "wd_timer2"; |
481 | }; | |
0be484bf PU |
482 | |
483 | mcbsp1: mcbsp@48074000 { | |
484 | compatible = "ti,omap3-mcbsp"; | |
485 | reg = <0x48074000 0xff>; | |
486 | reg-names = "mpu"; | |
487 | interrupts = <16>, /* OCP compliant interrupt */ | |
488 | <59>, /* TX interrupt */ | |
489 | <60>; /* RX interrupt */ | |
490 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
491 | ti,buffer-size = <128>; |
492 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
493 | dmas = <&sdma 31>, |
494 | <&sdma 32>; | |
495 | dma-names = "tx", "rx"; | |
138e996c PU |
496 | clocks = <&mcbsp1_fck>; |
497 | clock-names = "fck"; | |
726322ce | 498 | status = "disabled"; |
0be484bf PU |
499 | }; |
500 | ||
501 | mcbsp2: mcbsp@49022000 { | |
502 | compatible = "ti,omap3-mcbsp"; | |
503 | reg = <0x49022000 0xff>, | |
504 | <0x49028000 0xff>; | |
505 | reg-names = "mpu", "sidetone"; | |
506 | interrupts = <17>, /* OCP compliant interrupt */ | |
507 | <62>, /* TX interrupt */ | |
508 | <63>, /* RX interrupt */ | |
509 | <4>; /* Sidetone */ | |
510 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 511 | ti,buffer-size = <1280>; |
eef6fcaa | 512 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
4e4ead73 SG |
513 | dmas = <&sdma 33>, |
514 | <&sdma 34>; | |
515 | dma-names = "tx", "rx"; | |
138e996c PU |
516 | clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; |
517 | clock-names = "fck", "ick"; | |
726322ce | 518 | status = "disabled"; |
0be484bf PU |
519 | }; |
520 | ||
521 | mcbsp3: mcbsp@49024000 { | |
522 | compatible = "ti,omap3-mcbsp"; | |
523 | reg = <0x49024000 0xff>, | |
524 | <0x4902a000 0xff>; | |
525 | reg-names = "mpu", "sidetone"; | |
526 | interrupts = <22>, /* OCP compliant interrupt */ | |
527 | <89>, /* TX interrupt */ | |
528 | <90>, /* RX interrupt */ | |
529 | <5>; /* Sidetone */ | |
530 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 531 | ti,buffer-size = <128>; |
eef6fcaa | 532 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
4e4ead73 SG |
533 | dmas = <&sdma 17>, |
534 | <&sdma 18>; | |
535 | dma-names = "tx", "rx"; | |
138e996c PU |
536 | clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; |
537 | clock-names = "fck", "ick"; | |
726322ce | 538 | status = "disabled"; |
0be484bf PU |
539 | }; |
540 | ||
541 | mcbsp4: mcbsp@49026000 { | |
542 | compatible = "ti,omap3-mcbsp"; | |
543 | reg = <0x49026000 0xff>; | |
544 | reg-names = "mpu"; | |
545 | interrupts = <23>, /* OCP compliant interrupt */ | |
546 | <54>, /* TX interrupt */ | |
547 | <55>; /* RX interrupt */ | |
548 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
549 | ti,buffer-size = <128>; |
550 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
551 | dmas = <&sdma 19>, |
552 | <&sdma 20>; | |
553 | dma-names = "tx", "rx"; | |
138e996c PU |
554 | clocks = <&mcbsp4_fck>; |
555 | clock-names = "fck"; | |
726322ce | 556 | status = "disabled"; |
0be484bf PU |
557 | }; |
558 | ||
559 | mcbsp5: mcbsp@48096000 { | |
560 | compatible = "ti,omap3-mcbsp"; | |
561 | reg = <0x48096000 0xff>; | |
562 | reg-names = "mpu"; | |
563 | interrupts = <27>, /* OCP compliant interrupt */ | |
564 | <81>, /* TX interrupt */ | |
565 | <82>; /* RX interrupt */ | |
566 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
567 | ti,buffer-size = <128>; |
568 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
569 | dmas = <&sdma 21>, |
570 | <&sdma 22>; | |
571 | dma-names = "tx", "rx"; | |
138e996c PU |
572 | clocks = <&mcbsp5_fck>; |
573 | clock-names = "fck"; | |
726322ce | 574 | status = "disabled"; |
0be484bf | 575 | }; |
fab8ad0b | 576 | |
7ce93f31 TL |
577 | sham: sham@480c3000 { |
578 | compatible = "ti,omap3-sham"; | |
579 | ti,hwmods = "sham"; | |
580 | reg = <0x480c3000 0x64>; | |
581 | interrupts = <49>; | |
d6e5b7cc PR |
582 | dmas = <&sdma 69>; |
583 | dma-names = "rx"; | |
7ce93f31 TL |
584 | }; |
585 | ||
586 | smartreflex_core: smartreflex@480cb000 { | |
587 | compatible = "ti,omap3-smartreflex-core"; | |
588 | ti,hwmods = "smartreflex_core"; | |
589 | reg = <0x480cb000 0x400>; | |
590 | interrupts = <19>; | |
591 | }; | |
592 | ||
593 | smartreflex_mpu_iva: smartreflex@480c9000 { | |
594 | compatible = "ti,omap3-smartreflex-iva"; | |
595 | ti,hwmods = "smartreflex_mpu_iva"; | |
596 | reg = <0x480c9000 0x400>; | |
597 | interrupts = <18>; | |
598 | }; | |
599 | ||
fab8ad0b | 600 | timer1: timer@48318000 { |
002e1ec5 | 601 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
602 | reg = <0x48318000 0x400>; |
603 | interrupts = <37>; | |
604 | ti,hwmods = "timer1"; | |
605 | ti,timer-alwon; | |
606 | }; | |
607 | ||
608 | timer2: timer@49032000 { | |
002e1ec5 | 609 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
610 | reg = <0x49032000 0x400>; |
611 | interrupts = <38>; | |
612 | ti,hwmods = "timer2"; | |
613 | }; | |
614 | ||
615 | timer3: timer@49034000 { | |
002e1ec5 | 616 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
617 | reg = <0x49034000 0x400>; |
618 | interrupts = <39>; | |
619 | ti,hwmods = "timer3"; | |
620 | }; | |
621 | ||
622 | timer4: timer@49036000 { | |
002e1ec5 | 623 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
624 | reg = <0x49036000 0x400>; |
625 | interrupts = <40>; | |
626 | ti,hwmods = "timer4"; | |
627 | }; | |
628 | ||
629 | timer5: timer@49038000 { | |
002e1ec5 | 630 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
631 | reg = <0x49038000 0x400>; |
632 | interrupts = <41>; | |
633 | ti,hwmods = "timer5"; | |
634 | ti,timer-dsp; | |
635 | }; | |
636 | ||
637 | timer6: timer@4903a000 { | |
002e1ec5 | 638 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
639 | reg = <0x4903a000 0x400>; |
640 | interrupts = <42>; | |
641 | ti,hwmods = "timer6"; | |
642 | ti,timer-dsp; | |
643 | }; | |
644 | ||
645 | timer7: timer@4903c000 { | |
002e1ec5 | 646 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
647 | reg = <0x4903c000 0x400>; |
648 | interrupts = <43>; | |
649 | ti,hwmods = "timer7"; | |
650 | ti,timer-dsp; | |
651 | }; | |
652 | ||
653 | timer8: timer@4903e000 { | |
002e1ec5 | 654 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
655 | reg = <0x4903e000 0x400>; |
656 | interrupts = <44>; | |
657 | ti,hwmods = "timer8"; | |
658 | ti,timer-pwm; | |
659 | ti,timer-dsp; | |
660 | }; | |
661 | ||
662 | timer9: timer@49040000 { | |
002e1ec5 | 663 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
664 | reg = <0x49040000 0x400>; |
665 | interrupts = <45>; | |
666 | ti,hwmods = "timer9"; | |
667 | ti,timer-pwm; | |
668 | }; | |
669 | ||
670 | timer10: timer@48086000 { | |
002e1ec5 | 671 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
672 | reg = <0x48086000 0x400>; |
673 | interrupts = <46>; | |
674 | ti,hwmods = "timer10"; | |
675 | ti,timer-pwm; | |
676 | }; | |
677 | ||
678 | timer11: timer@48088000 { | |
002e1ec5 | 679 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
680 | reg = <0x48088000 0x400>; |
681 | interrupts = <47>; | |
682 | ti,hwmods = "timer11"; | |
683 | ti,timer-pwm; | |
684 | }; | |
685 | ||
686 | timer12: timer@48304000 { | |
002e1ec5 | 687 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
688 | reg = <0x48304000 0x400>; |
689 | interrupts = <95>; | |
690 | ti,hwmods = "timer12"; | |
691 | ti,timer-alwon; | |
692 | ti,timer-secure; | |
693 | }; | |
af3eb366 RQ |
694 | |
695 | usbhstll: usbhstll@48062000 { | |
696 | compatible = "ti,usbhs-tll"; | |
697 | reg = <0x48062000 0x1000>; | |
698 | interrupts = <78>; | |
699 | ti,hwmods = "usb_tll_hs"; | |
700 | }; | |
701 | ||
702 | usbhshost: usbhshost@48064000 { | |
703 | compatible = "ti,usbhs-host"; | |
704 | reg = <0x48064000 0x400>; | |
705 | ti,hwmods = "usb_host_hs"; | |
706 | #address-cells = <1>; | |
707 | #size-cells = <1>; | |
708 | ranges; | |
709 | ||
710 | usbhsohci: ohci@48064400 { | |
a2525e54 | 711 | compatible = "ti,ohci-omap3"; |
af3eb366 RQ |
712 | reg = <0x48064400 0x400>; |
713 | interrupt-parent = <&intc>; | |
714 | interrupts = <76>; | |
715 | }; | |
716 | ||
717 | usbhsehci: ehci@48064800 { | |
a2525e54 | 718 | compatible = "ti,ehci-omap"; |
af3eb366 RQ |
719 | reg = <0x48064800 0x400>; |
720 | interrupt-parent = <&intc>; | |
721 | interrupts = <77>; | |
722 | }; | |
723 | }; | |
724 | ||
6e8489df FV |
725 | gpmc: gpmc@6e000000 { |
726 | compatible = "ti,omap3430-gpmc"; | |
727 | ti,hwmods = "gpmc"; | |
41644e75 | 728 | reg = <0x6e000000 0x02d0>; |
6e8489df | 729 | interrupts = <20>; |
201c7e33 FCJ |
730 | dmas = <&sdma 4>; |
731 | dma-names = "rxtx"; | |
6e8489df FV |
732 | gpmc,num-cs = <8>; |
733 | gpmc,num-waitpins = <4>; | |
734 | #address-cells = <2>; | |
735 | #size-cells = <1>; | |
44e47164 RQ |
736 | interrupt-controller; |
737 | #interrupt-cells = <2>; | |
94f56c8b RQ |
738 | gpio-controller; |
739 | #gpio-cells = <2>; | |
6e8489df | 740 | }; |
ad871c10 KVA |
741 | |
742 | usb_otg_hs: usb_otg_hs@480ab000 { | |
743 | compatible = "ti,omap3-musb"; | |
744 | reg = <0x480ab000 0x1000>; | |
304e71e0 | 745 | interrupts = <92>, <93>; |
ad871c10 KVA |
746 | interrupt-names = "mc", "dma"; |
747 | ti,hwmods = "usb_otg_hs"; | |
ad871c10 KVA |
748 | multipoint = <1>; |
749 | num-eps = <16>; | |
750 | ram-bits = <12>; | |
751 | }; | |
b8a7e42b TV |
752 | |
753 | dss: dss@48050000 { | |
754 | compatible = "ti,omap3-dss"; | |
755 | reg = <0x48050000 0x200>; | |
756 | status = "disabled"; | |
757 | ti,hwmods = "dss_core"; | |
758 | clocks = <&dss1_alwon_fck>; | |
759 | clock-names = "fck"; | |
760 | #address-cells = <1>; | |
761 | #size-cells = <1>; | |
762 | ranges; | |
763 | ||
764 | dispc@48050400 { | |
765 | compatible = "ti,omap3-dispc"; | |
766 | reg = <0x48050400 0x400>; | |
767 | interrupts = <25>; | |
768 | ti,hwmods = "dss_dispc"; | |
769 | clocks = <&dss1_alwon_fck>; | |
770 | clock-names = "fck"; | |
771 | }; | |
772 | ||
773 | dsi: encoder@4804fc00 { | |
774 | compatible = "ti,omap3-dsi"; | |
775 | reg = <0x4804fc00 0x200>, | |
776 | <0x4804fe00 0x40>, | |
777 | <0x4804ff00 0x20>; | |
778 | reg-names = "proto", "phy", "pll"; | |
779 | interrupts = <25>; | |
780 | status = "disabled"; | |
781 | ti,hwmods = "dss_dsi1"; | |
782 | clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; | |
783 | clock-names = "fck", "sys_clk"; | |
784 | }; | |
785 | ||
786 | rfbi: encoder@48050800 { | |
787 | compatible = "ti,omap3-rfbi"; | |
788 | reg = <0x48050800 0x100>; | |
789 | status = "disabled"; | |
790 | ti,hwmods = "dss_rfbi"; | |
791 | clocks = <&dss1_alwon_fck>, <&dss_ick>; | |
792 | clock-names = "fck", "ick"; | |
793 | }; | |
794 | ||
795 | venc: encoder@48050c00 { | |
796 | compatible = "ti,omap3-venc"; | |
797 | reg = <0x48050c00 0x100>; | |
798 | status = "disabled"; | |
799 | ti,hwmods = "dss_venc"; | |
800 | clocks = <&dss_tv_fck>; | |
801 | clock-names = "fck"; | |
802 | }; | |
803 | }; | |
782e25a4 SR |
804 | |
805 | ssi: ssi-controller@48058000 { | |
806 | compatible = "ti,omap3-ssi"; | |
807 | ti,hwmods = "ssi"; | |
808 | ||
809 | status = "disabled"; | |
810 | ||
811 | reg = <0x48058000 0x1000>, | |
812 | <0x48059000 0x1000>; | |
813 | reg-names = "sys", | |
814 | "gdd"; | |
815 | ||
816 | interrupts = <71>; | |
817 | interrupt-names = "gdd_mpu"; | |
818 | ||
819 | #address-cells = <1>; | |
820 | #size-cells = <1>; | |
821 | ranges; | |
822 | ||
823 | ssi_port1: ssi-port@4805a000 { | |
824 | compatible = "ti,omap3-ssi-port"; | |
825 | ||
826 | reg = <0x4805a000 0x800>, | |
827 | <0x4805a800 0x800>; | |
828 | reg-names = "tx", | |
829 | "rx"; | |
830 | ||
831 | interrupt-parent = <&intc>; | |
832 | interrupts = <67>, | |
833 | <68>; | |
834 | }; | |
835 | ||
836 | ssi_port2: ssi-port@4805b000 { | |
837 | compatible = "ti,omap3-ssi-port"; | |
838 | ||
839 | reg = <0x4805b000 0x800>, | |
840 | <0x4805b800 0x800>; | |
841 | reg-names = "tx", | |
842 | "rx"; | |
843 | ||
844 | interrupt-parent = <&intc>; | |
845 | interrupts = <69>, | |
846 | <70>; | |
847 | }; | |
848 | }; | |
189892f4 BC |
849 | }; |
850 | }; | |
657fc11c TK |
851 | |
852 | /include/ "omap3xxx-clocks.dtsi" |