[deliverable/linux.git] / arch / arm / boot / dts / omap3.dtsi

/*
 * Device Tree Source for OMAP3 SoC
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>

#include "skeleton.dtsi"

/ {
	compatible = "ti,omap3430", "ti,omap3";
	interrupt-parent = <&intc>;

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a8";
			device_type = "cpu";
			reg = <0x0>;

			clocks = <&dpll1_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
		};
	};

	pmu {
		compatible = "arm,cortex-a8-pmu";
		reg = <0x54000000 0x800000>;
		interrupts = <3>;
		ti,hwmods = "debugss";
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};

		iva {
			compatible = "ti,iva2.2";
			ti,hwmods = "iva";

			dsp {
				compatible = "ti,omap3-c64";
			};
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		reg = <0x68000000 0x10000>;
		interrupts = <9 10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		aes: aes@480c5000 {
			compatible = "ti,omap3-aes";
			ti,hwmods = "aes";
			reg = <0x480c5000 0x50>;
			interrupts = <0>;
		};

		prm: prm@48306000 {
			compatible = "ti,omap3-prm";
			reg = <0x48306000 0x4000>;

			prm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prm_clockdomains: clockdomains {
			};
		};

		cm: cm@48004000 {
			compatible = "ti,omap3-cm";
			reg = <0x48004000 0x4000>;

			cm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cm_clockdomains: clockdomains {
			};
		};

		scrm: scrm@48002000 {
			compatible = "ti,omap3-scrm";
			reg = <0x48002000 0x2000>;

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		counter32k: counter@48320000 {
			compatible = "ti,omap-counter32k";
			reg = <0x48320000 0x20>;
			ti,hwmods = "counter_32k";
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <96>;
			reg = <0x48200000 0x1000>;
		};

		sdma: dma-controller@48056000 {
			compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
			reg = <0x48056000 0x1000>;
			interrupts = <12>,
				     <13>,
				     <14>,
				     <15>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <96>;
		};

		omap3_pmx_core: pinmux@48002030 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x48002030 0x0238>;
			#address-cells = <1>;
			#size-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		omap3_pmx_wkup: pinmux@48002a00 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x48002a00 0x5c>;
			#address-cells = <1>;
			#size-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		gpio1: gpio@48310000 {
			compatible = "ti,omap3-gpio";
			reg = <0x48310000 0x200>;
			interrupts = <29>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@49050000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49050000 0x200>;
			interrupts = <30>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@49052000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49052000 0x200>;
			interrupts = <31>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@49054000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49054000 0x200>;
			interrupts = <32>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@49056000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49056000 0x200>;
			interrupts = <33>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@49058000 {
			compatible = "ti,omap3-gpio";
			reg = <0x49058000 0x200>;
			interrupts = <34>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap3-uart";
			reg = <0x4806a000 0x2000>;
			interrupts = <72>;
			dmas = <&sdma 49 &sdma 50>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap3-uart";
			reg = <0x4806c000 0x400>;
			interrupts = <73>;
			dmas = <&sdma 51 &sdma 52>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@49020000 {
			compatible = "ti,omap3-uart";
			reg = <0x49020000 0x400>;
			interrupts = <74>;
			dmas = <&sdma 53 &sdma 54>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48070000 0x80>;
			interrupts = <56>;
			dmas = <&sdma 27 &sdma 28>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48072000 0x80>;
			interrupts = <57>;
			dmas = <&sdma 29 &sdma 30>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap3-i2c";
			reg = <0x48060000 0x80>;
			interrupts = <61>;
			dmas = <&sdma 25 &sdma 26>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		mailbox: mailbox@48094000 {
			compatible = "ti,omap3-mailbox";
			ti,hwmods = "mailbox";
			reg = <0x48094000 0x200>;
			interrupts = <26>;
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x48098000 0x100>;
			interrupts = <65>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x4809a000 0x100>;
			interrupts = <66>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x480b8000 0x100>;
			interrupts = <91>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>,
			       <&sdma 16>,
			       <&sdma 23>,
			       <&sdma 24>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap2-mcspi";
			reg = <0x480ba000 0x100>;
			interrupts = <48>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		hdqw1w: 1w@480b2000 {
			compatible = "ti,omap3-1w";
			reg = <0x480b2000 0x1000>;
			interrupts = <58>;
			ti,hwmods = "hdq1w";
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x4809c000 0x200>;
			interrupts = <83>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x480b4000 0x200>;
			interrupts = <86>;
			ti,hwmods = "mmc2";
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap3-hsmmc";
			reg = <0x480ad000 0x200>;
			interrupts = <94>;
			ti,hwmods = "mmc3";
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmu_isp: mmu@480bd400 {
			compatible = "ti,omap2-iommu";
			reg = <0x480bd400 0x80>;
			interrupts = <24>;
			ti,hwmods = "mmu_isp";
			ti,#tlb-entries = <8>;
		};

		wdt2: wdt@48314000 {
			compatible = "ti,omap3-wdt";
			reg = <0x48314000 0x80>;
			ti,hwmods = "wd_timer2";
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <16>, /* OCP compliant interrupt */
				     <59>, /* TX interrupt */
				     <60>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 31>,
			       <&sdma 32>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp2: mcbsp@49022000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49022000 0xff>,
			      <0x49028000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <17>, /* OCP compliant interrupt */
				     <62>, /* TX interrupt */
				     <63>, /* RX interrupt */
				     <4>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			ti,buffer-size = <1280>;
			ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp3: mcbsp@49024000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49024000 0xff>,
			      <0x4902a000 0xff>;
			reg-names = "mpu", "sidetone";
			interrupts = <22>, /* OCP compliant interrupt */
				     <89>, /* TX interrupt */
				     <90>, /* RX interrupt */
				     <5>;  /* Sidetone */
			interrupt-names = "common", "tx", "rx", "sidetone";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp4: mcbsp@49026000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x49026000 0xff>;
			reg-names = "mpu";
			interrupts = <23>, /* OCP compliant interrupt */
				     <54>, /* TX interrupt */
				     <55>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp5: mcbsp@48096000 {
			compatible = "ti,omap3-mcbsp";
			reg = <0x48096000 0xff>;
			reg-names = "mpu";
			interrupts = <27>, /* OCP compliant interrupt */
				     <81>, /* TX interrupt */
				     <82>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp5";
			dmas = <&sdma 21>,
			       <&sdma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		sham: sham@480c3000 {
			compatible = "ti,omap3-sham";
			ti,hwmods = "sham";
			reg = <0x480c3000 0x64>;
			interrupts = <49>;
		};

		smartreflex_core: smartreflex@480cb000 {
			compatible = "ti,omap3-smartreflex-core";
			ti,hwmods = "smartreflex_core";
			reg = <0x480cb000 0x400>;
			interrupts = <19>;
		};

		smartreflex_mpu_iva: smartreflex@480c9000 {
			compatible = "ti,omap3-smartreflex-iva";
			ti,hwmods = "smartreflex_mpu_iva";
			reg = <0x480c9000 0x400>;
			interrupts = <18>;
		};

		timer1: timer@48318000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48318000 0x400>;
			interrupts = <37>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@49032000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49032000 0x400>;
			interrupts = <38>;
			ti,hwmods = "timer2";
		};

		timer3: timer@49034000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49034000 0x400>;
			interrupts = <39>;
			ti,hwmods = "timer3";
		};

		timer4: timer@49036000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49036000 0x400>;
			interrupts = <40>;
			ti,hwmods = "timer4";
		};

		timer5: timer@49038000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49038000 0x400>;
			interrupts = <41>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4903a000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903a000 0x400>;
			interrupts = <42>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
		};

		timer7: timer@4903c000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903c000 0x400>;
			interrupts = <43>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4903e000 {
			compatible = "ti,omap3430-timer";
			reg = <0x4903e000 0x400>;
			interrupts = <44>;
			ti,hwmods = "timer8";
			ti,timer-pwm;
			ti,timer-dsp;
		};

		timer9: timer@49040000 {
			compatible = "ti,omap3430-timer";
			reg = <0x49040000 0x400>;
			interrupts = <45>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48086000 0x400>;
			interrupts = <46>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48088000 0x400>;
			interrupts = <47>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		timer12: timer@48304000 {
			compatible = "ti,omap3430-timer";
			reg = <0x48304000 0x400>;
			interrupts = <95>;
			ti,hwmods = "timer12";
			ti,timer-alwon;
			ti,timer-secure;
		};

		usbhstll: usbhstll@48062000 {
			compatible = "ti,usbhs-tll";
			reg = <0x48062000 0x1000>;
			interrupts = <78>;
			ti,hwmods = "usb_tll_hs";
		};

		usbhshost: usbhshost@48064000 {
			compatible = "ti,usbhs-host";
			reg = <0x48064000 0x400>;
			ti,hwmods = "usb_host_hs";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usbhsohci: ohci@48064400 {
				compatible = "ti,ohci-omap3";
				reg = <0x48064400 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <76>;
			};

			usbhsehci: ehci@48064800 {
				compatible = "ti,ehci-omap";
				reg = <0x48064800 0x400>;
				interrupt-parent = <&intc>;
				interrupts = <77>;
			};
		};

		gpmc: gpmc@6e000000 {
			compatible = "ti,omap3430-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x6e000000 0x02d0>;
			interrupts = <20>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		usb_otg_hs: usb_otg_hs@480ab000 {
			compatible = "ti,omap3-musb";
			reg = <0x480ab000 0x1000>;
			interrupts = <92>, <93>;
			interrupt-names = "mc", "dma";
			ti,hwmods = "usb_otg_hs";
			multipoint = <1>;
			num-eps = <16>;
			ram-bits = <12>;
		};
	};
};

/include/ "omap3xxx-clocks.dtsi"
Commit	Line	Data
189892f4 BC	1	/*
	2	* Device Tree Source for OMAP3 SoC
	3	*
	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
6d624eab	11	#include <dt-bindings/gpio/gpio.h>
71fdc6e4	12	#include <dt-bindings/interrupt-controller/irq.h>
bcd3cca7	13	#include <dt-bindings/pinctrl/omap.h>
6d624eab	14
98ef7957	15	#include "skeleton.dtsi"
189892f4 BC	16
	17	/ {
	18	compatible = "ti,omap3430", "ti,omap3";
4c94ac29	19	interrupt-parent = <&intc>;
189892f4	20
cf3c79de	21	aliases {
20b80942 NM	22	i2c0 = &i2c1;
	23	i2c1 = &i2c2;
	24	i2c2 = &i2c3;
cf3c79de RN	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
cf3c79de RN	28	};
cf3c79de RN	29
476b679a	30	cpus {
eeb25fd5 LP	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
476b679a BC	34	cpu@0 {
476b679a BC	35	compatible = "arm,cortex-a8";
eeb25fd5 LP	36	device_type = "cpu";
eeb25fd5 LP	37	reg = <0x0>;
8d766fa2 NM	38
	39	clocks = <&dpll1_ck>;
	40	clock-names = "cpu";
	41
	42	clock-latency = <300000>; /* From omap-cpufreq driver */
476b679a BC	43	};
	44	};
	45
9b07b477 JH	46	pmu {
9b07b477 JH	47	compatible = "arm,cortex-a8-pmu";
d7c8f259	48	reg = <0x54000000 0x800000>;
9b07b477 JH	49	interrupts = <3>;
	50	ti,hwmods = "debugss";
	51	};
	52
189892f4	53	/*
161e89a6	54	* The soc node represents the soc top level view. It is used for IPs
189892f4 BC	55	* that are not memory mapped in the MPU view or for the MPU itself.
	56	*/
	57	soc {
	58	compatible = "ti,omap-infra";
476b679a BC	59	mpu {
	60	compatible = "ti,omap3-mpu";
	61	ti,hwmods = "mpu";
	62	};
	63
	64	iva {
	65	compatible = "ti,iva2.2";
	66	ti,hwmods = "iva";
	67
	68	dsp {
	69	compatible = "ti,omap3-c64";
	70	};
	71	};
189892f4 BC	72	};
	73
	74	/*
	75	* XXX: Use a flat representation of the OMAP3 interconnect.
	76	* The real OMAP interconnect network is quite complex.
	77	* Since that will not bring real advantage to represent that in DT for
	78	* the moment, just use a fake OCP bus entry to represent the whole bus
	79	* hierarchy.
	80	*/
	81	ocp {
	82	compatible = "simple-bus";
d7c8f259 TL	83	reg = <0x68000000 0x10000>;
d7c8f259 TL	84	interrupts = <9 10>;
189892f4 BC	85	#address-cells = <1>;
	86	#size-cells = <1>;
	87	ranges;
	88	ti,hwmods = "l3_main";
	89
7ce93f31 TL	90	aes: aes@480c5000 {
	91	compatible = "ti,omap3-aes";
	92	ti,hwmods = "aes";
	93	reg = <0x480c5000 0x50>;
	94	interrupts = <0>;
	95	};
	96
657fc11c TK	97	prm: prm@48306000 {
	98	compatible = "ti,omap3-prm";
	99	reg = <0x48306000 0x4000>;
	100
	101	prm_clocks: clocks {
	102	#address-cells = <1>;
	103	#size-cells = <0>;
	104	};
	105
	106	prm_clockdomains: clockdomains {
	107	};
	108	};
	109
	110	cm: cm@48004000 {
	111	compatible = "ti,omap3-cm";
	112	reg = <0x48004000 0x4000>;
	113
	114	cm_clocks: clocks {
	115	#address-cells = <1>;
	116	#size-cells = <0>;
	117	};
	118
	119	cm_clockdomains: clockdomains {
	120	};
	121	};
	122
	123	scrm: scrm@48002000 {
	124	compatible = "ti,omap3-scrm";
	125	reg = <0x48002000 0x2000>;
	126
	127	scrm_clocks: clocks {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	};
	131
	132	scrm_clockdomains: clockdomains {
	133	};
	134	};
	135
510c0ffd JH	136	counter32k: counter@48320000 {
	137	compatible = "ti,omap-counter32k";
	138	reg = <0x48320000 0x20>;
	139	ti,hwmods = "counter_32k";
	140	};
	141
d65c5423 BC	142	intc: interrupt-controller@48200000 {
d65c5423 BC	143	compatible = "ti,omap2-intc";
189892f4 BC	144	interrupt-controller;
189892f4 BC	145	#interrupt-cells = <1>;
d65c5423 BC	146	ti,intc-size = <96>;
d65c5423 BC	147	reg = <0x48200000 0x1000>;
189892f4	148	};
cf3c79de	149
2c2dc545 JH	150	sdma: dma-controller@48056000 {
	151	compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
	152	reg = <0x48056000 0x1000>;
	153	interrupts = <12>,
	154	<13>,
	155	<14>,
	156	<15>;
	157	#dma-cells = <1>;
	158	#dma-channels = <32>;
	159	#dma-requests = <96>;
	160	};
	161
679e3310 TL	162	omap3_pmx_core: pinmux@48002030 {
679e3310 TL	163	compatible = "ti,omap3-padconf", "pinctrl-single";
3d495383	164	reg = <0x48002030 0x0238>;
679e3310 TL	165	#address-cells = <1>;
679e3310 TL	166	#size-cells = <0>;
30a69ef7 TL	167	#interrupt-cells = <1>;
30a69ef7 TL	168	interrupt-controller;
679e3310	169	pinctrl-single,register-width = <16>;
d623a0e1	170	pinctrl-single,function-mask = <0xff1f>;
679e3310 TL	171	};
679e3310 TL	172
b7317777	173	omap3_pmx_wkup: pinmux@48002a00 {
679e3310	174	compatible = "ti,omap3-padconf", "pinctrl-single";
161e89a6	175	reg = <0x48002a00 0x5c>;
679e3310 TL	176	#address-cells = <1>;
679e3310 TL	177	#size-cells = <0>;
30a69ef7 TL	178	#interrupt-cells = <1>;
30a69ef7 TL	179	interrupt-controller;
679e3310	180	pinctrl-single,register-width = <16>;
d623a0e1	181	pinctrl-single,function-mask = <0xff1f>;
679e3310 TL	182	};
679e3310 TL	183
385a64bb BC	184	gpio1: gpio@48310000 {
385a64bb BC	185	compatible = "ti,omap3-gpio";
e299185a JH	186	reg = <0x48310000 0x200>;
e299185a JH	187	interrupts = <29>;
385a64bb	188	ti,hwmods = "gpio1";
e4b9b9f3	189	ti,gpio-always-on;
385a64bb BC	190	gpio-controller;
	191	#gpio-cells = <2>;
	192	interrupt-controller;
ff5c9059	193	#interrupt-cells = <2>;
385a64bb BC	194	};
	195
	196	gpio2: gpio@49050000 {
	197	compatible = "ti,omap3-gpio";
e299185a JH	198	reg = <0x49050000 0x200>;
e299185a JH	199	interrupts = <30>;
385a64bb BC	200	ti,hwmods = "gpio2";
	201	gpio-controller;
	202	#gpio-cells = <2>;
	203	interrupt-controller;
ff5c9059	204	#interrupt-cells = <2>;
385a64bb BC	205	};
	206
	207	gpio3: gpio@49052000 {
	208	compatible = "ti,omap3-gpio";
e299185a JH	209	reg = <0x49052000 0x200>;
e299185a JH	210	interrupts = <31>;
385a64bb BC	211	ti,hwmods = "gpio3";
	212	gpio-controller;
	213	#gpio-cells = <2>;
	214	interrupt-controller;
ff5c9059	215	#interrupt-cells = <2>;
385a64bb BC	216	};
	217
	218	gpio4: gpio@49054000 {
	219	compatible = "ti,omap3-gpio";
e299185a JH	220	reg = <0x49054000 0x200>;
e299185a JH	221	interrupts = <32>;
385a64bb BC	222	ti,hwmods = "gpio4";
	223	gpio-controller;
	224	#gpio-cells = <2>;
	225	interrupt-controller;
ff5c9059	226	#interrupt-cells = <2>;
385a64bb BC	227	};
	228
	229	gpio5: gpio@49056000 {
	230	compatible = "ti,omap3-gpio";
e299185a JH	231	reg = <0x49056000 0x200>;
e299185a JH	232	interrupts = <33>;
385a64bb BC	233	ti,hwmods = "gpio5";
	234	gpio-controller;
	235	#gpio-cells = <2>;
	236	interrupt-controller;
ff5c9059	237	#interrupt-cells = <2>;
385a64bb BC	238	};
	239
	240	gpio6: gpio@49058000 {
	241	compatible = "ti,omap3-gpio";
e299185a JH	242	reg = <0x49058000 0x200>;
e299185a JH	243	interrupts = <34>;
385a64bb BC	244	ti,hwmods = "gpio6";
	245	gpio-controller;
	246	#gpio-cells = <2>;
	247	interrupt-controller;
ff5c9059	248	#interrupt-cells = <2>;
385a64bb BC	249	};
385a64bb BC	250
19bfb76c	251	uart1: serial@4806a000 {
cf3c79de	252	compatible = "ti,omap3-uart";
d7c8f259 TL	253	reg = <0x4806a000 0x2000>;
	254	interrupts = <72>;
	255	dmas = <&sdma 49 &sdma 50>;
	256	dma-names = "tx", "rx";
cf3c79de RN	257	ti,hwmods = "uart1";
	258	clock-frequency = <48000000>;
	259	};
	260
19bfb76c	261	uart2: serial@4806c000 {
cf3c79de	262	compatible = "ti,omap3-uart";
d7c8f259 TL	263	reg = <0x4806c000 0x400>;
	264	interrupts = <73>;
	265	dmas = <&sdma 51 &sdma 52>;
	266	dma-names = "tx", "rx";
cf3c79de RN	267	ti,hwmods = "uart2";
	268	clock-frequency = <48000000>;
	269	};
	270
19bfb76c	271	uart3: serial@49020000 {
cf3c79de	272	compatible = "ti,omap3-uart";
d7c8f259 TL	273	reg = <0x49020000 0x400>;
	274	interrupts = <74>;
	275	dmas = <&sdma 53 &sdma 54>;
	276	dma-names = "tx", "rx";
cf3c79de RN	277	ti,hwmods = "uart3";
	278	clock-frequency = <48000000>;
	279	};
	280
ca59a5c1 BC	281	i2c1: i2c@48070000 {
ca59a5c1 BC	282	compatible = "ti,omap3-i2c";
d7c8f259 TL	283	reg = <0x48070000 0x80>;
	284	interrupts = <56>;
	285	dmas = <&sdma 27 &sdma 28>;
	286	dma-names = "tx", "rx";
ca59a5c1 BC	287	#address-cells = <1>;
	288	#size-cells = <0>;
	289	ti,hwmods = "i2c1";
	290	};
	291
	292	i2c2: i2c@48072000 {
	293	compatible = "ti,omap3-i2c";
d7c8f259 TL	294	reg = <0x48072000 0x80>;
	295	interrupts = <57>;
	296	dmas = <&sdma 29 &sdma 30>;
	297	dma-names = "tx", "rx";
ca59a5c1 BC	298	#address-cells = <1>;
	299	#size-cells = <0>;
	300	ti,hwmods = "i2c2";
	301	};
	302
	303	i2c3: i2c@48060000 {
	304	compatible = "ti,omap3-i2c";
d7c8f259 TL	305	reg = <0x48060000 0x80>;
	306	interrupts = <61>;
	307	dmas = <&sdma 25 &sdma 26>;
	308	dma-names = "tx", "rx";
ca59a5c1 BC	309	#address-cells = <1>;
	310	#size-cells = <0>;
	311	ti,hwmods = "i2c3";
	312	};
fc72d248	313
7ce93f31 TL	314	mailbox: mailbox@48094000 {
	315	compatible = "ti,omap3-mailbox";
	316	ti,hwmods = "mailbox";
	317	reg = <0x48094000 0x200>;
	318	interrupts = <26>;
	319	};
	320
fc72d248 BC	321	mcspi1: spi@48098000 {
fc72d248 BC	322	compatible = "ti,omap2-mcspi";
d7c8f259 TL	323	reg = <0x48098000 0x100>;
d7c8f259 TL	324	interrupts = <65>;
fc72d248 BC	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327	ti,hwmods = "mcspi1";
	328	ti,spi-num-cs = <4>;
2c2dc545 JH	329	dmas = <&sdma 35>,
	330	<&sdma 36>,
	331	<&sdma 37>,
	332	<&sdma 38>,
	333	<&sdma 39>,
	334	<&sdma 40>,
	335	<&sdma 41>,
	336	<&sdma 42>;
	337	dma-names = "tx0", "rx0", "tx1", "rx1",
	338	"tx2", "rx2", "tx3", "rx3";
fc72d248 BC	339	};
	340
	341	mcspi2: spi@4809a000 {
	342	compatible = "ti,omap2-mcspi";
d7c8f259 TL	343	reg = <0x4809a000 0x100>;
d7c8f259 TL	344	interrupts = <66>;
fc72d248 BC	345	#address-cells = <1>;
	346	#size-cells = <0>;
	347	ti,hwmods = "mcspi2";
	348	ti,spi-num-cs = <2>;
2c2dc545 JH	349	dmas = <&sdma 43>,
	350	<&sdma 44>,
	351	<&sdma 45>,
	352	<&sdma 46>;
	353	dma-names = "tx0", "rx0", "tx1", "rx1";
fc72d248 BC	354	};
	355
	356	mcspi3: spi@480b8000 {
	357	compatible = "ti,omap2-mcspi";
d7c8f259 TL	358	reg = <0x480b8000 0x100>;
d7c8f259 TL	359	interrupts = <91>;
fc72d248 BC	360	#address-cells = <1>;
	361	#size-cells = <0>;
	362	ti,hwmods = "mcspi3";
	363	ti,spi-num-cs = <2>;
2c2dc545 JH	364	dmas = <&sdma 15>,
	365	<&sdma 16>,
	366	<&sdma 23>,
	367	<&sdma 24>;
	368	dma-names = "tx0", "rx0", "tx1", "rx1";
fc72d248 BC	369	};
	370
	371	mcspi4: spi@480ba000 {
	372	compatible = "ti,omap2-mcspi";
d7c8f259 TL	373	reg = <0x480ba000 0x100>;
d7c8f259 TL	374	interrupts = <48>;
fc72d248 BC	375	#address-cells = <1>;
	376	#size-cells = <0>;
	377	ti,hwmods = "mcspi4";
	378	ti,spi-num-cs = <1>;
2c2dc545 JH	379	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	380	dma-names = "tx0", "rx0";
fc72d248	381	};
b3431f5b	382
d7c8f259 TL	383	hdqw1w: 1w@480b2000 {
	384	compatible = "ti,omap3-1w";
	385	reg = <0x480b2000 0x1000>;
	386	interrupts = <58>;
	387	ti,hwmods = "hdq1w";
	388	};
	389
b3431f5b RN	390	mmc1: mmc@4809c000 {
b3431f5b RN	391	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	392	reg = <0x4809c000 0x200>;
d7c8f259 TL	393	interrupts = <83>;
b3431f5b RN	394	ti,hwmods = "mmc1";
b3431f5b RN	395	ti,dual-volt;
2c2dc545 JH	396	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	397	dma-names = "tx", "rx";
b3431f5b RN	398	};
	399
	400	mmc2: mmc@480b4000 {
	401	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	402	reg = <0x480b4000 0x200>;
d7c8f259 TL	403	interrupts = <86>;
b3431f5b	404	ti,hwmods = "mmc2";
2c2dc545 JH	405	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	406	dma-names = "tx", "rx";
b3431f5b RN	407	};
	408
	409	mmc3: mmc@480ad000 {
	410	compatible = "ti,omap3-hsmmc";
d7c8f259 TL	411	reg = <0x480ad000 0x200>;
d7c8f259 TL	412	interrupts = <94>;
b3431f5b	413	ti,hwmods = "mmc3";
2c2dc545 JH	414	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	415	dma-names = "tx", "rx";
b3431f5b	416	};
94c30732	417
7ce93f31	418	mmu_isp: mmu@480bd400 {
b7cd9597	419	compatible = "ti,omap2-iommu";
7ce93f31	420	reg = <0x480bd400 0x80>;
b7cd9597 FV	421	interrupts = <24>;
	422	ti,hwmods = "mmu_isp";
	423	ti,#tlb-entries = <8>;
7ce93f31 TL	424	};
7ce93f31 TL	425
94c30732 XJ	426	wdt2: wdt@48314000 {
94c30732 XJ	427	compatible = "ti,omap3-wdt";
d7c8f259	428	reg = <0x48314000 0x80>;
94c30732 XJ	429	ti,hwmods = "wd_timer2";
94c30732 XJ	430	};
0be484bf PU	431
	432	mcbsp1: mcbsp@48074000 {
	433	compatible = "ti,omap3-mcbsp";
	434	reg = <0x48074000 0xff>;
	435	reg-names = "mpu";
	436	interrupts = <16>, /* OCP compliant interrupt */
	437	<59>, /* TX interrupt */
	438	<60>; /* RX interrupt */
	439	interrupt-names = "common", "tx", "rx";
0be484bf PU	440	ti,buffer-size = <128>;
0be484bf PU	441	ti,hwmods = "mcbsp1";
4e4ead73 SG	442	dmas = <&sdma 31>,
	443	<&sdma 32>;
	444	dma-names = "tx", "rx";
726322ce	445	status = "disabled";
0be484bf PU	446	};
	447
	448	mcbsp2: mcbsp@49022000 {
	449	compatible = "ti,omap3-mcbsp";
	450	reg = <0x49022000 0xff>,
	451	<0x49028000 0xff>;
	452	reg-names = "mpu", "sidetone";
	453	interrupts = <17>, /* OCP compliant interrupt */
	454	<62>, /* TX interrupt */
	455	<63>, /* RX interrupt */
	456	<4>; /* Sidetone */
	457	interrupt-names = "common", "tx", "rx", "sidetone";
0be484bf	458	ti,buffer-size = <1280>;
eef6fcaa	459	ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
4e4ead73 SG	460	dmas = <&sdma 33>,
	461	<&sdma 34>;
	462	dma-names = "tx", "rx";
726322ce	463	status = "disabled";
0be484bf PU	464	};
	465
	466	mcbsp3: mcbsp@49024000 {
	467	compatible = "ti,omap3-mcbsp";
	468	reg = <0x49024000 0xff>,
	469	<0x4902a000 0xff>;
	470	reg-names = "mpu", "sidetone";
	471	interrupts = <22>, /* OCP compliant interrupt */
	472	<89>, /* TX interrupt */
	473	<90>, /* RX interrupt */
	474	<5>; /* Sidetone */
	475	interrupt-names = "common", "tx", "rx", "sidetone";
0be484bf	476	ti,buffer-size = <128>;
eef6fcaa	477	ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
4e4ead73 SG	478	dmas = <&sdma 17>,
	479	<&sdma 18>;
	480	dma-names = "tx", "rx";
726322ce	481	status = "disabled";
0be484bf PU	482	};
	483
	484	mcbsp4: mcbsp@49026000 {
	485	compatible = "ti,omap3-mcbsp";
	486	reg = <0x49026000 0xff>;
	487	reg-names = "mpu";
	488	interrupts = <23>, /* OCP compliant interrupt */
	489	<54>, /* TX interrupt */
	490	<55>; /* RX interrupt */
	491	interrupt-names = "common", "tx", "rx";
0be484bf PU	492	ti,buffer-size = <128>;
0be484bf PU	493	ti,hwmods = "mcbsp4";
4e4ead73 SG	494	dmas = <&sdma 19>,
	495	<&sdma 20>;
	496	dma-names = "tx", "rx";
726322ce	497	status = "disabled";
0be484bf PU	498	};
	499
	500	mcbsp5: mcbsp@48096000 {
	501	compatible = "ti,omap3-mcbsp";
	502	reg = <0x48096000 0xff>;
	503	reg-names = "mpu";
	504	interrupts = <27>, /* OCP compliant interrupt */
	505	<81>, /* TX interrupt */
	506	<82>; /* RX interrupt */
	507	interrupt-names = "common", "tx", "rx";
0be484bf PU	508	ti,buffer-size = <128>;
0be484bf PU	509	ti,hwmods = "mcbsp5";
4e4ead73 SG	510	dmas = <&sdma 21>,
	511	<&sdma 22>;
	512	dma-names = "tx", "rx";
726322ce	513	status = "disabled";
0be484bf	514	};
fab8ad0b	515
7ce93f31 TL	516	sham: sham@480c3000 {
	517	compatible = "ti,omap3-sham";
	518	ti,hwmods = "sham";
	519	reg = <0x480c3000 0x64>;
	520	interrupts = <49>;
	521	};
	522
	523	smartreflex_core: smartreflex@480cb000 {
	524	compatible = "ti,omap3-smartreflex-core";
	525	ti,hwmods = "smartreflex_core";
	526	reg = <0x480cb000 0x400>;
	527	interrupts = <19>;
	528	};
	529
	530	smartreflex_mpu_iva: smartreflex@480c9000 {
	531	compatible = "ti,omap3-smartreflex-iva";
	532	ti,hwmods = "smartreflex_mpu_iva";
	533	reg = <0x480c9000 0x400>;
	534	interrupts = <18>;
	535	};
	536
fab8ad0b	537	timer1: timer@48318000 {
002e1ec5	538	compatible = "ti,omap3430-timer";
fab8ad0b JH	539	reg = <0x48318000 0x400>;
	540	interrupts = <37>;
	541	ti,hwmods = "timer1";
	542	ti,timer-alwon;
	543	};
	544
	545	timer2: timer@49032000 {
002e1ec5	546	compatible = "ti,omap3430-timer";
fab8ad0b JH	547	reg = <0x49032000 0x400>;
	548	interrupts = <38>;
	549	ti,hwmods = "timer2";
	550	};
	551
	552	timer3: timer@49034000 {
002e1ec5	553	compatible = "ti,omap3430-timer";
fab8ad0b JH	554	reg = <0x49034000 0x400>;
	555	interrupts = <39>;
	556	ti,hwmods = "timer3";
	557	};
	558
	559	timer4: timer@49036000 {
002e1ec5	560	compatible = "ti,omap3430-timer";
fab8ad0b JH	561	reg = <0x49036000 0x400>;
	562	interrupts = <40>;
	563	ti,hwmods = "timer4";
	564	};
	565
	566	timer5: timer@49038000 {
002e1ec5	567	compatible = "ti,omap3430-timer";
fab8ad0b JH	568	reg = <0x49038000 0x400>;
	569	interrupts = <41>;
	570	ti,hwmods = "timer5";
	571	ti,timer-dsp;
	572	};
	573
	574	timer6: timer@4903a000 {
002e1ec5	575	compatible = "ti,omap3430-timer";
fab8ad0b JH	576	reg = <0x4903a000 0x400>;
	577	interrupts = <42>;
	578	ti,hwmods = "timer6";
	579	ti,timer-dsp;
	580	};
	581
	582	timer7: timer@4903c000 {
002e1ec5	583	compatible = "ti,omap3430-timer";
fab8ad0b JH	584	reg = <0x4903c000 0x400>;
	585	interrupts = <43>;
	586	ti,hwmods = "timer7";
	587	ti,timer-dsp;
	588	};
	589
	590	timer8: timer@4903e000 {
002e1ec5	591	compatible = "ti,omap3430-timer";
fab8ad0b JH	592	reg = <0x4903e000 0x400>;
	593	interrupts = <44>;
	594	ti,hwmods = "timer8";
	595	ti,timer-pwm;
	596	ti,timer-dsp;
	597	};
	598
	599	timer9: timer@49040000 {
002e1ec5	600	compatible = "ti,omap3430-timer";
fab8ad0b JH	601	reg = <0x49040000 0x400>;
	602	interrupts = <45>;
	603	ti,hwmods = "timer9";
	604	ti,timer-pwm;
	605	};
	606
	607	timer10: timer@48086000 {
002e1ec5	608	compatible = "ti,omap3430-timer";
fab8ad0b JH	609	reg = <0x48086000 0x400>;
	610	interrupts = <46>;
	611	ti,hwmods = "timer10";
	612	ti,timer-pwm;
	613	};
	614
	615	timer11: timer@48088000 {
002e1ec5	616	compatible = "ti,omap3430-timer";
fab8ad0b JH	617	reg = <0x48088000 0x400>;
	618	interrupts = <47>;
	619	ti,hwmods = "timer11";
	620	ti,timer-pwm;
	621	};
	622
	623	timer12: timer@48304000 {
002e1ec5	624	compatible = "ti,omap3430-timer";
fab8ad0b JH	625	reg = <0x48304000 0x400>;
	626	interrupts = <95>;
	627	ti,hwmods = "timer12";
	628	ti,timer-alwon;
	629	ti,timer-secure;
	630	};
af3eb366 RQ	631
	632	usbhstll: usbhstll@48062000 {
	633	compatible = "ti,usbhs-tll";
	634	reg = <0x48062000 0x1000>;
	635	interrupts = <78>;
	636	ti,hwmods = "usb_tll_hs";
	637	};
	638
	639	usbhshost: usbhshost@48064000 {
	640	compatible = "ti,usbhs-host";
	641	reg = <0x48064000 0x400>;
	642	ti,hwmods = "usb_host_hs";
	643	#address-cells = <1>;
	644	#size-cells = <1>;
	645	ranges;
	646
	647	usbhsohci: ohci@48064400 {
a2525e54	648	compatible = "ti,ohci-omap3";
af3eb366 RQ	649	reg = <0x48064400 0x400>;
	650	interrupt-parent = <&intc>;
	651	interrupts = <76>;
	652	};
	653
	654	usbhsehci: ehci@48064800 {
a2525e54	655	compatible = "ti,ehci-omap";
af3eb366 RQ	656	reg = <0x48064800 0x400>;
	657	interrupt-parent = <&intc>;
	658	interrupts = <77>;
	659	};
	660	};
	661
6e8489df FV	662	gpmc: gpmc@6e000000 {
	663	compatible = "ti,omap3430-gpmc";
	664	ti,hwmods = "gpmc";
41644e75	665	reg = <0x6e000000 0x02d0>;
6e8489df FV	666	interrupts = <20>;
	667	gpmc,num-cs = <8>;
	668	gpmc,num-waitpins = <4>;
	669	#address-cells = <2>;
	670	#size-cells = <1>;
	671	};
ad871c10 KVA	672
	673	usb_otg_hs: usb_otg_hs@480ab000 {
	674	compatible = "ti,omap3-musb";
	675	reg = <0x480ab000 0x1000>;
304e71e0	676	interrupts = <92>, <93>;
ad871c10 KVA	677	interrupt-names = "mc", "dma";
ad871c10 KVA	678	ti,hwmods = "usb_otg_hs";
ad871c10 KVA	679	multipoint = <1>;
	680	num-eps = <16>;
	681	ram-bits = <12>;
	682	};
189892f4 BC	683	};
189892f4 BC	684	};
657fc11c TK	685
657fc11c TK	686	/include/ "omap3xxx-clocks.dtsi"