Commit | Line | Data |
---|---|---|
189892f4 BC |
1 | /* |
2 | * Device Tree Source for OMAP3 SoC | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
6d624eab | 11 | #include <dt-bindings/gpio/gpio.h> |
71fdc6e4 | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
bcd3cca7 | 13 | #include <dt-bindings/pinctrl/omap.h> |
6d624eab | 14 | |
98ef7957 | 15 | #include "skeleton.dtsi" |
189892f4 BC |
16 | |
17 | / { | |
18 | compatible = "ti,omap3430", "ti,omap3"; | |
4c94ac29 | 19 | interrupt-parent = <&intc>; |
189892f4 | 20 | |
cf3c79de | 21 | aliases { |
20b80942 NM |
22 | i2c0 = &i2c1; |
23 | i2c1 = &i2c2; | |
24 | i2c2 = &i2c3; | |
cf3c79de RN |
25 | serial0 = &uart1; |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
cf3c79de RN |
28 | }; |
29 | ||
476b679a | 30 | cpus { |
eeb25fd5 LP |
31 | #address-cells = <1>; |
32 | #size-cells = <0>; | |
33 | ||
476b679a BC |
34 | cpu@0 { |
35 | compatible = "arm,cortex-a8"; | |
eeb25fd5 LP |
36 | device_type = "cpu"; |
37 | reg = <0x0>; | |
8d766fa2 NM |
38 | |
39 | clocks = <&dpll1_ck>; | |
40 | clock-names = "cpu"; | |
41 | ||
42 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
476b679a BC |
43 | }; |
44 | }; | |
45 | ||
9b07b477 JH |
46 | pmu { |
47 | compatible = "arm,cortex-a8-pmu"; | |
d7c8f259 | 48 | reg = <0x54000000 0x800000>; |
9b07b477 JH |
49 | interrupts = <3>; |
50 | ti,hwmods = "debugss"; | |
51 | }; | |
52 | ||
189892f4 | 53 | /* |
161e89a6 | 54 | * The soc node represents the soc top level view. It is used for IPs |
189892f4 BC |
55 | * that are not memory mapped in the MPU view or for the MPU itself. |
56 | */ | |
57 | soc { | |
58 | compatible = "ti,omap-infra"; | |
476b679a BC |
59 | mpu { |
60 | compatible = "ti,omap3-mpu"; | |
61 | ti,hwmods = "mpu"; | |
62 | }; | |
63 | ||
64 | iva { | |
65 | compatible = "ti,iva2.2"; | |
66 | ti,hwmods = "iva"; | |
67 | ||
68 | dsp { | |
69 | compatible = "ti,omap3-c64"; | |
70 | }; | |
71 | }; | |
189892f4 BC |
72 | }; |
73 | ||
74 | /* | |
75 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
76 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 77 | * Since it will not bring real advantage to represent that in DT for |
189892f4 BC |
78 | * the moment, just use a fake OCP bus entry to represent the whole bus |
79 | * hierarchy. | |
80 | */ | |
81 | ocp { | |
82 | compatible = "simple-bus"; | |
d7c8f259 TL |
83 | reg = <0x68000000 0x10000>; |
84 | interrupts = <9 10>; | |
189892f4 BC |
85 | #address-cells = <1>; |
86 | #size-cells = <1>; | |
87 | ranges; | |
88 | ti,hwmods = "l3_main"; | |
89 | ||
7ce93f31 TL |
90 | aes: aes@480c5000 { |
91 | compatible = "ti,omap3-aes"; | |
92 | ti,hwmods = "aes"; | |
93 | reg = <0x480c5000 0x50>; | |
94 | interrupts = <0>; | |
95 | }; | |
96 | ||
657fc11c TK |
97 | prm: prm@48306000 { |
98 | compatible = "ti,omap3-prm"; | |
99 | reg = <0x48306000 0x4000>; | |
100 | ||
101 | prm_clocks: clocks { | |
102 | #address-cells = <1>; | |
103 | #size-cells = <0>; | |
104 | }; | |
105 | ||
106 | prm_clockdomains: clockdomains { | |
107 | }; | |
108 | }; | |
109 | ||
110 | cm: cm@48004000 { | |
111 | compatible = "ti,omap3-cm"; | |
112 | reg = <0x48004000 0x4000>; | |
113 | ||
114 | cm_clocks: clocks { | |
115 | #address-cells = <1>; | |
116 | #size-cells = <0>; | |
117 | }; | |
118 | ||
119 | cm_clockdomains: clockdomains { | |
120 | }; | |
121 | }; | |
122 | ||
123 | scrm: scrm@48002000 { | |
124 | compatible = "ti,omap3-scrm"; | |
125 | reg = <0x48002000 0x2000>; | |
126 | ||
127 | scrm_clocks: clocks { | |
128 | #address-cells = <1>; | |
129 | #size-cells = <0>; | |
130 | }; | |
131 | ||
132 | scrm_clockdomains: clockdomains { | |
133 | }; | |
134 | }; | |
135 | ||
510c0ffd JH |
136 | counter32k: counter@48320000 { |
137 | compatible = "ti,omap-counter32k"; | |
138 | reg = <0x48320000 0x20>; | |
139 | ti,hwmods = "counter_32k"; | |
140 | }; | |
141 | ||
d65c5423 BC |
142 | intc: interrupt-controller@48200000 { |
143 | compatible = "ti,omap2-intc"; | |
189892f4 BC |
144 | interrupt-controller; |
145 | #interrupt-cells = <1>; | |
d65c5423 BC |
146 | ti,intc-size = <96>; |
147 | reg = <0x48200000 0x1000>; | |
189892f4 | 148 | }; |
cf3c79de | 149 | |
2c2dc545 JH |
150 | sdma: dma-controller@48056000 { |
151 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; | |
152 | reg = <0x48056000 0x1000>; | |
153 | interrupts = <12>, | |
154 | <13>, | |
155 | <14>, | |
156 | <15>; | |
157 | #dma-cells = <1>; | |
158 | #dma-channels = <32>; | |
159 | #dma-requests = <96>; | |
160 | }; | |
161 | ||
679e3310 TL |
162 | omap3_pmx_core: pinmux@48002030 { |
163 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
3d495383 | 164 | reg = <0x48002030 0x0238>; |
679e3310 TL |
165 | #address-cells = <1>; |
166 | #size-cells = <0>; | |
30a69ef7 TL |
167 | #interrupt-cells = <1>; |
168 | interrupt-controller; | |
679e3310 | 169 | pinctrl-single,register-width = <16>; |
d623a0e1 | 170 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
171 | }; |
172 | ||
b7317777 | 173 | omap3_pmx_wkup: pinmux@48002a00 { |
679e3310 | 174 | compatible = "ti,omap3-padconf", "pinctrl-single"; |
161e89a6 | 175 | reg = <0x48002a00 0x5c>; |
679e3310 TL |
176 | #address-cells = <1>; |
177 | #size-cells = <0>; | |
30a69ef7 TL |
178 | #interrupt-cells = <1>; |
179 | interrupt-controller; | |
679e3310 | 180 | pinctrl-single,register-width = <16>; |
d623a0e1 | 181 | pinctrl-single,function-mask = <0xff1f>; |
679e3310 TL |
182 | }; |
183 | ||
cd042fe5 B |
184 | omap3_scm_general: tisyscon@48002270 { |
185 | compatible = "syscon"; | |
186 | reg = <0x48002270 0x2f0>; | |
187 | }; | |
188 | ||
189 | pbias_regulator: pbias_regulator { | |
190 | compatible = "ti,pbias-omap"; | |
191 | reg = <0x2b0 0x4>; | |
192 | syscon = <&omap3_scm_general>; | |
193 | pbias_mmc_reg: pbias_mmc_omap2430 { | |
194 | regulator-name = "pbias_mmc_omap2430"; | |
195 | regulator-min-microvolt = <1800000>; | |
196 | regulator-max-microvolt = <3000000>; | |
197 | }; | |
198 | }; | |
199 | ||
385a64bb BC |
200 | gpio1: gpio@48310000 { |
201 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
202 | reg = <0x48310000 0x200>; |
203 | interrupts = <29>; | |
385a64bb | 204 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 205 | ti,gpio-always-on; |
385a64bb BC |
206 | gpio-controller; |
207 | #gpio-cells = <2>; | |
208 | interrupt-controller; | |
ff5c9059 | 209 | #interrupt-cells = <2>; |
385a64bb BC |
210 | }; |
211 | ||
212 | gpio2: gpio@49050000 { | |
213 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
214 | reg = <0x49050000 0x200>; |
215 | interrupts = <30>; | |
385a64bb BC |
216 | ti,hwmods = "gpio2"; |
217 | gpio-controller; | |
218 | #gpio-cells = <2>; | |
219 | interrupt-controller; | |
ff5c9059 | 220 | #interrupt-cells = <2>; |
385a64bb BC |
221 | }; |
222 | ||
223 | gpio3: gpio@49052000 { | |
224 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
225 | reg = <0x49052000 0x200>; |
226 | interrupts = <31>; | |
385a64bb BC |
227 | ti,hwmods = "gpio3"; |
228 | gpio-controller; | |
229 | #gpio-cells = <2>; | |
230 | interrupt-controller; | |
ff5c9059 | 231 | #interrupt-cells = <2>; |
385a64bb BC |
232 | }; |
233 | ||
234 | gpio4: gpio@49054000 { | |
235 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
236 | reg = <0x49054000 0x200>; |
237 | interrupts = <32>; | |
385a64bb BC |
238 | ti,hwmods = "gpio4"; |
239 | gpio-controller; | |
240 | #gpio-cells = <2>; | |
241 | interrupt-controller; | |
ff5c9059 | 242 | #interrupt-cells = <2>; |
385a64bb BC |
243 | }; |
244 | ||
245 | gpio5: gpio@49056000 { | |
246 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
247 | reg = <0x49056000 0x200>; |
248 | interrupts = <33>; | |
385a64bb BC |
249 | ti,hwmods = "gpio5"; |
250 | gpio-controller; | |
251 | #gpio-cells = <2>; | |
252 | interrupt-controller; | |
ff5c9059 | 253 | #interrupt-cells = <2>; |
385a64bb BC |
254 | }; |
255 | ||
256 | gpio6: gpio@49058000 { | |
257 | compatible = "ti,omap3-gpio"; | |
e299185a JH |
258 | reg = <0x49058000 0x200>; |
259 | interrupts = <34>; | |
385a64bb BC |
260 | ti,hwmods = "gpio6"; |
261 | gpio-controller; | |
262 | #gpio-cells = <2>; | |
263 | interrupt-controller; | |
ff5c9059 | 264 | #interrupt-cells = <2>; |
385a64bb BC |
265 | }; |
266 | ||
19bfb76c | 267 | uart1: serial@4806a000 { |
cf3c79de | 268 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
269 | reg = <0x4806a000 0x2000>; |
270 | interrupts = <72>; | |
271 | dmas = <&sdma 49 &sdma 50>; | |
272 | dma-names = "tx", "rx"; | |
cf3c79de RN |
273 | ti,hwmods = "uart1"; |
274 | clock-frequency = <48000000>; | |
275 | }; | |
276 | ||
19bfb76c | 277 | uart2: serial@4806c000 { |
cf3c79de | 278 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
279 | reg = <0x4806c000 0x400>; |
280 | interrupts = <73>; | |
281 | dmas = <&sdma 51 &sdma 52>; | |
282 | dma-names = "tx", "rx"; | |
cf3c79de RN |
283 | ti,hwmods = "uart2"; |
284 | clock-frequency = <48000000>; | |
285 | }; | |
286 | ||
19bfb76c | 287 | uart3: serial@49020000 { |
cf3c79de | 288 | compatible = "ti,omap3-uart"; |
d7c8f259 TL |
289 | reg = <0x49020000 0x400>; |
290 | interrupts = <74>; | |
291 | dmas = <&sdma 53 &sdma 54>; | |
292 | dma-names = "tx", "rx"; | |
cf3c79de RN |
293 | ti,hwmods = "uart3"; |
294 | clock-frequency = <48000000>; | |
295 | }; | |
296 | ||
ca59a5c1 BC |
297 | i2c1: i2c@48070000 { |
298 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
299 | reg = <0x48070000 0x80>; |
300 | interrupts = <56>; | |
301 | dmas = <&sdma 27 &sdma 28>; | |
302 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
303 | #address-cells = <1>; |
304 | #size-cells = <0>; | |
305 | ti,hwmods = "i2c1"; | |
306 | }; | |
307 | ||
308 | i2c2: i2c@48072000 { | |
309 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
310 | reg = <0x48072000 0x80>; |
311 | interrupts = <57>; | |
312 | dmas = <&sdma 29 &sdma 30>; | |
313 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
314 | #address-cells = <1>; |
315 | #size-cells = <0>; | |
316 | ti,hwmods = "i2c2"; | |
317 | }; | |
318 | ||
319 | i2c3: i2c@48060000 { | |
320 | compatible = "ti,omap3-i2c"; | |
d7c8f259 TL |
321 | reg = <0x48060000 0x80>; |
322 | interrupts = <61>; | |
323 | dmas = <&sdma 25 &sdma 26>; | |
324 | dma-names = "tx", "rx"; | |
ca59a5c1 BC |
325 | #address-cells = <1>; |
326 | #size-cells = <0>; | |
327 | ti,hwmods = "i2c3"; | |
328 | }; | |
fc72d248 | 329 | |
7ce93f31 TL |
330 | mailbox: mailbox@48094000 { |
331 | compatible = "ti,omap3-mailbox"; | |
332 | ti,hwmods = "mailbox"; | |
333 | reg = <0x48094000 0x200>; | |
334 | interrupts = <26>; | |
335 | }; | |
336 | ||
fc72d248 BC |
337 | mcspi1: spi@48098000 { |
338 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
339 | reg = <0x48098000 0x100>; |
340 | interrupts = <65>; | |
fc72d248 BC |
341 | #address-cells = <1>; |
342 | #size-cells = <0>; | |
343 | ti,hwmods = "mcspi1"; | |
344 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
345 | dmas = <&sdma 35>, |
346 | <&sdma 36>, | |
347 | <&sdma 37>, | |
348 | <&sdma 38>, | |
349 | <&sdma 39>, | |
350 | <&sdma 40>, | |
351 | <&sdma 41>, | |
352 | <&sdma 42>; | |
353 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
354 | "tx2", "rx2", "tx3", "rx3"; | |
fc72d248 BC |
355 | }; |
356 | ||
357 | mcspi2: spi@4809a000 { | |
358 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
359 | reg = <0x4809a000 0x100>; |
360 | interrupts = <66>; | |
fc72d248 BC |
361 | #address-cells = <1>; |
362 | #size-cells = <0>; | |
363 | ti,hwmods = "mcspi2"; | |
364 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
365 | dmas = <&sdma 43>, |
366 | <&sdma 44>, | |
367 | <&sdma 45>, | |
368 | <&sdma 46>; | |
369 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
370 | }; |
371 | ||
372 | mcspi3: spi@480b8000 { | |
373 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
374 | reg = <0x480b8000 0x100>; |
375 | interrupts = <91>; | |
fc72d248 BC |
376 | #address-cells = <1>; |
377 | #size-cells = <0>; | |
378 | ti,hwmods = "mcspi3"; | |
379 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
380 | dmas = <&sdma 15>, |
381 | <&sdma 16>, | |
382 | <&sdma 23>, | |
383 | <&sdma 24>; | |
384 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
fc72d248 BC |
385 | }; |
386 | ||
387 | mcspi4: spi@480ba000 { | |
388 | compatible = "ti,omap2-mcspi"; | |
d7c8f259 TL |
389 | reg = <0x480ba000 0x100>; |
390 | interrupts = <48>; | |
fc72d248 BC |
391 | #address-cells = <1>; |
392 | #size-cells = <0>; | |
393 | ti,hwmods = "mcspi4"; | |
394 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
395 | dmas = <&sdma 70>, <&sdma 71>; |
396 | dma-names = "tx0", "rx0"; | |
fc72d248 | 397 | }; |
b3431f5b | 398 | |
d7c8f259 TL |
399 | hdqw1w: 1w@480b2000 { |
400 | compatible = "ti,omap3-1w"; | |
401 | reg = <0x480b2000 0x1000>; | |
402 | interrupts = <58>; | |
403 | ti,hwmods = "hdq1w"; | |
404 | }; | |
405 | ||
b3431f5b RN |
406 | mmc1: mmc@4809c000 { |
407 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
408 | reg = <0x4809c000 0x200>; |
409 | interrupts = <83>; | |
b3431f5b RN |
410 | ti,hwmods = "mmc1"; |
411 | ti,dual-volt; | |
2c2dc545 JH |
412 | dmas = <&sdma 61>, <&sdma 62>; |
413 | dma-names = "tx", "rx"; | |
cd042fe5 | 414 | pbias-supply = <&pbias_mmc_reg>; |
b3431f5b RN |
415 | }; |
416 | ||
417 | mmc2: mmc@480b4000 { | |
418 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
419 | reg = <0x480b4000 0x200>; |
420 | interrupts = <86>; | |
b3431f5b | 421 | ti,hwmods = "mmc2"; |
2c2dc545 JH |
422 | dmas = <&sdma 47>, <&sdma 48>; |
423 | dma-names = "tx", "rx"; | |
b3431f5b RN |
424 | }; |
425 | ||
426 | mmc3: mmc@480ad000 { | |
427 | compatible = "ti,omap3-hsmmc"; | |
d7c8f259 TL |
428 | reg = <0x480ad000 0x200>; |
429 | interrupts = <94>; | |
b3431f5b | 430 | ti,hwmods = "mmc3"; |
2c2dc545 JH |
431 | dmas = <&sdma 77>, <&sdma 78>; |
432 | dma-names = "tx", "rx"; | |
b3431f5b | 433 | }; |
94c30732 | 434 | |
7ce93f31 | 435 | mmu_isp: mmu@480bd400 { |
b7cd9597 | 436 | compatible = "ti,omap2-iommu"; |
7ce93f31 | 437 | reg = <0x480bd400 0x80>; |
b7cd9597 FV |
438 | interrupts = <24>; |
439 | ti,hwmods = "mmu_isp"; | |
440 | ti,#tlb-entries = <8>; | |
7ce93f31 TL |
441 | }; |
442 | ||
40ac051d FV |
443 | mmu_iva: mmu@5d000000 { |
444 | compatible = "ti,omap2-iommu"; | |
445 | reg = <0x5d000000 0x80>; | |
446 | interrupts = <28>; | |
447 | ti,hwmods = "mmu_iva"; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
94c30732 XJ |
451 | wdt2: wdt@48314000 { |
452 | compatible = "ti,omap3-wdt"; | |
d7c8f259 | 453 | reg = <0x48314000 0x80>; |
94c30732 XJ |
454 | ti,hwmods = "wd_timer2"; |
455 | }; | |
0be484bf PU |
456 | |
457 | mcbsp1: mcbsp@48074000 { | |
458 | compatible = "ti,omap3-mcbsp"; | |
459 | reg = <0x48074000 0xff>; | |
460 | reg-names = "mpu"; | |
461 | interrupts = <16>, /* OCP compliant interrupt */ | |
462 | <59>, /* TX interrupt */ | |
463 | <60>; /* RX interrupt */ | |
464 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
465 | ti,buffer-size = <128>; |
466 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
467 | dmas = <&sdma 31>, |
468 | <&sdma 32>; | |
469 | dma-names = "tx", "rx"; | |
726322ce | 470 | status = "disabled"; |
0be484bf PU |
471 | }; |
472 | ||
473 | mcbsp2: mcbsp@49022000 { | |
474 | compatible = "ti,omap3-mcbsp"; | |
475 | reg = <0x49022000 0xff>, | |
476 | <0x49028000 0xff>; | |
477 | reg-names = "mpu", "sidetone"; | |
478 | interrupts = <17>, /* OCP compliant interrupt */ | |
479 | <62>, /* TX interrupt */ | |
480 | <63>, /* RX interrupt */ | |
481 | <4>; /* Sidetone */ | |
482 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 483 | ti,buffer-size = <1280>; |
eef6fcaa | 484 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
4e4ead73 SG |
485 | dmas = <&sdma 33>, |
486 | <&sdma 34>; | |
487 | dma-names = "tx", "rx"; | |
726322ce | 488 | status = "disabled"; |
0be484bf PU |
489 | }; |
490 | ||
491 | mcbsp3: mcbsp@49024000 { | |
492 | compatible = "ti,omap3-mcbsp"; | |
493 | reg = <0x49024000 0xff>, | |
494 | <0x4902a000 0xff>; | |
495 | reg-names = "mpu", "sidetone"; | |
496 | interrupts = <22>, /* OCP compliant interrupt */ | |
497 | <89>, /* TX interrupt */ | |
498 | <90>, /* RX interrupt */ | |
499 | <5>; /* Sidetone */ | |
500 | interrupt-names = "common", "tx", "rx", "sidetone"; | |
0be484bf | 501 | ti,buffer-size = <128>; |
eef6fcaa | 502 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
4e4ead73 SG |
503 | dmas = <&sdma 17>, |
504 | <&sdma 18>; | |
505 | dma-names = "tx", "rx"; | |
726322ce | 506 | status = "disabled"; |
0be484bf PU |
507 | }; |
508 | ||
509 | mcbsp4: mcbsp@49026000 { | |
510 | compatible = "ti,omap3-mcbsp"; | |
511 | reg = <0x49026000 0xff>; | |
512 | reg-names = "mpu"; | |
513 | interrupts = <23>, /* OCP compliant interrupt */ | |
514 | <54>, /* TX interrupt */ | |
515 | <55>; /* RX interrupt */ | |
516 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
517 | ti,buffer-size = <128>; |
518 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
519 | dmas = <&sdma 19>, |
520 | <&sdma 20>; | |
521 | dma-names = "tx", "rx"; | |
726322ce | 522 | status = "disabled"; |
0be484bf PU |
523 | }; |
524 | ||
525 | mcbsp5: mcbsp@48096000 { | |
526 | compatible = "ti,omap3-mcbsp"; | |
527 | reg = <0x48096000 0xff>; | |
528 | reg-names = "mpu"; | |
529 | interrupts = <27>, /* OCP compliant interrupt */ | |
530 | <81>, /* TX interrupt */ | |
531 | <82>; /* RX interrupt */ | |
532 | interrupt-names = "common", "tx", "rx"; | |
0be484bf PU |
533 | ti,buffer-size = <128>; |
534 | ti,hwmods = "mcbsp5"; | |
4e4ead73 SG |
535 | dmas = <&sdma 21>, |
536 | <&sdma 22>; | |
537 | dma-names = "tx", "rx"; | |
726322ce | 538 | status = "disabled"; |
0be484bf | 539 | }; |
fab8ad0b | 540 | |
7ce93f31 TL |
541 | sham: sham@480c3000 { |
542 | compatible = "ti,omap3-sham"; | |
543 | ti,hwmods = "sham"; | |
544 | reg = <0x480c3000 0x64>; | |
545 | interrupts = <49>; | |
546 | }; | |
547 | ||
548 | smartreflex_core: smartreflex@480cb000 { | |
549 | compatible = "ti,omap3-smartreflex-core"; | |
550 | ti,hwmods = "smartreflex_core"; | |
551 | reg = <0x480cb000 0x400>; | |
552 | interrupts = <19>; | |
553 | }; | |
554 | ||
555 | smartreflex_mpu_iva: smartreflex@480c9000 { | |
556 | compatible = "ti,omap3-smartreflex-iva"; | |
557 | ti,hwmods = "smartreflex_mpu_iva"; | |
558 | reg = <0x480c9000 0x400>; | |
559 | interrupts = <18>; | |
560 | }; | |
561 | ||
fab8ad0b | 562 | timer1: timer@48318000 { |
002e1ec5 | 563 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
564 | reg = <0x48318000 0x400>; |
565 | interrupts = <37>; | |
566 | ti,hwmods = "timer1"; | |
567 | ti,timer-alwon; | |
568 | }; | |
569 | ||
570 | timer2: timer@49032000 { | |
002e1ec5 | 571 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
572 | reg = <0x49032000 0x400>; |
573 | interrupts = <38>; | |
574 | ti,hwmods = "timer2"; | |
575 | }; | |
576 | ||
577 | timer3: timer@49034000 { | |
002e1ec5 | 578 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
579 | reg = <0x49034000 0x400>; |
580 | interrupts = <39>; | |
581 | ti,hwmods = "timer3"; | |
582 | }; | |
583 | ||
584 | timer4: timer@49036000 { | |
002e1ec5 | 585 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
586 | reg = <0x49036000 0x400>; |
587 | interrupts = <40>; | |
588 | ti,hwmods = "timer4"; | |
589 | }; | |
590 | ||
591 | timer5: timer@49038000 { | |
002e1ec5 | 592 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
593 | reg = <0x49038000 0x400>; |
594 | interrupts = <41>; | |
595 | ti,hwmods = "timer5"; | |
596 | ti,timer-dsp; | |
597 | }; | |
598 | ||
599 | timer6: timer@4903a000 { | |
002e1ec5 | 600 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
601 | reg = <0x4903a000 0x400>; |
602 | interrupts = <42>; | |
603 | ti,hwmods = "timer6"; | |
604 | ti,timer-dsp; | |
605 | }; | |
606 | ||
607 | timer7: timer@4903c000 { | |
002e1ec5 | 608 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
609 | reg = <0x4903c000 0x400>; |
610 | interrupts = <43>; | |
611 | ti,hwmods = "timer7"; | |
612 | ti,timer-dsp; | |
613 | }; | |
614 | ||
615 | timer8: timer@4903e000 { | |
002e1ec5 | 616 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
617 | reg = <0x4903e000 0x400>; |
618 | interrupts = <44>; | |
619 | ti,hwmods = "timer8"; | |
620 | ti,timer-pwm; | |
621 | ti,timer-dsp; | |
622 | }; | |
623 | ||
624 | timer9: timer@49040000 { | |
002e1ec5 | 625 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
626 | reg = <0x49040000 0x400>; |
627 | interrupts = <45>; | |
628 | ti,hwmods = "timer9"; | |
629 | ti,timer-pwm; | |
630 | }; | |
631 | ||
632 | timer10: timer@48086000 { | |
002e1ec5 | 633 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
634 | reg = <0x48086000 0x400>; |
635 | interrupts = <46>; | |
636 | ti,hwmods = "timer10"; | |
637 | ti,timer-pwm; | |
638 | }; | |
639 | ||
640 | timer11: timer@48088000 { | |
002e1ec5 | 641 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
642 | reg = <0x48088000 0x400>; |
643 | interrupts = <47>; | |
644 | ti,hwmods = "timer11"; | |
645 | ti,timer-pwm; | |
646 | }; | |
647 | ||
648 | timer12: timer@48304000 { | |
002e1ec5 | 649 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
650 | reg = <0x48304000 0x400>; |
651 | interrupts = <95>; | |
652 | ti,hwmods = "timer12"; | |
653 | ti,timer-alwon; | |
654 | ti,timer-secure; | |
655 | }; | |
af3eb366 RQ |
656 | |
657 | usbhstll: usbhstll@48062000 { | |
658 | compatible = "ti,usbhs-tll"; | |
659 | reg = <0x48062000 0x1000>; | |
660 | interrupts = <78>; | |
661 | ti,hwmods = "usb_tll_hs"; | |
662 | }; | |
663 | ||
664 | usbhshost: usbhshost@48064000 { | |
665 | compatible = "ti,usbhs-host"; | |
666 | reg = <0x48064000 0x400>; | |
667 | ti,hwmods = "usb_host_hs"; | |
668 | #address-cells = <1>; | |
669 | #size-cells = <1>; | |
670 | ranges; | |
671 | ||
672 | usbhsohci: ohci@48064400 { | |
a2525e54 | 673 | compatible = "ti,ohci-omap3"; |
af3eb366 RQ |
674 | reg = <0x48064400 0x400>; |
675 | interrupt-parent = <&intc>; | |
676 | interrupts = <76>; | |
677 | }; | |
678 | ||
679 | usbhsehci: ehci@48064800 { | |
a2525e54 | 680 | compatible = "ti,ehci-omap"; |
af3eb366 RQ |
681 | reg = <0x48064800 0x400>; |
682 | interrupt-parent = <&intc>; | |
683 | interrupts = <77>; | |
684 | }; | |
685 | }; | |
686 | ||
6e8489df FV |
687 | gpmc: gpmc@6e000000 { |
688 | compatible = "ti,omap3430-gpmc"; | |
689 | ti,hwmods = "gpmc"; | |
41644e75 | 690 | reg = <0x6e000000 0x02d0>; |
6e8489df FV |
691 | interrupts = <20>; |
692 | gpmc,num-cs = <8>; | |
693 | gpmc,num-waitpins = <4>; | |
694 | #address-cells = <2>; | |
695 | #size-cells = <1>; | |
696 | }; | |
ad871c10 KVA |
697 | |
698 | usb_otg_hs: usb_otg_hs@480ab000 { | |
699 | compatible = "ti,omap3-musb"; | |
700 | reg = <0x480ab000 0x1000>; | |
304e71e0 | 701 | interrupts = <92>, <93>; |
ad871c10 KVA |
702 | interrupt-names = "mc", "dma"; |
703 | ti,hwmods = "usb_otg_hs"; | |
ad871c10 KVA |
704 | multipoint = <1>; |
705 | num-eps = <16>; | |
706 | ram-bits = <12>; | |
707 | }; | |
b8a7e42b TV |
708 | |
709 | dss: dss@48050000 { | |
710 | compatible = "ti,omap3-dss"; | |
711 | reg = <0x48050000 0x200>; | |
712 | status = "disabled"; | |
713 | ti,hwmods = "dss_core"; | |
714 | clocks = <&dss1_alwon_fck>; | |
715 | clock-names = "fck"; | |
716 | #address-cells = <1>; | |
717 | #size-cells = <1>; | |
718 | ranges; | |
719 | ||
720 | dispc@48050400 { | |
721 | compatible = "ti,omap3-dispc"; | |
722 | reg = <0x48050400 0x400>; | |
723 | interrupts = <25>; | |
724 | ti,hwmods = "dss_dispc"; | |
725 | clocks = <&dss1_alwon_fck>; | |
726 | clock-names = "fck"; | |
727 | }; | |
728 | ||
729 | dsi: encoder@4804fc00 { | |
730 | compatible = "ti,omap3-dsi"; | |
731 | reg = <0x4804fc00 0x200>, | |
732 | <0x4804fe00 0x40>, | |
733 | <0x4804ff00 0x20>; | |
734 | reg-names = "proto", "phy", "pll"; | |
735 | interrupts = <25>; | |
736 | status = "disabled"; | |
737 | ti,hwmods = "dss_dsi1"; | |
738 | clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; | |
739 | clock-names = "fck", "sys_clk"; | |
740 | }; | |
741 | ||
742 | rfbi: encoder@48050800 { | |
743 | compatible = "ti,omap3-rfbi"; | |
744 | reg = <0x48050800 0x100>; | |
745 | status = "disabled"; | |
746 | ti,hwmods = "dss_rfbi"; | |
747 | clocks = <&dss1_alwon_fck>, <&dss_ick>; | |
748 | clock-names = "fck", "ick"; | |
749 | }; | |
750 | ||
751 | venc: encoder@48050c00 { | |
752 | compatible = "ti,omap3-venc"; | |
753 | reg = <0x48050c00 0x100>; | |
754 | status = "disabled"; | |
755 | ti,hwmods = "dss_venc"; | |
756 | clocks = <&dss_tv_fck>; | |
757 | clock-names = "fck"; | |
758 | }; | |
759 | }; | |
189892f4 BC |
760 | }; |
761 | }; | |
657fc11c TK |
762 | |
763 | /include/ "omap3xxx-clocks.dtsi" |