projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 642f12b4 TL |
1 | /* |
| 2 | * Device Tree Source for OMAP3 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 98ef7957 | 11 | #include "omap3.dtsi" |
| 642f12b4 TL |
12 | |
| 13 | / { | |
| 14 | aliases { | |
| 15 | serial3 = &uart4; | |
| 16 | }; | |
| 17 | ||
| 3027e267 NM |
18 | cpus { |
| 19 | /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ | |
| 20 | cpu@0 { | |
| 21 | operating-points = < | |
| 22 | /* kHz uV */ | |
| e011cf69 NM |
23 | 300000 1012500 |
| 24 | 600000 1200000 | |
| 25 | 800000 1325000 | |
| 3027e267 NM |
26 | >; |
| 27 | clock-latency = <300000>; /* From legacy driver */ | |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 642f12b4 TL |
31 | ocp { |
| 32 | uart4: serial@49042000 { | |
| 33 | compatible = "ti,omap3-uart"; | |
| d7c8f259 TL |
34 | reg = <0x49042000 0x400>; |
| 35 | interrupts = <80>; | |
| 36 | dmas = <&sdma 81 &sdma 82>; | |
| 37 | dma-names = "tx", "rx"; | |
| 642f12b4 TL |
38 | ti,hwmods = "uart4"; |
| 39 | clock-frequency = <48000000>; | |
| 40 | }; | |
| 3d495383 | 41 | |
| b391d387 AT |
42 | abb_mpu_iva: regulator-abb-mpu { |
| 43 | compatible = "ti,abb-v1"; | |
| 44 | regulator-name = "abb_mpu_iva"; | |
| 45 | #address-cell = <0>; | |
| 46 | #size-cells = <0>; | |
| 47 | reg = <0x483072f0 0x8>, <0x48306818 0x4>; | |
| 48 | reg-names = "base-address", "int-address"; | |
| 49 | ti,tranxdone-status-mask = <0x4000000>; | |
| 50 | clocks = <&sys_ck>; | |
| 51 | ti,settling-time = <30>; | |
| 52 | ti,clock-cycles = <8>; | |
| 53 | ti,abb_info = < | |
| 54 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
| 55 | 1012500 0 0 0 0 0 | |
| 56 | 1200000 0 0 0 0 0 | |
| 57 | 1325000 0 0 0 0 0 | |
| 58 | 1375000 1 0 0 0 0 | |
| 59 | >; | |
| 60 | }; | |
| 61 | ||
| 3d495383 LP |
62 | omap3_pmx_core2: pinmux@480025a0 { |
| 63 | compatible = "ti,omap3-padconf", "pinctrl-single"; | |
| 64 | reg = <0x480025a0 0x5c>; | |
| 65 | #address-cells = <1>; | |
| 66 | #size-cells = <0>; | |
| 67 | #interrupt-cells = <1>; | |
| 68 | interrupt-controller; | |
| 69 | pinctrl-single,register-width = <16>; | |
| 70 | pinctrl-single,function-mask = <0xff1f>; | |
| 71 | }; | |
| 642f12b4 TL |
72 | }; |
| 73 | }; | |
| 657fc11c | 74 | |
| b8a7e42b TV |
75 | /* OMAP3630 needs dss_96m_fck for VENC */ |
| 76 | &venc { | |
| 77 | clocks = <&dss_tv_fck>, <&dss_96m_fck>; | |
| 78 | clock-names = "fck", "tv_dac_clk"; | |
| 79 | }; | |
| 80 | ||
| 782e25a4 SR |
81 | &ssi { |
| 82 | status = "ok"; | |
| 83 | ||
| 84 | clocks = <&ssi_ssr_fck>, | |
| 85 | <&ssi_sst_fck>, | |
| 86 | <&ssi_ick>; | |
| 87 | clock-names = "ssi_ssr_fck", | |
| 88 | "ssi_sst_fck", | |
| 89 | "ssi_ick"; | |
| 90 | }; | |
| 91 | ||
| 657fc11c TK |
92 | /include/ "omap34xx-omap36xx-clocks.dtsi" |
| 93 | /include/ "omap36xx-omap3430es2plus-clocks.dtsi" | |
| d30492ad | 94 | /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
| 64a900ff | 95 | /include/ "omap36xx-clocks.dtsi" |