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MAINTAINERS: Add phy-miphy28lp.c and phy-miphy365x.c to ARCH/STI architecture
[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi
CommitLineData
d9fda07a
BC		 1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
6d624eab 9#include <dt-bindings/gpio/gpio.h>
8fea7d5a 10#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 11#include <dt-bindings/pinctrl/omap.h>
d9fda07a 12
98ef7957 13#include "skeleton.dtsi"
d9fda07a
BC		 14
15/ {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
20b80942
NM		 20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
cf3c79de
RN		 24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
d9fda07a
BC		 28 };
29
476b679a 30 cpus {
eeb25fd5
LP		 31 #address-cells = <1>;
32 #size-cells = <0>;
33
476b679a
BC		 34 cpu@0 {
35 compatible = "arm,cortex-a9";
eeb25fd5 36 device_type = "cpu";
926fd45b 37 next-level-cache = <&L2>;
eeb25fd5 38 reg = <0x0>;
8d766fa2
NM		 39
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
476b679a
BC		 44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
eeb25fd5 47 device_type = "cpu";
926fd45b 48 next-level-cache = <&L2>;
eeb25fd5 49 reg = <0x1>;
476b679a
BC		 50 };
51 };
52
5635121e
BC		 53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>;
59 };
60
926fd45b
SS		 61 L2: l2-cache-controller@48242000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x48242000 0x1000>;
64 cache-unified;
65 cache-level = <2>;
66 };
67
75d71d46 68 local-timer@48240600 {
eed0de27 69 compatible = "arm,cortex-a9-twd-timer";
23c47378 70 clocks = <&mpu_periphclk>;
eed0de27 71 reg = <0x48240600 0x20>;
8fea7d5a 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
eed0de27
SS		 73 };
74
d9fda07a 75 /*
5c5be9db 76 * The soc node represents the soc top level view. It is used for IPs
d9fda07a
BC		 77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
476b679a
BC		 81 mpu {
82 compatible = "ti,omap4-mpu";
83 ti,hwmods = "mpu";
1306c08a 84 sram = <&ocmcram>;
476b679a
BC		 85 };
86
87 dsp {
88 compatible = "ti,omap3-c64";
89 ti,hwmods = "dsp";
90 };
91
92 iva {
93 compatible = "ti,ivahd";
94 ti,hwmods = "iva";
95 };
d9fda07a
BC		 96 };
97
98 /*
99 * XXX: Use a flat representation of the OMAP4 interconnect.
100 * The real OMAP interconnect network is quite complex.
b7ab524b 101 * Since it will not bring real advantage to represent that in DT for
d9fda07a
BC		 102 * the moment, just use a fake OCP bus entry to represent the whole bus
103 * hierarchy.
104 */
105 ocp {
ad8dfac6 106 compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a
BC		 107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
ad8dfac6 110 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 111 reg = <0x44000000 0x1000>,
112 <0x44800000 0x2000>,
113 <0x45000000 0x1000>;
8fea7d5a
FV		 114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
d9fda07a 116
2488ff6c
TK		 117 cm1: cm1@4a004000 {
118 compatible = "ti,omap4-cm1";
119 reg = <0x4a004000 0x2000>;
120
121 cm1_clocks: clocks {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
125
126 cm1_clockdomains: clockdomains {
127 };
128 };
129
130 prm: prm@4a306000 {
131 compatible = "ti,omap4-prm";
132 reg = <0x4a306000 0x3000>;
5081ce62 133 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2488ff6c
TK		 134
135 prm_clocks: clocks {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 };
139
140 prm_clockdomains: clockdomains {
141 };
142 };
143
144 cm2: cm2@4a008000 {
145 compatible = "ti,omap4-cm2";
146 reg = <0x4a008000 0x3000>;
147
148 cm2_clocks: clocks {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 cm2_clockdomains: clockdomains {
154 };
155 };
156
157 scrm: scrm@4a30a000 {
158 compatible = "ti,omap4-scrm";
159 reg = <0x4a30a000 0x2000>;
160
161 scrm_clocks: clocks {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 };
165
166 scrm_clockdomains: clockdomains {
167 };
168 };
169
510c0ffd
JH		 170 counter32k: counter@4a304000 {
171 compatible = "ti,omap-counter32k";
172 reg = <0x4a304000 0x20>;
173 ti,hwmods = "counter_32k";
174 };
175
679e3310
TL		 176 omap4_pmx_core: pinmux@4a100040 {
177 compatible = "ti,omap4-padconf", "pinctrl-single";
178 reg = <0x4a100040 0x0196>;
179 #address-cells = <1>;
180 #size-cells = <0>;
30a69ef7
TL		 181 #interrupt-cells = <1>;
182 interrupt-controller;
679e3310
TL		 183 pinctrl-single,register-width = <16>;
184 pinctrl-single,function-mask = <0x7fff>;
185 };
186 omap4_pmx_wkup: pinmux@4a31e040 {
187 compatible = "ti,omap4-padconf", "pinctrl-single";
188 reg = <0x4a31e040 0x0038>;
189 #address-cells = <1>;
190 #size-cells = <0>;
30a69ef7
TL		 191 #interrupt-cells = <1>;
192 interrupt-controller;
679e3310
TL		 193 pinctrl-single,register-width = <16>;
194 pinctrl-single,function-mask = <0x7fff>;
195 };
196
cd042fe5
B		 197 omap4_padconf_global: tisyscon@4a1005a0 {
198 compatible = "syscon";
199 reg = <0x4a1005a0 0x170>;
200 };
201
202 pbias_regulator: pbias_regulator {
203 compatible = "ti,pbias-omap";
204 reg = <0x60 0x4>;
205 syscon = <&omap4_padconf_global>;
206 pbias_mmc_reg: pbias_mmc_omap4 {
207 regulator-name = "pbias_mmc_omap4";
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <3000000>;
210 };
211 };
212
8b9a2810
RN		 213 ocmcram: ocmcram@40304000 {
214 compatible = "mmio-sram";
215 reg = <0x40304000 0xa000>; /* 40k */
216 };
217
2c2dc545
JH		 218 sdma: dma-controller@4a056000 {
219 compatible = "ti,omap4430-sdma";
220 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 225 #dma-cells = <1>;
226 #dma-channels = <32>;
227 #dma-requests = <127>;
228 };
229
e3e5a92d
BC		 230 gpio1: gpio@4a310000 {
231 compatible = "ti,omap4-gpio";
48420dbc 232 reg = <0x4a310000 0x200>;
8fea7d5a 233 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d 234 ti,hwmods = "gpio1";
e4b9b9f3 235 ti,gpio-always-on;
e3e5a92d
BC		 236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
ff5c9059 239 #interrupt-cells = <2>;
e3e5a92d
BC		 240 };
241
242 gpio2: gpio@48055000 {
243 compatible = "ti,omap4-gpio";
48420dbc 244 reg = <0x48055000 0x200>;
8fea7d5a 245 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 246 ti,hwmods = "gpio2";
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
ff5c9059 250 #interrupt-cells = <2>;
e3e5a92d
BC		 251 };
252
253 gpio3: gpio@48057000 {
254 compatible = "ti,omap4-gpio";
48420dbc 255 reg = <0x48057000 0x200>;
8fea7d5a 256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 257 ti,hwmods = "gpio3";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
ff5c9059 261 #interrupt-cells = <2>;
e3e5a92d
BC		 262 };
263
264 gpio4: gpio@48059000 {
265 compatible = "ti,omap4-gpio";
48420dbc 266 reg = <0x48059000 0x200>;
8fea7d5a 267 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 268 ti,hwmods = "gpio4";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
ff5c9059 272 #interrupt-cells = <2>;
e3e5a92d
BC		 273 };
274
275 gpio5: gpio@4805b000 {
276 compatible = "ti,omap4-gpio";
48420dbc 277 reg = <0x4805b000 0x200>;
8fea7d5a 278 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 279 ti,hwmods = "gpio5";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
ff5c9059 283 #interrupt-cells = <2>;
e3e5a92d
BC		 284 };
285
286 gpio6: gpio@4805d000 {
287 compatible = "ti,omap4-gpio";
48420dbc 288 reg = <0x4805d000 0x200>;
8fea7d5a 289 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 290 ti,hwmods = "gpio6";
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
ff5c9059 294 #interrupt-cells = <2>;
e3e5a92d 295 };
cf3c79de 296
1c7dbb55
JH		 297 gpmc: gpmc@50000000 {
298 compatible = "ti,omap4430-gpmc";
299 reg = <0x50000000 0x1000>;
300 #address-cells = <2>;
301 #size-cells = <1>;
8fea7d5a 302 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 303 gpmc,num-cs = <8>;
304 gpmc,num-waitpins = <4>;
305 ti,hwmods = "gpmc";
f12ecbe2 306 ti,no-idle-on-init;
7b8b6af1
FV		 307 clocks = <&l3_div_ck>;
308 clock-names = "fck";
1c7dbb55
JH		 309 };
310
19bfb76c 311 uart1: serial@4806a000 {
cf3c79de 312 compatible = "ti,omap4-uart";
48420dbc 313 reg = <0x4806a000 0x100>;
8fea7d5a 314 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 315 ti,hwmods = "uart1";
316 clock-frequency = <48000000>;
317 };
318
19bfb76c 319 uart2: serial@4806c000 {
cf3c79de 320 compatible = "ti,omap4-uart";
48420dbc 321 reg = <0x4806c000 0x100>;
31f0820a 322 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 323 ti,hwmods = "uart2";
324 clock-frequency = <48000000>;
325 };
326
19bfb76c 327 uart3: serial@48020000 {
cf3c79de 328 compatible = "ti,omap4-uart";
48420dbc 329 reg = <0x48020000 0x100>;
31f0820a 330 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 331 ti,hwmods = "uart3";
332 clock-frequency = <48000000>;
333 };
334
19bfb76c 335 uart4: serial@4806e000 {
cf3c79de 336 compatible = "ti,omap4-uart";
48420dbc 337 reg = <0x4806e000 0x100>;
31f0820a 338 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 339 ti,hwmods = "uart4";
340 clock-frequency = <48000000>;
341 };
58e778f9 342
04c7d924
SA		 343 hwspinlock: spinlock@4a0f6000 {
344 compatible = "ti,omap4-hwspinlock";
345 reg = <0x4a0f6000 0x1000>;
346 ti,hwmods = "spinlock";
34054213 347 #hwlock-cells = <1>;
04c7d924
SA		 348 };
349
58e778f9
BC		 350 i2c1: i2c@48070000 {
351 compatible = "ti,omap4-i2c";
48420dbc 352 reg = <0x48070000 0x100>;
8fea7d5a 353 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 354 #address-cells = <1>;
355 #size-cells = <0>;
356 ti,hwmods = "i2c1";
357 };
358
359 i2c2: i2c@48072000 {
360 compatible = "ti,omap4-i2c";
48420dbc 361 reg = <0x48072000 0x100>;
8fea7d5a 362 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 363 #address-cells = <1>;
364 #size-cells = <0>;
365 ti,hwmods = "i2c2";
366 };
367
368 i2c3: i2c@48060000 {
369 compatible = "ti,omap4-i2c";
48420dbc 370 reg = <0x48060000 0x100>;
8fea7d5a 371 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 372 #address-cells = <1>;
373 #size-cells = <0>;
374 ti,hwmods = "i2c3";
375 };
376
377 i2c4: i2c@48350000 {
378 compatible = "ti,omap4-i2c";
48420dbc 379 reg = <0x48350000 0x100>;
8fea7d5a 380 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 381 #address-cells = <1>;
382 #size-cells = <0>;
383 ti,hwmods = "i2c4";
384 };
efcf1e50
BC		 385
386 mcspi1: spi@48098000 {
387 compatible = "ti,omap4-mcspi";
48420dbc 388 reg = <0x48098000 0x200>;
8fea7d5a 389 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 390 #address-cells = <1>;
391 #size-cells = <0>;
392 ti,hwmods = "mcspi1";
393 ti,spi-num-cs = <4>;
2c2dc545
JH		 394 dmas = <&sdma 35>,
395 <&sdma 36>,
396 <&sdma 37>,
397 <&sdma 38>,
398 <&sdma 39>,
399 <&sdma 40>,
400 <&sdma 41>,
401 <&sdma 42>;
402 dma-names = "tx0", "rx0", "tx1", "rx1",
403 "tx2", "rx2", "tx3", "rx3";
efcf1e50
BC		 404 };
405
406 mcspi2: spi@4809a000 {
407 compatible = "ti,omap4-mcspi";
48420dbc 408 reg = <0x4809a000 0x200>;
8fea7d5a 409 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 410 #address-cells = <1>;
411 #size-cells = <0>;
412 ti,hwmods = "mcspi2";
413 ti,spi-num-cs = <2>;
2c2dc545
JH		 414 dmas = <&sdma 43>,
415 <&sdma 44>,
416 <&sdma 45>,
417 <&sdma 46>;
418 dma-names = "tx0", "rx0", "tx1", "rx1";
efcf1e50
BC		 419 };
420
421 mcspi3: spi@480b8000 {
422 compatible = "ti,omap4-mcspi";
48420dbc 423 reg = <0x480b8000 0x200>;
8fea7d5a 424 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 425 #address-cells = <1>;
426 #size-cells = <0>;
427 ti,hwmods = "mcspi3";
428 ti,spi-num-cs = <2>;
2c2dc545
JH		 429 dmas = <&sdma 15>, <&sdma 16>;
430 dma-names = "tx0", "rx0";
efcf1e50
BC		 431 };
432
433 mcspi4: spi@480ba000 {
434 compatible = "ti,omap4-mcspi";
48420dbc 435 reg = <0x480ba000 0x200>;
8fea7d5a 436 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 437 #address-cells = <1>;
438 #size-cells = <0>;
439 ti,hwmods = "mcspi4";
440 ti,spi-num-cs = <1>;
2c2dc545
JH		 441 dmas = <&sdma 70>, <&sdma 71>;
442 dma-names = "tx0", "rx0";
efcf1e50 443 };
74981768
RN		 444
445 mmc1: mmc@4809c000 {
446 compatible = "ti,omap4-hsmmc";
48420dbc 447 reg = <0x4809c000 0x400>;
8fea7d5a 448 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 449 ti,hwmods = "mmc1";
450 ti,dual-volt;
451 ti,needs-special-reset;
2c2dc545
JH		 452 dmas = <&sdma 61>, <&sdma 62>;
453 dma-names = "tx", "rx";
cd042fe5 454 pbias-supply = <&pbias_mmc_reg>;
74981768
RN		 455 };
456
457 mmc2: mmc@480b4000 {
458 compatible = "ti,omap4-hsmmc";
48420dbc 459 reg = <0x480b4000 0x400>;
8fea7d5a 460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 461 ti,hwmods = "mmc2";
462 ti,needs-special-reset;
2c2dc545
JH		 463 dmas = <&sdma 47>, <&sdma 48>;
464 dma-names = "tx", "rx";
74981768
RN		 465 };
466
467 mmc3: mmc@480ad000 {
468 compatible = "ti,omap4-hsmmc";
48420dbc 469 reg = <0x480ad000 0x400>;
8fea7d5a 470 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 471 ti,hwmods = "mmc3";
472 ti,needs-special-reset;
2c2dc545
JH		 473 dmas = <&sdma 77>, <&sdma 78>;
474 dma-names = "tx", "rx";
74981768
RN		 475 };
476
477 mmc4: mmc@480d1000 {
478 compatible = "ti,omap4-hsmmc";
48420dbc 479 reg = <0x480d1000 0x400>;
8fea7d5a 480 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 481 ti,hwmods = "mmc4";
482 ti,needs-special-reset;
2c2dc545
JH		 483 dmas = <&sdma 57>, <&sdma 58>;
484 dma-names = "tx", "rx";
74981768
RN		 485 };
486
487 mmc5: mmc@480d5000 {
488 compatible = "ti,omap4-hsmmc";
48420dbc 489 reg = <0x480d5000 0x400>;
8fea7d5a 490 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 491 ti,hwmods = "mmc5";
492 ti,needs-special-reset;
2c2dc545
JH		 493 dmas = <&sdma 59>, <&sdma 60>;
494 dma-names = "tx", "rx";
74981768 495 };
94c30732 496
21bd85a1
FV		 497 mmu_dsp: mmu@4a066000 {
498 compatible = "ti,omap4-iommu";
499 reg = <0x4a066000 0x100>;
500 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
501 ti,hwmods = "mmu_dsp";
502 };
503
504 mmu_ipu: mmu@55082000 {
505 compatible = "ti,omap4-iommu";
506 reg = <0x55082000 0x100>;
507 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "mmu_ipu";
509 ti,iommu-bus-err-back;
510 };
511
94c30732
XJ		 512 wdt2: wdt@4a314000 {
513 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
48420dbc 514 reg = <0x4a314000 0x80>;
8fea7d5a 515 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
94c30732
XJ		 516 ti,hwmods = "wd_timer2";
517 };
4f4b5c74
PU		 518
519 mcpdm: mcpdm@40132000 {
520 compatible = "ti,omap4-mcpdm";
521 reg = <0x40132000 0x7f>, /* MPU private access */
522 <0x49032000 0x7f>; /* L3 Interconnect */
63467cf2 523 reg-names = "mpu", "dma";
8fea7d5a 524 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
4f4b5c74 525 ti,hwmods = "mcpdm";
4e4ead73
SG		 526 dmas = <&sdma 65>,
527 <&sdma 66>;
528 dma-names = "up_link", "dn_link";
7adb0933 529 status = "disabled";
4f4b5c74 530 };
a4c38319
PU		 531
532 dmic: dmic@4012e000 {
533 compatible = "ti,omap4-dmic";
534 reg = <0x4012e000 0x7f>, /* MPU private access */
535 <0x4902e000 0x7f>; /* L3 Interconnect */
63467cf2 536 reg-names = "mpu", "dma";
8fea7d5a 537 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
a4c38319 538 ti,hwmods = "dmic";
4e4ead73
SG		 539 dmas = <&sdma 67>;
540 dma-names = "up_link";
7adb0933 541 status = "disabled";
a4c38319 542 };
61bc3544 543
2995a100
PU		 544 mcbsp1: mcbsp@40122000 {
545 compatible = "ti,omap4-mcbsp";
546 reg = <0x40122000 0xff>, /* MPU private access */
547 <0x49022000 0xff>; /* L3 Interconnect */
548 reg-names = "mpu", "dma";
8fea7d5a 549 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2995a100 550 interrupt-names = "common";
2995a100
PU		 551 ti,buffer-size = <128>;
552 ti,hwmods = "mcbsp1";
4e4ead73
SG		 553 dmas = <&sdma 33>,
554 <&sdma 34>;
555 dma-names = "tx", "rx";
7adb0933 556 status = "disabled";
2995a100
PU		 557 };
558
559 mcbsp2: mcbsp@40124000 {
560 compatible = "ti,omap4-mcbsp";
561 reg = <0x40124000 0xff>, /* MPU private access */
562 <0x49024000 0xff>; /* L3 Interconnect */
563 reg-names = "mpu", "dma";
8fea7d5a 564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
2995a100 565 interrupt-names = "common";
2995a100
PU		 566 ti,buffer-size = <128>;
567 ti,hwmods = "mcbsp2";
4e4ead73
SG		 568 dmas = <&sdma 17>,
569 <&sdma 18>;
570 dma-names = "tx", "rx";
7adb0933 571 status = "disabled";
2995a100
PU		 572 };
573
574 mcbsp3: mcbsp@40126000 {
575 compatible = "ti,omap4-mcbsp";
576 reg = <0x40126000 0xff>, /* MPU private access */
577 <0x49026000 0xff>; /* L3 Interconnect */
578 reg-names = "mpu", "dma";
8fea7d5a 579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
2995a100 580 interrupt-names = "common";
2995a100
PU		 581 ti,buffer-size = <128>;
582 ti,hwmods = "mcbsp3";
4e4ead73
SG		 583 dmas = <&sdma 19>,
584 <&sdma 20>;
585 dma-names = "tx", "rx";
7adb0933 586 status = "disabled";
2995a100
PU		 587 };
588
589 mcbsp4: mcbsp@48096000 {
590 compatible = "ti,omap4-mcbsp";
591 reg = <0x48096000 0xff>; /* L4 Interconnect */
592 reg-names = "mpu";
8fea7d5a 593 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2995a100 594 interrupt-names = "common";
2995a100
PU		 595 ti,buffer-size = <128>;
596 ti,hwmods = "mcbsp4";
4e4ead73
SG		 597 dmas = <&sdma 31>,
598 <&sdma 32>;
599 dma-names = "tx", "rx";
7adb0933 600 status = "disabled";
2995a100
PU		 601 };
602
61bc3544
SP		 603 keypad: keypad@4a31c000 {
604 compatible = "ti,omap4-keypad";
48420dbc 605 reg = <0x4a31c000 0x80>;
8fea7d5a 606 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
48420dbc 607 reg-names = "mpu";
61bc3544
SP		 608 ti,hwmods = "kbd";
609 };
11c27069 610
1a5fe3ca
AT		 611 dmm@4e000000 {
612 compatible = "ti,omap4-dmm";
613 reg = <0x4e000000 0x800>;
614 interrupts = <0 113 0x4>;
615 ti,hwmods = "dmm";
616 };
617
11c27069
A		 618 emif1: emif@4c000000 {
619 compatible = "ti,emif-4d";
48420dbc 620 reg = <0x4c000000 0x100>;
8fea7d5a 621 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
11c27069 622 ti,hwmods = "emif1";
f12ecbe2 623 ti,no-idle-on-init;
11c27069
A		 624 phy-type = <1>;
625 hw-caps-read-idle-ctrl;
626 hw-caps-ll-interface;
627 hw-caps-temp-alert;
628 };
629
630 emif2: emif@4d000000 {
631 compatible = "ti,emif-4d";
48420dbc 632 reg = <0x4d000000 0x100>;
8fea7d5a 633 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
11c27069 634 ti,hwmods = "emif2";
f12ecbe2 635 ti,no-idle-on-init;
11c27069
A		 636 phy-type = <1>;
637 hw-caps-read-idle-ctrl;
638 hw-caps-ll-interface;
639 hw-caps-temp-alert;
640 };
8f446a7a 641
3ce0a99c 642 ocp2scp@4a0ad000 {
59bafcf6 643 compatible = "ti,omap-ocp2scp";
3ce0a99c 644 reg = <0x4a0ad000 0x1f>;
59bafcf6
KVA		 645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges;
648 ti,hwmods = "ocp2scp_usb_phy";
cf0d869e
KVA		 649 usb2_phy: usb2phy@4a0ad080 {
650 compatible = "ti,omap-usb2";
651 reg = <0x4a0ad080 0x58>;
470019a4 652 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 653 clocks = <&usb_phy_cm_clk32k>;
654 clock-names = "wkupclk";
975d963e 655 #phy-cells = <0>;
cf0d869e 656 };
59bafcf6 657 };
fab8ad0b 658
8ebc30dd
SA		 659 mailbox: mailbox@4a0f4000 {
660 compatible = "ti,omap4-mailbox";
661 reg = <0x4a0f4000 0x200>;
662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox";
24df0453 664 #mbox-cells = <1>;
8ebc30dd
SA		 665 ti,mbox-num-users = <3>;
666 ti,mbox-num-fifos = <8>;
d27704d1
SA		 667 mbox_ipu: mbox_ipu {
668 ti,mbox-tx = <0 0 0>;
669 ti,mbox-rx = <1 0 0>;
670 };
671 mbox_dsp: mbox_dsp {
672 ti,mbox-tx = <3 0 0>;
673 ti,mbox-rx = <2 0 0>;
674 };
8ebc30dd
SA		 675 };
676
fab8ad0b 677 timer1: timer@4a318000 {
002e1ec5 678 compatible = "ti,omap3430-timer";
fab8ad0b 679 reg = <0x4a318000 0x80>;
8fea7d5a 680 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 681 ti,hwmods = "timer1";
682 ti,timer-alwon;
683 };
684
685 timer2: timer@48032000 {
002e1ec5 686 compatible = "ti,omap3430-timer";
fab8ad0b 687 reg = <0x48032000 0x80>;
8fea7d5a 688 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 689 ti,hwmods = "timer2";
690 };
691
692 timer3: timer@48034000 {
002e1ec5 693 compatible = "ti,omap4430-timer";
fab8ad0b 694 reg = <0x48034000 0x80>;
8fea7d5a 695 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 696 ti,hwmods = "timer3";
697 };
698
699 timer4: timer@48036000 {
002e1ec5 700 compatible = "ti,omap4430-timer";
fab8ad0b 701 reg = <0x48036000 0x80>;
8fea7d5a 702 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 703 ti,hwmods = "timer4";
704 };
705
d03a93bb 706 timer5: timer@40138000 {
002e1ec5 707 compatible = "ti,omap4430-timer";
d03a93bb
JH		 708 reg = <0x40138000 0x80>,
709 <0x49038000 0x80>;
8fea7d5a 710 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 711 ti,hwmods = "timer5";
712 ti,timer-dsp;
713 };
714
d03a93bb 715 timer6: timer@4013a000 {
002e1ec5 716 compatible = "ti,omap4430-timer";
d03a93bb
JH		 717 reg = <0x4013a000 0x80>,
718 <0x4903a000 0x80>;
8fea7d5a 719 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 720 ti,hwmods = "timer6";
721 ti,timer-dsp;
722 };
723
d03a93bb 724 timer7: timer@4013c000 {
002e1ec5 725 compatible = "ti,omap4430-timer";
d03a93bb
JH		 726 reg = <0x4013c000 0x80>,
727 <0x4903c000 0x80>;
8fea7d5a 728 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 729 ti,hwmods = "timer7";
730 ti,timer-dsp;
731 };
732
d03a93bb 733 timer8: timer@4013e000 {
002e1ec5 734 compatible = "ti,omap4430-timer";
d03a93bb
JH		 735 reg = <0x4013e000 0x80>,
736 <0x4903e000 0x80>;
8fea7d5a 737 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 738 ti,hwmods = "timer8";
739 ti,timer-pwm;
740 ti,timer-dsp;
741 };
742
743 timer9: timer@4803e000 {
002e1ec5 744 compatible = "ti,omap4430-timer";
fab8ad0b 745 reg = <0x4803e000 0x80>;
8fea7d5a 746 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 747 ti,hwmods = "timer9";
748 ti,timer-pwm;
749 };
750
751 timer10: timer@48086000 {
002e1ec5 752 compatible = "ti,omap3430-timer";
fab8ad0b 753 reg = <0x48086000 0x80>;
8fea7d5a 754 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 755 ti,hwmods = "timer10";
756 ti,timer-pwm;
757 };
758
759 timer11: timer@48088000 {
002e1ec5 760 compatible = "ti,omap4430-timer";
fab8ad0b 761 reg = <0x48088000 0x80>;
8fea7d5a 762 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 763 ti,hwmods = "timer11";
764 ti,timer-pwm;
765 };
f17c8994
RQ		 766
767 usbhstll: usbhstll@4a062000 {
768 compatible = "ti,usbhs-tll";
769 reg = <0x4a062000 0x1000>;
8fea7d5a 770 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 771 ti,hwmods = "usb_tll_hs";
772 };
773
774 usbhshost: usbhshost@4a064000 {
775 compatible = "ti,usbhs-host";
776 reg = <0x4a064000 0x800>;
777 ti,hwmods = "usb_host_hs";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 ranges;
051fc06d
RQ		 781 clocks = <&init_60m_fclk>,
782 <&xclk60mhsp1_ck>,
783 <&xclk60mhsp2_ck>;
784 clock-names = "refclk_60m_int",
785 "refclk_60m_ext_p1",
786 "refclk_60m_ext_p2";
f17c8994
RQ		 787
788 usbhsohci: ohci@4a064800 {
a2525e54 789 compatible = "ti,ohci-omap3";
f17c8994
RQ		 790 reg = <0x4a064800 0x400>;
791 interrupt-parent = <&gic>;
8fea7d5a 792 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 793 };
794
795 usbhsehci: ehci@4a064c00 {
a2525e54 796 compatible = "ti,ehci-omap";
f17c8994
RQ		 797 reg = <0x4a064c00 0x400>;
798 interrupt-parent = <&gic>;
8fea7d5a 799 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 800 };
801 };
840e5fd8 802
470019a4
RQ		 803 omap_control_usb2phy: control-phy@4a002300 {
804 compatible = "ti,control-phy-usb2";
805 reg = <0x4a002300 0x4>;
806 reg-names = "power";
807 };
808
809 omap_control_usbotg: control-phy@4a00233c {
810 compatible = "ti,control-phy-otghs";
811 reg = <0x4a00233c 0x4>;
812 reg-names = "otghs_control";
840e5fd8 813 };
ad871c10
KVA		 814
815 usb_otg_hs: usb_otg_hs@4a0ab000 {
816 compatible = "ti,omap4-musb";
817 reg = <0x4a0ab000 0x7ff>;
8fea7d5a 818 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
ad871c10
KVA		 819 interrupt-names = "mc", "dma";
820 ti,hwmods = "usb_otg_hs";
821 usb-phy = <&usb2_phy>;
975d963e
KVA		 822 phys = <&usb2_phy>;
823 phy-names = "usb2-phy";
ad871c10
KVA		 824 multipoint = <1>;
825 num-eps = <16>;
826 ram-bits = <12>;
470019a4 827 ctrl-module = <&omap_control_usbotg>;
ad871c10 828 };
dd6317df
JF		 829
830 aes: aes@4b501000 {
831 compatible = "ti,omap4-aes";
832 ti,hwmods = "aes";
833 reg = <0x4b501000 0xa0>;
834 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
835 dmas = <&sdma 111>, <&sdma 110>;
836 dma-names = "tx", "rx";
837 };
806e9431
JF		 838
839 des: des@480a5000 {
840 compatible = "ti,omap4-des";
841 ti,hwmods = "des";
842 reg = <0x480a5000 0xa0>;
843 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
844 dmas = <&sdma 117>, <&sdma 116>;
845 dma-names = "tx", "rx";
846 };
e12c7737
AT		 847
848 abb_mpu: regulator-abb-mpu {
849 compatible = "ti,abb-v2";
850 regulator-name = "abb_mpu";
851 #address-cells = <0>;
852 #size-cells = <0>;
853 ti,tranxdone-status-mask = <0x80>;
854 clocks = <&sys_clkin_ck>;
855 ti,settling-time = <50>;
856 ti,clock-cycles = <16>;
857
858 status = "disabled";
859 };
860
861 abb_iva: regulator-abb-iva {
862 compatible = "ti,abb-v2";
863 regulator-name = "abb_iva";
864 #address-cells = <0>;
865 #size-cells = <0>;
866 ti,tranxdone-status-mask = <0x80000000>;
867 clocks = <&sys_clkin_ck>;
868 ti,settling-time = <50>;
869 ti,clock-cycles = <16>;
870
871 status = "disabled";
872 };
cfe86fcf
TV		 873
874 dss: dss@58000000 {
875 compatible = "ti,omap4-dss";
876 reg = <0x58000000 0x80>;
877 status = "disabled";
878 ti,hwmods = "dss_core";
879 clocks = <&dss_dss_clk>;
880 clock-names = "fck";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 ranges;
884
885 dispc@58001000 {
886 compatible = "ti,omap4-dispc";
887 reg = <0x58001000 0x1000>;
888 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
889 ti,hwmods = "dss_dispc";
890 clocks = <&dss_dss_clk>;
891 clock-names = "fck";
892 };
893
894 rfbi: encoder@58002000 {
895 compatible = "ti,omap4-rfbi";
896 reg = <0x58002000 0x1000>;
897 status = "disabled";
898 ti,hwmods = "dss_rfbi";
2cc84f46 899 clocks = <&dss_dss_clk>, <&l3_div_ck>;
cfe86fcf
TV		 900 clock-names = "fck", "ick";
901 };
902
903 venc: encoder@58003000 {
904 compatible = "ti,omap4-venc";
905 reg = <0x58003000 0x1000>;
906 status = "disabled";
907 ti,hwmods = "dss_venc";
908 clocks = <&dss_tv_clk>;
909 clock-names = "fck";
910 };
911
912 dsi1: encoder@58004000 {
913 compatible = "ti,omap4-dsi";
914 reg = <0x58004000 0x200>,
915 <0x58004200 0x40>,
916 <0x58004300 0x20>;
917 reg-names = "proto", "phy", "pll";
918 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
919 status = "disabled";
920 ti,hwmods = "dss_dsi1";
921 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
922 clock-names = "fck", "sys_clk";
923 };
924
925 dsi2: encoder@58005000 {
926 compatible = "ti,omap4-dsi";
927 reg = <0x58005000 0x200>,
928 <0x58005200 0x40>,
929 <0x58005300 0x20>;
930 reg-names = "proto", "phy", "pll";
931 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
932 status = "disabled";
933 ti,hwmods = "dss_dsi2";
934 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
935 clock-names = "fck", "sys_clk";
936 };
937
938 hdmi: encoder@58006000 {
939 compatible = "ti,omap4-hdmi";
940 reg = <0x58006000 0x200>,
941 <0x58006200 0x100>,
942 <0x58006300 0x100>,
943 <0x58006400 0x1000>;
944 reg-names = "wp", "pll", "phy", "core";
945 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
946 status = "disabled";
947 ti,hwmods = "dss_hdmi";
948 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
949 clock-names = "fck", "sys_clk";
53855b30
JS		 950 dmas = <&sdma 76>;
951 dma-names = "audio_tx";
cfe86fcf
TV		 952 };
953 };
d9fda07a
BC		 954 };
955};
2488ff6c
TK		 956
957/include/ "omap44xx-clocks.dtsi"
Linux kernel - Deliverables
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