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ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi
CommitLineData
d9fda07a
BC		 1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
6d624eab 9#include <dt-bindings/gpio/gpio.h>
8fea7d5a 10#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 11#include <dt-bindings/pinctrl/omap.h>
d9fda07a 12
98ef7957 13#include "skeleton.dtsi"
d9fda07a
BC		 14
15/ {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
18
19 aliases {
20b80942
NM		 20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
cf3c79de
RN		 24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
d9fda07a
BC		 28 };
29
476b679a 30 cpus {
eeb25fd5
LP		 31 #address-cells = <1>;
32 #size-cells = <0>;
33
476b679a
BC		 34 cpu@0 {
35 compatible = "arm,cortex-a9";
eeb25fd5 36 device_type = "cpu";
926fd45b 37 next-level-cache = <&L2>;
eeb25fd5 38 reg = <0x0>;
8d766fa2
NM		 39
40 clocks = <&dpll_mpu_ck>;
41 clock-names = "cpu";
42
43 clock-latency = <300000>; /* From omap-cpufreq driver */
476b679a
BC		 44 };
45 cpu@1 {
46 compatible = "arm,cortex-a9";
eeb25fd5 47 device_type = "cpu";
926fd45b 48 next-level-cache = <&L2>;
eeb25fd5 49 reg = <0x1>;
476b679a
BC		 50 };
51 };
52
5635121e
BC		 53 gic: interrupt-controller@48241000 {
54 compatible = "arm,cortex-a9-gic";
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 reg = <0x48241000 0x1000>,
58 <0x48240100 0x0100>;
59 };
60
926fd45b
SS		 61 L2: l2-cache-controller@48242000 {
62 compatible = "arm,pl310-cache";
63 reg = <0x48242000 0x1000>;
64 cache-unified;
65 cache-level = <2>;
66 };
67
75d71d46 68 local-timer@48240600 {
eed0de27 69 compatible = "arm,cortex-a9-twd-timer";
23c47378 70 clocks = <&mpu_periphclk>;
eed0de27 71 reg = <0x48240600 0x20>;
8fea7d5a 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
eed0de27
SS		 73 };
74
d9fda07a 75 /*
5c5be9db 76 * The soc node represents the soc top level view. It is used for IPs
d9fda07a
BC		 77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
476b679a
BC		 81 mpu {
82 compatible = "ti,omap4-mpu";
83 ti,hwmods = "mpu";
84 };
85
86 dsp {
87 compatible = "ti,omap3-c64";
88 ti,hwmods = "dsp";
89 };
90
91 iva {
92 compatible = "ti,ivahd";
93 ti,hwmods = "iva";
94 };
d9fda07a
BC		 95 };
96
97 /*
98 * XXX: Use a flat representation of the OMAP4 interconnect.
99 * The real OMAP interconnect network is quite complex.
b7ab524b 100 * Since it will not bring real advantage to represent that in DT for
d9fda07a
BC		 101 * the moment, just use a fake OCP bus entry to represent the whole bus
102 * hierarchy.
103 */
104 ocp {
ad8dfac6 105 compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a
BC		 106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges;
ad8dfac6 109 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 110 reg = <0x44000000 0x1000>,
111 <0x44800000 0x2000>,
112 <0x45000000 0x1000>;
8fea7d5a
FV		 113 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
d9fda07a 115
2488ff6c
TK		 116 cm1: cm1@4a004000 {
117 compatible = "ti,omap4-cm1";
118 reg = <0x4a004000 0x2000>;
119
120 cm1_clocks: clocks {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 };
124
125 cm1_clockdomains: clockdomains {
126 };
127 };
128
129 prm: prm@4a306000 {
130 compatible = "ti,omap4-prm";
131 reg = <0x4a306000 0x3000>;
132
133 prm_clocks: clocks {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 };
137
138 prm_clockdomains: clockdomains {
139 };
140 };
141
142 cm2: cm2@4a008000 {
143 compatible = "ti,omap4-cm2";
144 reg = <0x4a008000 0x3000>;
145
146 cm2_clocks: clocks {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 };
150
151 cm2_clockdomains: clockdomains {
152 };
153 };
154
155 scrm: scrm@4a30a000 {
156 compatible = "ti,omap4-scrm";
157 reg = <0x4a30a000 0x2000>;
158
159 scrm_clocks: clocks {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 };
163
164 scrm_clockdomains: clockdomains {
165 };
166 };
167
510c0ffd
JH		 168 counter32k: counter@4a304000 {
169 compatible = "ti,omap-counter32k";
170 reg = <0x4a304000 0x20>;
171 ti,hwmods = "counter_32k";
172 };
173
679e3310
TL		 174 omap4_pmx_core: pinmux@4a100040 {
175 compatible = "ti,omap4-padconf", "pinctrl-single";
176 reg = <0x4a100040 0x0196>;
177 #address-cells = <1>;
178 #size-cells = <0>;
30a69ef7
TL		 179 #interrupt-cells = <1>;
180 interrupt-controller;
679e3310
TL		 181 pinctrl-single,register-width = <16>;
182 pinctrl-single,function-mask = <0x7fff>;
183 };
184 omap4_pmx_wkup: pinmux@4a31e040 {
185 compatible = "ti,omap4-padconf", "pinctrl-single";
186 reg = <0x4a31e040 0x0038>;
187 #address-cells = <1>;
188 #size-cells = <0>;
30a69ef7
TL		 189 #interrupt-cells = <1>;
190 interrupt-controller;
679e3310
TL		 191 pinctrl-single,register-width = <16>;
192 pinctrl-single,function-mask = <0x7fff>;
193 };
194
cd042fe5
B		 195 omap4_padconf_global: tisyscon@4a1005a0 {
196 compatible = "syscon";
197 reg = <0x4a1005a0 0x170>;
198 };
199
200 pbias_regulator: pbias_regulator {
201 compatible = "ti,pbias-omap";
202 reg = <0x60 0x4>;
203 syscon = <&omap4_padconf_global>;
204 pbias_mmc_reg: pbias_mmc_omap4 {
205 regulator-name = "pbias_mmc_omap4";
206 regulator-min-microvolt = <1800000>;
207 regulator-max-microvolt = <3000000>;
208 };
209 };
210
2c2dc545
JH		 211 sdma: dma-controller@4a056000 {
212 compatible = "ti,omap4430-sdma";
213 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 214 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 218 #dma-cells = <1>;
219 #dma-channels = <32>;
220 #dma-requests = <127>;
221 };
222
e3e5a92d
BC		 223 gpio1: gpio@4a310000 {
224 compatible = "ti,omap4-gpio";
48420dbc 225 reg = <0x4a310000 0x200>;
8fea7d5a 226 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d 227 ti,hwmods = "gpio1";
e4b9b9f3 228 ti,gpio-always-on;
e3e5a92d
BC		 229 gpio-controller;
230 #gpio-cells = <2>;
231 interrupt-controller;
ff5c9059 232 #interrupt-cells = <2>;
e3e5a92d
BC		 233 };
234
235 gpio2: gpio@48055000 {
236 compatible = "ti,omap4-gpio";
48420dbc 237 reg = <0x48055000 0x200>;
8fea7d5a 238 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 239 ti,hwmods = "gpio2";
240 gpio-controller;
241 #gpio-cells = <2>;
242 interrupt-controller;
ff5c9059 243 #interrupt-cells = <2>;
e3e5a92d
BC		 244 };
245
246 gpio3: gpio@48057000 {
247 compatible = "ti,omap4-gpio";
48420dbc 248 reg = <0x48057000 0x200>;
8fea7d5a 249 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 250 ti,hwmods = "gpio3";
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
ff5c9059 254 #interrupt-cells = <2>;
e3e5a92d
BC		 255 };
256
257 gpio4: gpio@48059000 {
258 compatible = "ti,omap4-gpio";
48420dbc 259 reg = <0x48059000 0x200>;
8fea7d5a 260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 261 ti,hwmods = "gpio4";
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
ff5c9059 265 #interrupt-cells = <2>;
e3e5a92d
BC		 266 };
267
268 gpio5: gpio@4805b000 {
269 compatible = "ti,omap4-gpio";
48420dbc 270 reg = <0x4805b000 0x200>;
8fea7d5a 271 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 272 ti,hwmods = "gpio5";
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
ff5c9059 276 #interrupt-cells = <2>;
e3e5a92d
BC		 277 };
278
279 gpio6: gpio@4805d000 {
280 compatible = "ti,omap4-gpio";
48420dbc 281 reg = <0x4805d000 0x200>;
8fea7d5a 282 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
e3e5a92d
BC		 283 ti,hwmods = "gpio6";
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
ff5c9059 287 #interrupt-cells = <2>;
e3e5a92d 288 };
cf3c79de 289
1c7dbb55
JH		 290 gpmc: gpmc@50000000 {
291 compatible = "ti,omap4430-gpmc";
292 reg = <0x50000000 0x1000>;
293 #address-cells = <2>;
294 #size-cells = <1>;
8fea7d5a 295 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 296 gpmc,num-cs = <8>;
297 gpmc,num-waitpins = <4>;
298 ti,hwmods = "gpmc";
f12ecbe2 299 ti,no-idle-on-init;
7b8b6af1
FV		 300 clocks = <&l3_div_ck>;
301 clock-names = "fck";
1c7dbb55
JH		 302 };
303
19bfb76c 304 uart1: serial@4806a000 {
cf3c79de 305 compatible = "ti,omap4-uart";
48420dbc 306 reg = <0x4806a000 0x100>;
8fea7d5a 307 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 308 ti,hwmods = "uart1";
309 clock-frequency = <48000000>;
310 };
311
19bfb76c 312 uart2: serial@4806c000 {
cf3c79de 313 compatible = "ti,omap4-uart";
48420dbc 314 reg = <0x4806c000 0x100>;
31f0820a 315 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 316 ti,hwmods = "uart2";
317 clock-frequency = <48000000>;
318 };
319
19bfb76c 320 uart3: serial@48020000 {
cf3c79de 321 compatible = "ti,omap4-uart";
48420dbc 322 reg = <0x48020000 0x100>;
31f0820a 323 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 324 ti,hwmods = "uart3";
325 clock-frequency = <48000000>;
326 };
327
19bfb76c 328 uart4: serial@4806e000 {
cf3c79de 329 compatible = "ti,omap4-uart";
48420dbc 330 reg = <0x4806e000 0x100>;
31f0820a 331 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
cf3c79de
RN		 332 ti,hwmods = "uart4";
333 clock-frequency = <48000000>;
334 };
58e778f9 335
04c7d924
SA		 336 hwspinlock: spinlock@4a0f6000 {
337 compatible = "ti,omap4-hwspinlock";
338 reg = <0x4a0f6000 0x1000>;
339 ti,hwmods = "spinlock";
34054213 340 #hwlock-cells = <1>;
04c7d924
SA		 341 };
342
58e778f9
BC		 343 i2c1: i2c@48070000 {
344 compatible = "ti,omap4-i2c";
48420dbc 345 reg = <0x48070000 0x100>;
8fea7d5a 346 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 347 #address-cells = <1>;
348 #size-cells = <0>;
349 ti,hwmods = "i2c1";
350 };
351
352 i2c2: i2c@48072000 {
353 compatible = "ti,omap4-i2c";
48420dbc 354 reg = <0x48072000 0x100>;
8fea7d5a 355 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 356 #address-cells = <1>;
357 #size-cells = <0>;
358 ti,hwmods = "i2c2";
359 };
360
361 i2c3: i2c@48060000 {
362 compatible = "ti,omap4-i2c";
48420dbc 363 reg = <0x48060000 0x100>;
8fea7d5a 364 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 365 #address-cells = <1>;
366 #size-cells = <0>;
367 ti,hwmods = "i2c3";
368 };
369
370 i2c4: i2c@48350000 {
371 compatible = "ti,omap4-i2c";
48420dbc 372 reg = <0x48350000 0x100>;
8fea7d5a 373 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
58e778f9
BC		 374 #address-cells = <1>;
375 #size-cells = <0>;
376 ti,hwmods = "i2c4";
377 };
efcf1e50
BC		 378
379 mcspi1: spi@48098000 {
380 compatible = "ti,omap4-mcspi";
48420dbc 381 reg = <0x48098000 0x200>;
8fea7d5a 382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 383 #address-cells = <1>;
384 #size-cells = <0>;
385 ti,hwmods = "mcspi1";
386 ti,spi-num-cs = <4>;
2c2dc545
JH		 387 dmas = <&sdma 35>,
388 <&sdma 36>,
389 <&sdma 37>,
390 <&sdma 38>,
391 <&sdma 39>,
392 <&sdma 40>,
393 <&sdma 41>,
394 <&sdma 42>;
395 dma-names = "tx0", "rx0", "tx1", "rx1",
396 "tx2", "rx2", "tx3", "rx3";
efcf1e50
BC		 397 };
398
399 mcspi2: spi@4809a000 {
400 compatible = "ti,omap4-mcspi";
48420dbc 401 reg = <0x4809a000 0x200>;
8fea7d5a 402 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 403 #address-cells = <1>;
404 #size-cells = <0>;
405 ti,hwmods = "mcspi2";
406 ti,spi-num-cs = <2>;
2c2dc545
JH		 407 dmas = <&sdma 43>,
408 <&sdma 44>,
409 <&sdma 45>,
410 <&sdma 46>;
411 dma-names = "tx0", "rx0", "tx1", "rx1";
efcf1e50
BC		 412 };
413
414 mcspi3: spi@480b8000 {
415 compatible = "ti,omap4-mcspi";
48420dbc 416 reg = <0x480b8000 0x200>;
8fea7d5a 417 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "mcspi3";
421 ti,spi-num-cs = <2>;
2c2dc545
JH		 422 dmas = <&sdma 15>, <&sdma 16>;
423 dma-names = "tx0", "rx0";
efcf1e50
BC		 424 };
425
426 mcspi4: spi@480ba000 {
427 compatible = "ti,omap4-mcspi";
48420dbc 428 reg = <0x480ba000 0x200>;
8fea7d5a 429 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
efcf1e50
BC		 430 #address-cells = <1>;
431 #size-cells = <0>;
432 ti,hwmods = "mcspi4";
433 ti,spi-num-cs = <1>;
2c2dc545
JH		 434 dmas = <&sdma 70>, <&sdma 71>;
435 dma-names = "tx0", "rx0";
efcf1e50 436 };
74981768
RN		 437
438 mmc1: mmc@4809c000 {
439 compatible = "ti,omap4-hsmmc";
48420dbc 440 reg = <0x4809c000 0x400>;
8fea7d5a 441 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 442 ti,hwmods = "mmc1";
443 ti,dual-volt;
444 ti,needs-special-reset;
2c2dc545
JH		 445 dmas = <&sdma 61>, <&sdma 62>;
446 dma-names = "tx", "rx";
cd042fe5 447 pbias-supply = <&pbias_mmc_reg>;
74981768
RN		 448 };
449
450 mmc2: mmc@480b4000 {
451 compatible = "ti,omap4-hsmmc";
48420dbc 452 reg = <0x480b4000 0x400>;
8fea7d5a 453 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 454 ti,hwmods = "mmc2";
455 ti,needs-special-reset;
2c2dc545
JH		 456 dmas = <&sdma 47>, <&sdma 48>;
457 dma-names = "tx", "rx";
74981768
RN		 458 };
459
460 mmc3: mmc@480ad000 {
461 compatible = "ti,omap4-hsmmc";
48420dbc 462 reg = <0x480ad000 0x400>;
8fea7d5a 463 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 464 ti,hwmods = "mmc3";
465 ti,needs-special-reset;
2c2dc545
JH		 466 dmas = <&sdma 77>, <&sdma 78>;
467 dma-names = "tx", "rx";
74981768
RN		 468 };
469
470 mmc4: mmc@480d1000 {
471 compatible = "ti,omap4-hsmmc";
48420dbc 472 reg = <0x480d1000 0x400>;
8fea7d5a 473 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 474 ti,hwmods = "mmc4";
475 ti,needs-special-reset;
2c2dc545
JH		 476 dmas = <&sdma 57>, <&sdma 58>;
477 dma-names = "tx", "rx";
74981768
RN		 478 };
479
480 mmc5: mmc@480d5000 {
481 compatible = "ti,omap4-hsmmc";
48420dbc 482 reg = <0x480d5000 0x400>;
8fea7d5a 483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
74981768
RN		 484 ti,hwmods = "mmc5";
485 ti,needs-special-reset;
2c2dc545
JH		 486 dmas = <&sdma 59>, <&sdma 60>;
487 dma-names = "tx", "rx";
74981768 488 };
94c30732 489
21bd85a1
FV		 490 mmu_dsp: mmu@4a066000 {
491 compatible = "ti,omap4-iommu";
492 reg = <0x4a066000 0x100>;
493 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "mmu_dsp";
495 };
496
497 mmu_ipu: mmu@55082000 {
498 compatible = "ti,omap4-iommu";
499 reg = <0x55082000 0x100>;
500 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
501 ti,hwmods = "mmu_ipu";
502 ti,iommu-bus-err-back;
503 };
504
94c30732
XJ		 505 wdt2: wdt@4a314000 {
506 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
48420dbc 507 reg = <0x4a314000 0x80>;
8fea7d5a 508 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
94c30732
XJ		 509 ti,hwmods = "wd_timer2";
510 };
4f4b5c74
PU		 511
512 mcpdm: mcpdm@40132000 {
513 compatible = "ti,omap4-mcpdm";
514 reg = <0x40132000 0x7f>, /* MPU private access */
515 <0x49032000 0x7f>; /* L3 Interconnect */
63467cf2 516 reg-names = "mpu", "dma";
8fea7d5a 517 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
4f4b5c74 518 ti,hwmods = "mcpdm";
4e4ead73
SG		 519 dmas = <&sdma 65>,
520 <&sdma 66>;
521 dma-names = "up_link", "dn_link";
7adb0933 522 status = "disabled";
4f4b5c74 523 };
a4c38319
PU		 524
525 dmic: dmic@4012e000 {
526 compatible = "ti,omap4-dmic";
527 reg = <0x4012e000 0x7f>, /* MPU private access */
528 <0x4902e000 0x7f>; /* L3 Interconnect */
63467cf2 529 reg-names = "mpu", "dma";
8fea7d5a 530 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
a4c38319 531 ti,hwmods = "dmic";
4e4ead73
SG		 532 dmas = <&sdma 67>;
533 dma-names = "up_link";
7adb0933 534 status = "disabled";
a4c38319 535 };
61bc3544 536
2995a100
PU		 537 mcbsp1: mcbsp@40122000 {
538 compatible = "ti,omap4-mcbsp";
539 reg = <0x40122000 0xff>, /* MPU private access */
540 <0x49022000 0xff>; /* L3 Interconnect */
541 reg-names = "mpu", "dma";
8fea7d5a 542 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2995a100 543 interrupt-names = "common";
2995a100
PU		 544 ti,buffer-size = <128>;
545 ti,hwmods = "mcbsp1";
4e4ead73
SG		 546 dmas = <&sdma 33>,
547 <&sdma 34>;
548 dma-names = "tx", "rx";
7adb0933 549 status = "disabled";
2995a100
PU		 550 };
551
552 mcbsp2: mcbsp@40124000 {
553 compatible = "ti,omap4-mcbsp";
554 reg = <0x40124000 0xff>, /* MPU private access */
555 <0x49024000 0xff>; /* L3 Interconnect */
556 reg-names = "mpu", "dma";
8fea7d5a 557 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
2995a100 558 interrupt-names = "common";
2995a100
PU		 559 ti,buffer-size = <128>;
560 ti,hwmods = "mcbsp2";
4e4ead73
SG		 561 dmas = <&sdma 17>,
562 <&sdma 18>;
563 dma-names = "tx", "rx";
7adb0933 564 status = "disabled";
2995a100
PU		 565 };
566
567 mcbsp3: mcbsp@40126000 {
568 compatible = "ti,omap4-mcbsp";
569 reg = <0x40126000 0xff>, /* MPU private access */
570 <0x49026000 0xff>; /* L3 Interconnect */
571 reg-names = "mpu", "dma";
8fea7d5a 572 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
2995a100 573 interrupt-names = "common";
2995a100
PU		 574 ti,buffer-size = <128>;
575 ti,hwmods = "mcbsp3";
4e4ead73
SG		 576 dmas = <&sdma 19>,
577 <&sdma 20>;
578 dma-names = "tx", "rx";
7adb0933 579 status = "disabled";
2995a100
PU		 580 };
581
582 mcbsp4: mcbsp@48096000 {
583 compatible = "ti,omap4-mcbsp";
584 reg = <0x48096000 0xff>; /* L4 Interconnect */
585 reg-names = "mpu";
8fea7d5a 586 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2995a100 587 interrupt-names = "common";
2995a100
PU		 588 ti,buffer-size = <128>;
589 ti,hwmods = "mcbsp4";
4e4ead73
SG		 590 dmas = <&sdma 31>,
591 <&sdma 32>;
592 dma-names = "tx", "rx";
7adb0933 593 status = "disabled";
2995a100
PU		 594 };
595
61bc3544
SP		 596 keypad: keypad@4a31c000 {
597 compatible = "ti,omap4-keypad";
48420dbc 598 reg = <0x4a31c000 0x80>;
8fea7d5a 599 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
48420dbc 600 reg-names = "mpu";
61bc3544
SP		 601 ti,hwmods = "kbd";
602 };
11c27069 603
1a5fe3ca
AT		 604 dmm@4e000000 {
605 compatible = "ti,omap4-dmm";
606 reg = <0x4e000000 0x800>;
607 interrupts = <0 113 0x4>;
608 ti,hwmods = "dmm";
609 };
610
11c27069
A		 611 emif1: emif@4c000000 {
612 compatible = "ti,emif-4d";
48420dbc 613 reg = <0x4c000000 0x100>;
8fea7d5a 614 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
11c27069 615 ti,hwmods = "emif1";
f12ecbe2 616 ti,no-idle-on-init;
11c27069
A		 617 phy-type = <1>;
618 hw-caps-read-idle-ctrl;
619 hw-caps-ll-interface;
620 hw-caps-temp-alert;
621 };
622
623 emif2: emif@4d000000 {
624 compatible = "ti,emif-4d";
48420dbc 625 reg = <0x4d000000 0x100>;
8fea7d5a 626 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
11c27069 627 ti,hwmods = "emif2";
f12ecbe2 628 ti,no-idle-on-init;
11c27069
A		 629 phy-type = <1>;
630 hw-caps-read-idle-ctrl;
631 hw-caps-ll-interface;
632 hw-caps-temp-alert;
633 };
8f446a7a 634
3ce0a99c 635 ocp2scp@4a0ad000 {
59bafcf6 636 compatible = "ti,omap-ocp2scp";
3ce0a99c 637 reg = <0x4a0ad000 0x1f>;
59bafcf6
KVA		 638 #address-cells = <1>;
639 #size-cells = <1>;
640 ranges;
641 ti,hwmods = "ocp2scp_usb_phy";
cf0d869e
KVA		 642 usb2_phy: usb2phy@4a0ad080 {
643 compatible = "ti,omap-usb2";
644 reg = <0x4a0ad080 0x58>;
470019a4 645 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 646 clocks = <&usb_phy_cm_clk32k>;
647 clock-names = "wkupclk";
975d963e 648 #phy-cells = <0>;
cf0d869e 649 };
59bafcf6 650 };
fab8ad0b 651
8ebc30dd
SA		 652 mailbox: mailbox@4a0f4000 {
653 compatible = "ti,omap4-mailbox";
654 reg = <0x4a0f4000 0x200>;
655 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
656 ti,hwmods = "mailbox";
657 ti,mbox-num-users = <3>;
658 ti,mbox-num-fifos = <8>;
d27704d1
SA		 659 mbox_ipu: mbox_ipu {
660 ti,mbox-tx = <0 0 0>;
661 ti,mbox-rx = <1 0 0>;
662 };
663 mbox_dsp: mbox_dsp {
664 ti,mbox-tx = <3 0 0>;
665 ti,mbox-rx = <2 0 0>;
666 };
8ebc30dd
SA		 667 };
668
fab8ad0b 669 timer1: timer@4a318000 {
002e1ec5 670 compatible = "ti,omap3430-timer";
fab8ad0b 671 reg = <0x4a318000 0x80>;
8fea7d5a 672 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 673 ti,hwmods = "timer1";
674 ti,timer-alwon;
675 };
676
677 timer2: timer@48032000 {
002e1ec5 678 compatible = "ti,omap3430-timer";
fab8ad0b 679 reg = <0x48032000 0x80>;
8fea7d5a 680 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 681 ti,hwmods = "timer2";
682 };
683
684 timer3: timer@48034000 {
002e1ec5 685 compatible = "ti,omap4430-timer";
fab8ad0b 686 reg = <0x48034000 0x80>;
8fea7d5a 687 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 688 ti,hwmods = "timer3";
689 };
690
691 timer4: timer@48036000 {
002e1ec5 692 compatible = "ti,omap4430-timer";
fab8ad0b 693 reg = <0x48036000 0x80>;
8fea7d5a 694 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 695 ti,hwmods = "timer4";
696 };
697
d03a93bb 698 timer5: timer@40138000 {
002e1ec5 699 compatible = "ti,omap4430-timer";
d03a93bb
JH		 700 reg = <0x40138000 0x80>,
701 <0x49038000 0x80>;
8fea7d5a 702 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 703 ti,hwmods = "timer5";
704 ti,timer-dsp;
705 };
706
d03a93bb 707 timer6: timer@4013a000 {
002e1ec5 708 compatible = "ti,omap4430-timer";
d03a93bb
JH		 709 reg = <0x4013a000 0x80>,
710 <0x4903a000 0x80>;
8fea7d5a 711 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 712 ti,hwmods = "timer6";
713 ti,timer-dsp;
714 };
715
d03a93bb 716 timer7: timer@4013c000 {
002e1ec5 717 compatible = "ti,omap4430-timer";
d03a93bb
JH		 718 reg = <0x4013c000 0x80>,
719 <0x4903c000 0x80>;
8fea7d5a 720 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 721 ti,hwmods = "timer7";
722 ti,timer-dsp;
723 };
724
d03a93bb 725 timer8: timer@4013e000 {
002e1ec5 726 compatible = "ti,omap4430-timer";
d03a93bb
JH		 727 reg = <0x4013e000 0x80>,
728 <0x4903e000 0x80>;
8fea7d5a 729 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 730 ti,hwmods = "timer8";
731 ti,timer-pwm;
732 ti,timer-dsp;
733 };
734
735 timer9: timer@4803e000 {
002e1ec5 736 compatible = "ti,omap4430-timer";
fab8ad0b 737 reg = <0x4803e000 0x80>;
8fea7d5a 738 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 739 ti,hwmods = "timer9";
740 ti,timer-pwm;
741 };
742
743 timer10: timer@48086000 {
002e1ec5 744 compatible = "ti,omap3430-timer";
fab8ad0b 745 reg = <0x48086000 0x80>;
8fea7d5a 746 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 747 ti,hwmods = "timer10";
748 ti,timer-pwm;
749 };
750
751 timer11: timer@48088000 {
002e1ec5 752 compatible = "ti,omap4430-timer";
fab8ad0b 753 reg = <0x48088000 0x80>;
8fea7d5a 754 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
fab8ad0b
JH		 755 ti,hwmods = "timer11";
756 ti,timer-pwm;
757 };
f17c8994
RQ		 758
759 usbhstll: usbhstll@4a062000 {
760 compatible = "ti,usbhs-tll";
761 reg = <0x4a062000 0x1000>;
8fea7d5a 762 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 763 ti,hwmods = "usb_tll_hs";
764 };
765
766 usbhshost: usbhshost@4a064000 {
767 compatible = "ti,usbhs-host";
768 reg = <0x4a064000 0x800>;
769 ti,hwmods = "usb_host_hs";
770 #address-cells = <1>;
771 #size-cells = <1>;
772 ranges;
051fc06d
RQ		 773 clocks = <&init_60m_fclk>,
774 <&xclk60mhsp1_ck>,
775 <&xclk60mhsp2_ck>;
776 clock-names = "refclk_60m_int",
777 "refclk_60m_ext_p1",
778 "refclk_60m_ext_p2";
f17c8994
RQ		 779
780 usbhsohci: ohci@4a064800 {
a2525e54 781 compatible = "ti,ohci-omap3";
f17c8994
RQ		 782 reg = <0x4a064800 0x400>;
783 interrupt-parent = <&gic>;
8fea7d5a 784 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 785 };
786
787 usbhsehci: ehci@4a064c00 {
a2525e54 788 compatible = "ti,ehci-omap";
f17c8994
RQ		 789 reg = <0x4a064c00 0x400>;
790 interrupt-parent = <&gic>;
8fea7d5a 791 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
f17c8994
RQ		 792 };
793 };
840e5fd8 794
470019a4
RQ		 795 omap_control_usb2phy: control-phy@4a002300 {
796 compatible = "ti,control-phy-usb2";
797 reg = <0x4a002300 0x4>;
798 reg-names = "power";
799 };
800
801 omap_control_usbotg: control-phy@4a00233c {
802 compatible = "ti,control-phy-otghs";
803 reg = <0x4a00233c 0x4>;
804 reg-names = "otghs_control";
840e5fd8 805 };
ad871c10
KVA		 806
807 usb_otg_hs: usb_otg_hs@4a0ab000 {
808 compatible = "ti,omap4-musb";
809 reg = <0x4a0ab000 0x7ff>;
8fea7d5a 810 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
ad871c10
KVA		 811 interrupt-names = "mc", "dma";
812 ti,hwmods = "usb_otg_hs";
813 usb-phy = <&usb2_phy>;
975d963e
KVA		 814 phys = <&usb2_phy>;
815 phy-names = "usb2-phy";
ad871c10
KVA		 816 multipoint = <1>;
817 num-eps = <16>;
818 ram-bits = <12>;
470019a4 819 ctrl-module = <&omap_control_usbotg>;
ad871c10 820 };
dd6317df
JF		 821
822 aes: aes@4b501000 {
823 compatible = "ti,omap4-aes";
824 ti,hwmods = "aes";
825 reg = <0x4b501000 0xa0>;
826 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
827 dmas = <&sdma 111>, <&sdma 110>;
828 dma-names = "tx", "rx";
829 };
806e9431
JF		 830
831 des: des@480a5000 {
832 compatible = "ti,omap4-des";
833 ti,hwmods = "des";
834 reg = <0x480a5000 0xa0>;
835 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
836 dmas = <&sdma 117>, <&sdma 116>;
837 dma-names = "tx", "rx";
838 };
e12c7737
AT		 839
840 abb_mpu: regulator-abb-mpu {
841 compatible = "ti,abb-v2";
842 regulator-name = "abb_mpu";
843 #address-cells = <0>;
844 #size-cells = <0>;
845 ti,tranxdone-status-mask = <0x80>;
846 clocks = <&sys_clkin_ck>;
847 ti,settling-time = <50>;
848 ti,clock-cycles = <16>;
849
850 status = "disabled";
851 };
852
853 abb_iva: regulator-abb-iva {
854 compatible = "ti,abb-v2";
855 regulator-name = "abb_iva";
856 #address-cells = <0>;
857 #size-cells = <0>;
858 ti,tranxdone-status-mask = <0x80000000>;
859 clocks = <&sys_clkin_ck>;
860 ti,settling-time = <50>;
861 ti,clock-cycles = <16>;
862
863 status = "disabled";
864 };
cfe86fcf
TV		 865
866 dss: dss@58000000 {
867 compatible = "ti,omap4-dss";
868 reg = <0x58000000 0x80>;
869 status = "disabled";
870 ti,hwmods = "dss_core";
871 clocks = <&dss_dss_clk>;
872 clock-names = "fck";
873 #address-cells = <1>;
874 #size-cells = <1>;
875 ranges;
876
877 dispc@58001000 {
878 compatible = "ti,omap4-dispc";
879 reg = <0x58001000 0x1000>;
880 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
881 ti,hwmods = "dss_dispc";
882 clocks = <&dss_dss_clk>;
883 clock-names = "fck";
884 };
885
886 rfbi: encoder@58002000 {
887 compatible = "ti,omap4-rfbi";
888 reg = <0x58002000 0x1000>;
889 status = "disabled";
890 ti,hwmods = "dss_rfbi";
891 clocks = <&dss_dss_clk>, <&dss_fck>;
892 clock-names = "fck", "ick";
893 };
894
895 venc: encoder@58003000 {
896 compatible = "ti,omap4-venc";
897 reg = <0x58003000 0x1000>;
898 status = "disabled";
899 ti,hwmods = "dss_venc";
900 clocks = <&dss_tv_clk>;
901 clock-names = "fck";
902 };
903
904 dsi1: encoder@58004000 {
905 compatible = "ti,omap4-dsi";
906 reg = <0x58004000 0x200>,
907 <0x58004200 0x40>,
908 <0x58004300 0x20>;
909 reg-names = "proto", "phy", "pll";
910 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
911 status = "disabled";
912 ti,hwmods = "dss_dsi1";
913 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
914 clock-names = "fck", "sys_clk";
915 };
916
917 dsi2: encoder@58005000 {
918 compatible = "ti,omap4-dsi";
919 reg = <0x58005000 0x200>,
920 <0x58005200 0x40>,
921 <0x58005300 0x20>;
922 reg-names = "proto", "phy", "pll";
923 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
924 status = "disabled";
925 ti,hwmods = "dss_dsi2";
926 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
927 clock-names = "fck", "sys_clk";
928 };
929
930 hdmi: encoder@58006000 {
931 compatible = "ti,omap4-hdmi";
932 reg = <0x58006000 0x200>,
933 <0x58006200 0x100>,
934 <0x58006300 0x100>,
935 <0x58006400 0x1000>;
936 reg-names = "wp", "pll", "phy", "core";
937 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
938 status = "disabled";
939 ti,hwmods = "dss_hdmi";
940 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
941 clock-names = "fck", "sys_clk";
53855b30
JS		 942 dmas = <&sdma 76>;
943 dma-names = "audio_tx";
cfe86fcf
TV		 944 };
945 };
d9fda07a
BC		 946 };
947};
2488ff6c
TK		 948
949/include/ "omap44xx-clocks.dtsi"
Linux kernel - Deliverables
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