[deliverable/linux.git] / arch / arm / boot / dts / omap4.dtsi

/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap4430", "ti,omap4";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
		};
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
	};

	L2: l2-cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	local-timer@0x48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x48240600 0x20>;
		interrupts = <1 13 0x304>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap4-mpu";
			ti,hwmods = "mpu";
		};

		dsp {
			compatible = "ti,omap3-c64";
			ti,hwmods = "dsp";
		};

		iva {
			compatible = "ti,ivahd";
			ti,hwmods = "iva";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP4 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		gpio1: gpio@4a310000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@48350000 {
			compatible = "ti,omap4-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
		};

		wdt2: wdt@4a314000 {
			compatible = "ti,omap4-wdt", "ti,omap3-wdt";
			ti,hwmods = "wd_timer2";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			interrupt-parent = <&gic>;
			ti,hwmods = "mcpdm";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			interrupt-parent = <&gic>;
			ti,hwmods = "dmic";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			interrupt-parent = <&gic>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			interrupt-parent = <&gic>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			interrupt-parent = <&gic>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};

		mcbsp4: mcbsp@48096000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x48096000 0xff>; /* L4 Interconnect */
			reg-names = "mpu";
			interrupts = <0 16 0x4>;
			interrupt-names = "common";
			interrupt-parent = <&gic>;
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
		};

		keypad: keypad@4a31c000 {
			compatible = "ti,omap4-keypad";
			ti,hwmods = "kbd";
		};

		emif1: emif@4c000000 {
			compatible = "ti,emif-4d";
			ti,hwmods = "emif1";
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@4d000000 {
			compatible = "ti,emif-4d";
			ti,hwmods = "emif2";
			phy-type = <1>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};
	};
};
Commit	Line	Data
d9fda07a BC	1	/*
	2	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/*
	10	* Carveout for multimedia usecases
	11	* It should be the last 48MB of the first 512MB memory part
	12	* In theory, it should not even exist. That zone should be reserved
	13	* dynamically during the .reserve callback.
	14	*/
	15	/memreserve/ 0x9d000000 0x03000000;
	16
	17	/include/ "skeleton.dtsi"
	18
	19	/ {
	20	compatible = "ti,omap4430", "ti,omap4";
	21	interrupt-parent = <&gic>;
	22
	23	aliases {
cf3c79de RN	24	serial0 = &uart1;
	25	serial1 = &uart2;
	26	serial2 = &uart3;
	27	serial3 = &uart4;
d9fda07a BC	28	};
d9fda07a BC	29
476b679a BC	30	cpus {
	31	cpu@0 {
	32	compatible = "arm,cortex-a9";
926fd45b	33	next-level-cache = <&L2>;
476b679a BC	34	};
	35	cpu@1 {
	36	compatible = "arm,cortex-a9";
926fd45b	37	next-level-cache = <&L2>;
476b679a BC	38	};
	39	};
	40
5635121e BC	41	gic: interrupt-controller@48241000 {
	42	compatible = "arm,cortex-a9-gic";
	43	interrupt-controller;
	44	#interrupt-cells = <3>;
	45	reg = <0x48241000 0x1000>,
	46	<0x48240100 0x0100>;
	47	};
	48
926fd45b SS	49	L2: l2-cache-controller@48242000 {
	50	compatible = "arm,pl310-cache";
	51	reg = <0x48242000 0x1000>;
	52	cache-unified;
	53	cache-level = <2>;
	54	};
	55
eed0de27 SS	56	local-timer@0x48240600 {
	57	compatible = "arm,cortex-a9-twd-timer";
	58	reg = <0x48240600 0x20>;
	59	interrupts = <1 13 0x304>;
	60	};
	61
d9fda07a BC	62	/*
	63	* The soc node represents the soc top level view. It is uses for IPs
	64	* that are not memory mapped in the MPU view or for the MPU itself.
	65	*/
	66	soc {
	67	compatible = "ti,omap-infra";
476b679a BC	68	mpu {
	69	compatible = "ti,omap4-mpu";
	70	ti,hwmods = "mpu";
	71	};
	72
	73	dsp {
	74	compatible = "ti,omap3-c64";
	75	ti,hwmods = "dsp";
	76	};
	77
	78	iva {
	79	compatible = "ti,ivahd";
	80	ti,hwmods = "iva";
	81	};
d9fda07a BC	82	};
	83
	84	/*
	85	* XXX: Use a flat representation of the OMAP4 interconnect.
	86	* The real OMAP interconnect network is quite complex.
d9fda07a BC	87	* Since that will not bring real advantage to represent that in DT for
	88	* the moment, just use a fake OCP bus entry to represent the whole bus
	89	* hierarchy.
	90	*/
	91	ocp {
ad8dfac6	92	compatible = "ti,omap4-l3-noc", "simple-bus";
d9fda07a BC	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
ad8dfac6	96	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
d9fda07a	97
e3e5a92d BC	98	gpio1: gpio@4a310000 {
	99	compatible = "ti,omap4-gpio";
	100	ti,hwmods = "gpio1";
	101	gpio-controller;
	102	#gpio-cells = <2>;
	103	interrupt-controller;
	104	#interrupt-cells = <1>;
	105	};
	106
	107	gpio2: gpio@48055000 {
	108	compatible = "ti,omap4-gpio";
	109	ti,hwmods = "gpio2";
	110	gpio-controller;
	111	#gpio-cells = <2>;
	112	interrupt-controller;
	113	#interrupt-cells = <1>;
	114	};
	115
	116	gpio3: gpio@48057000 {
	117	compatible = "ti,omap4-gpio";
	118	ti,hwmods = "gpio3";
	119	gpio-controller;
	120	#gpio-cells = <2>;
	121	interrupt-controller;
	122	#interrupt-cells = <1>;
	123	};
	124
	125	gpio4: gpio@48059000 {
	126	compatible = "ti,omap4-gpio";
	127	ti,hwmods = "gpio4";
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-controller;
	131	#interrupt-cells = <1>;
	132	};
	133
	134	gpio5: gpio@4805b000 {
	135	compatible = "ti,omap4-gpio";
	136	ti,hwmods = "gpio5";
	137	gpio-controller;
	138	#gpio-cells = <2>;
	139	interrupt-controller;
	140	#interrupt-cells = <1>;
	141	};
	142
	143	gpio6: gpio@4805d000 {
	144	compatible = "ti,omap4-gpio";
	145	ti,hwmods = "gpio6";
	146	gpio-controller;
	147	#gpio-cells = <2>;
	148	interrupt-controller;
	149	#interrupt-cells = <1>;
	150	};
cf3c79de	151
19bfb76c	152	uart1: serial@4806a000 {
cf3c79de RN	153	compatible = "ti,omap4-uart";
	154	ti,hwmods = "uart1";
	155	clock-frequency = <48000000>;
	156	};
	157
19bfb76c	158	uart2: serial@4806c000 {
cf3c79de RN	159	compatible = "ti,omap4-uart";
	160	ti,hwmods = "uart2";
	161	clock-frequency = <48000000>;
	162	};
	163
19bfb76c	164	uart3: serial@48020000 {
cf3c79de RN	165	compatible = "ti,omap4-uart";
	166	ti,hwmods = "uart3";
	167	clock-frequency = <48000000>;
	168	};
	169
19bfb76c	170	uart4: serial@4806e000 {
cf3c79de RN	171	compatible = "ti,omap4-uart";
	172	ti,hwmods = "uart4";
	173	clock-frequency = <48000000>;
	174	};
58e778f9 BC	175
	176	i2c1: i2c@48070000 {
	177	compatible = "ti,omap4-i2c";
	178	#address-cells = <1>;
	179	#size-cells = <0>;
	180	ti,hwmods = "i2c1";
	181	};
	182
	183	i2c2: i2c@48072000 {
	184	compatible = "ti,omap4-i2c";
	185	#address-cells = <1>;
	186	#size-cells = <0>;
	187	ti,hwmods = "i2c2";
	188	};
	189
	190	i2c3: i2c@48060000 {
	191	compatible = "ti,omap4-i2c";
	192	#address-cells = <1>;
	193	#size-cells = <0>;
	194	ti,hwmods = "i2c3";
	195	};
	196
	197	i2c4: i2c@48350000 {
	198	compatible = "ti,omap4-i2c";
	199	#address-cells = <1>;
	200	#size-cells = <0>;
	201	ti,hwmods = "i2c4";
	202	};
efcf1e50 BC	203
	204	mcspi1: spi@48098000 {
	205	compatible = "ti,omap4-mcspi";
	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	ti,hwmods = "mcspi1";
	209	ti,spi-num-cs = <4>;
	210	};
	211
	212	mcspi2: spi@4809a000 {
	213	compatible = "ti,omap4-mcspi";
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	ti,hwmods = "mcspi2";
	217	ti,spi-num-cs = <2>;
	218	};
	219
	220	mcspi3: spi@480b8000 {
	221	compatible = "ti,omap4-mcspi";
	222	#address-cells = <1>;
	223	#size-cells = <0>;
	224	ti,hwmods = "mcspi3";
	225	ti,spi-num-cs = <2>;
	226	};
	227
	228	mcspi4: spi@480ba000 {
	229	compatible = "ti,omap4-mcspi";
	230	#address-cells = <1>;
	231	#size-cells = <0>;
	232	ti,hwmods = "mcspi4";
	233	ti,spi-num-cs = <1>;
	234	};
74981768 RN	235
	236	mmc1: mmc@4809c000 {
	237	compatible = "ti,omap4-hsmmc";
	238	ti,hwmods = "mmc1";
	239	ti,dual-volt;
	240	ti,needs-special-reset;
	241	};
	242
	243	mmc2: mmc@480b4000 {
	244	compatible = "ti,omap4-hsmmc";
	245	ti,hwmods = "mmc2";
	246	ti,needs-special-reset;
	247	};
	248
	249	mmc3: mmc@480ad000 {
	250	compatible = "ti,omap4-hsmmc";
	251	ti,hwmods = "mmc3";
	252	ti,needs-special-reset;
	253	};
	254
	255	mmc4: mmc@480d1000 {
	256	compatible = "ti,omap4-hsmmc";
	257	ti,hwmods = "mmc4";
	258	ti,needs-special-reset;
	259	};
	260
	261	mmc5: mmc@480d5000 {
	262	compatible = "ti,omap4-hsmmc";
	263	ti,hwmods = "mmc5";
	264	ti,needs-special-reset;
	265	};
94c30732 XJ	266
	267	wdt2: wdt@4a314000 {
	268	compatible = "ti,omap4-wdt", "ti,omap3-wdt";
	269	ti,hwmods = "wd_timer2";
	270	};
4f4b5c74 PU	271
	272	mcpdm: mcpdm@40132000 {
	273	compatible = "ti,omap4-mcpdm";
	274	reg = <0x40132000 0x7f>, /* MPU private access */
	275	<0x49032000 0x7f>; /* L3 Interconnect */
63467cf2	276	reg-names = "mpu", "dma";
4f4b5c74 PU	277	interrupts = <0 112 0x4>;
	278	interrupt-parent = <&gic>;
	279	ti,hwmods = "mcpdm";
	280	};
a4c38319 PU	281
	282	dmic: dmic@4012e000 {
	283	compatible = "ti,omap4-dmic";
	284	reg = <0x4012e000 0x7f>, /* MPU private access */
	285	<0x4902e000 0x7f>; /* L3 Interconnect */
63467cf2	286	reg-names = "mpu", "dma";
a4c38319 PU	287	interrupts = <0 114 0x4>;
	288	interrupt-parent = <&gic>;
	289	ti,hwmods = "dmic";
	290	};
61bc3544	291
2995a100 PU	292	mcbsp1: mcbsp@40122000 {
	293	compatible = "ti,omap4-mcbsp";
	294	reg = <0x40122000 0xff>, /* MPU private access */
	295	<0x49022000 0xff>; /* L3 Interconnect */
	296	reg-names = "mpu", "dma";
	297	interrupts = <0 17 0x4>;
	298	interrupt-names = "common";
	299	interrupt-parent = <&gic>;
	300	ti,buffer-size = <128>;
	301	ti,hwmods = "mcbsp1";
	302	};
	303
	304	mcbsp2: mcbsp@40124000 {
	305	compatible = "ti,omap4-mcbsp";
	306	reg = <0x40124000 0xff>, /* MPU private access */
	307	<0x49024000 0xff>; /* L3 Interconnect */
	308	reg-names = "mpu", "dma";
	309	interrupts = <0 22 0x4>;
	310	interrupt-names = "common";
	311	interrupt-parent = <&gic>;
	312	ti,buffer-size = <128>;
	313	ti,hwmods = "mcbsp2";
	314	};
	315
	316	mcbsp3: mcbsp@40126000 {
	317	compatible = "ti,omap4-mcbsp";
	318	reg = <0x40126000 0xff>, /* MPU private access */
	319	<0x49026000 0xff>; /* L3 Interconnect */
	320	reg-names = "mpu", "dma";
	321	interrupts = <0 23 0x4>;
	322	interrupt-names = "common";
	323	interrupt-parent = <&gic>;
	324	ti,buffer-size = <128>;
	325	ti,hwmods = "mcbsp3";
	326	};
	327
	328	mcbsp4: mcbsp@48096000 {
	329	compatible = "ti,omap4-mcbsp";
	330	reg = <0x48096000 0xff>; /* L4 Interconnect */
	331	reg-names = "mpu";
	332	interrupts = <0 16 0x4>;
	333	interrupt-names = "common";
	334	interrupt-parent = <&gic>;
	335	ti,buffer-size = <128>;
	336	ti,hwmods = "mcbsp4";
	337	};
	338
61bc3544 SP	339	keypad: keypad@4a31c000 {
	340	compatible = "ti,omap4-keypad";
	341	ti,hwmods = "kbd";
	342	};
11c27069 A	343
	344	emif1: emif@4c000000 {
	345	compatible = "ti,emif-4d";
	346	ti,hwmods = "emif1";
	347	phy-type = <1>;
	348	hw-caps-read-idle-ctrl;
	349	hw-caps-ll-interface;
	350	hw-caps-temp-alert;
	351	};
	352
	353	emif2: emif@4d000000 {
	354	compatible = "ti,emif-4d";
	355	ti,hwmods = "emif2";
	356	phy-type = <1>;
	357	hw-caps-read-idle-ctrl;
	358	hw-caps-ll-interface;
	359	hw-caps-temp-alert;
	360	};
d9fda07a BC	361	};
d9fda07a BC	362	};