Commit | Line | Data |
---|---|---|
d9fda07a BC |
1 | /* |
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
6d624eab FV |
9 | #include <dt-bindings/gpio/gpio.h> |
10 | ||
98ef7957 | 11 | #include "skeleton.dtsi" |
d9fda07a BC |
12 | |
13 | / { | |
14 | compatible = "ti,omap4430", "ti,omap4"; | |
15 | interrupt-parent = <&gic>; | |
16 | ||
17 | aliases { | |
cf3c79de RN |
18 | serial0 = &uart1; |
19 | serial1 = &uart2; | |
20 | serial2 = &uart3; | |
21 | serial3 = &uart4; | |
d9fda07a BC |
22 | }; |
23 | ||
476b679a BC |
24 | cpus { |
25 | cpu@0 { | |
26 | compatible = "arm,cortex-a9"; | |
926fd45b | 27 | next-level-cache = <&L2>; |
476b679a BC |
28 | }; |
29 | cpu@1 { | |
30 | compatible = "arm,cortex-a9"; | |
926fd45b | 31 | next-level-cache = <&L2>; |
476b679a BC |
32 | }; |
33 | }; | |
34 | ||
5635121e BC |
35 | gic: interrupt-controller@48241000 { |
36 | compatible = "arm,cortex-a9-gic"; | |
37 | interrupt-controller; | |
38 | #interrupt-cells = <3>; | |
39 | reg = <0x48241000 0x1000>, | |
40 | <0x48240100 0x0100>; | |
41 | }; | |
42 | ||
926fd45b SS |
43 | L2: l2-cache-controller@48242000 { |
44 | compatible = "arm,pl310-cache"; | |
45 | reg = <0x48242000 0x1000>; | |
46 | cache-unified; | |
47 | cache-level = <2>; | |
48 | }; | |
49 | ||
eed0de27 SS |
50 | local-timer@0x48240600 { |
51 | compatible = "arm,cortex-a9-twd-timer"; | |
52 | reg = <0x48240600 0x20>; | |
53 | interrupts = <1 13 0x304>; | |
54 | }; | |
55 | ||
d9fda07a BC |
56 | /* |
57 | * The soc node represents the soc top level view. It is uses for IPs | |
58 | * that are not memory mapped in the MPU view or for the MPU itself. | |
59 | */ | |
60 | soc { | |
61 | compatible = "ti,omap-infra"; | |
476b679a BC |
62 | mpu { |
63 | compatible = "ti,omap4-mpu"; | |
64 | ti,hwmods = "mpu"; | |
65 | }; | |
66 | ||
67 | dsp { | |
68 | compatible = "ti,omap3-c64"; | |
69 | ti,hwmods = "dsp"; | |
70 | }; | |
71 | ||
72 | iva { | |
73 | compatible = "ti,ivahd"; | |
74 | ti,hwmods = "iva"; | |
75 | }; | |
d9fda07a BC |
76 | }; |
77 | ||
78 | /* | |
79 | * XXX: Use a flat representation of the OMAP4 interconnect. | |
80 | * The real OMAP interconnect network is quite complex. | |
d9fda07a BC |
81 | * Since that will not bring real advantage to represent that in DT for |
82 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
83 | * hierarchy. | |
84 | */ | |
85 | ocp { | |
ad8dfac6 | 86 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
d9fda07a BC |
87 | #address-cells = <1>; |
88 | #size-cells = <1>; | |
89 | ranges; | |
ad8dfac6 | 90 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
20a60eaa SS |
91 | reg = <0x44000000 0x1000>, |
92 | <0x44800000 0x2000>, | |
93 | <0x45000000 0x1000>; | |
94 | interrupts = <0 9 0x4>, | |
95 | <0 10 0x4>; | |
d9fda07a | 96 | |
510c0ffd JH |
97 | counter32k: counter@4a304000 { |
98 | compatible = "ti,omap-counter32k"; | |
99 | reg = <0x4a304000 0x20>; | |
100 | ti,hwmods = "counter_32k"; | |
101 | }; | |
102 | ||
679e3310 TL |
103 | omap4_pmx_core: pinmux@4a100040 { |
104 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
105 | reg = <0x4a100040 0x0196>; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <0>; | |
108 | pinctrl-single,register-width = <16>; | |
109 | pinctrl-single,function-mask = <0x7fff>; | |
110 | }; | |
111 | omap4_pmx_wkup: pinmux@4a31e040 { | |
112 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
113 | reg = <0x4a31e040 0x0038>; | |
114 | #address-cells = <1>; | |
115 | #size-cells = <0>; | |
116 | pinctrl-single,register-width = <16>; | |
117 | pinctrl-single,function-mask = <0x7fff>; | |
118 | }; | |
119 | ||
2c2dc545 JH |
120 | sdma: dma-controller@4a056000 { |
121 | compatible = "ti,omap4430-sdma"; | |
122 | reg = <0x4a056000 0x1000>; | |
123 | interrupts = <0 12 0x4>, | |
124 | <0 13 0x4>, | |
125 | <0 14 0x4>, | |
126 | <0 15 0x4>; | |
127 | #dma-cells = <1>; | |
128 | #dma-channels = <32>; | |
129 | #dma-requests = <127>; | |
130 | }; | |
131 | ||
e3e5a92d BC |
132 | gpio1: gpio@4a310000 { |
133 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
134 | reg = <0x4a310000 0x200>; |
135 | interrupts = <0 29 0x4>; | |
e3e5a92d | 136 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 137 | ti,gpio-always-on; |
e3e5a92d BC |
138 | gpio-controller; |
139 | #gpio-cells = <2>; | |
140 | interrupt-controller; | |
ff5c9059 | 141 | #interrupt-cells = <2>; |
e3e5a92d BC |
142 | }; |
143 | ||
144 | gpio2: gpio@48055000 { | |
145 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
146 | reg = <0x48055000 0x200>; |
147 | interrupts = <0 30 0x4>; | |
e3e5a92d BC |
148 | ti,hwmods = "gpio2"; |
149 | gpio-controller; | |
150 | #gpio-cells = <2>; | |
151 | interrupt-controller; | |
ff5c9059 | 152 | #interrupt-cells = <2>; |
e3e5a92d BC |
153 | }; |
154 | ||
155 | gpio3: gpio@48057000 { | |
156 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
157 | reg = <0x48057000 0x200>; |
158 | interrupts = <0 31 0x4>; | |
e3e5a92d BC |
159 | ti,hwmods = "gpio3"; |
160 | gpio-controller; | |
161 | #gpio-cells = <2>; | |
162 | interrupt-controller; | |
ff5c9059 | 163 | #interrupt-cells = <2>; |
e3e5a92d BC |
164 | }; |
165 | ||
166 | gpio4: gpio@48059000 { | |
167 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
168 | reg = <0x48059000 0x200>; |
169 | interrupts = <0 32 0x4>; | |
e3e5a92d BC |
170 | ti,hwmods = "gpio4"; |
171 | gpio-controller; | |
172 | #gpio-cells = <2>; | |
173 | interrupt-controller; | |
ff5c9059 | 174 | #interrupt-cells = <2>; |
e3e5a92d BC |
175 | }; |
176 | ||
177 | gpio5: gpio@4805b000 { | |
178 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
179 | reg = <0x4805b000 0x200>; |
180 | interrupts = <0 33 0x4>; | |
e3e5a92d BC |
181 | ti,hwmods = "gpio5"; |
182 | gpio-controller; | |
183 | #gpio-cells = <2>; | |
184 | interrupt-controller; | |
ff5c9059 | 185 | #interrupt-cells = <2>; |
e3e5a92d BC |
186 | }; |
187 | ||
188 | gpio6: gpio@4805d000 { | |
189 | compatible = "ti,omap4-gpio"; | |
48420dbc BC |
190 | reg = <0x4805d000 0x200>; |
191 | interrupts = <0 34 0x4>; | |
e3e5a92d BC |
192 | ti,hwmods = "gpio6"; |
193 | gpio-controller; | |
194 | #gpio-cells = <2>; | |
195 | interrupt-controller; | |
ff5c9059 | 196 | #interrupt-cells = <2>; |
e3e5a92d | 197 | }; |
cf3c79de | 198 | |
1c7dbb55 JH |
199 | gpmc: gpmc@50000000 { |
200 | compatible = "ti,omap4430-gpmc"; | |
201 | reg = <0x50000000 0x1000>; | |
202 | #address-cells = <2>; | |
203 | #size-cells = <1>; | |
204 | interrupts = <0 20 0x4>; | |
205 | gpmc,num-cs = <8>; | |
206 | gpmc,num-waitpins = <4>; | |
207 | ti,hwmods = "gpmc"; | |
208 | }; | |
209 | ||
19bfb76c | 210 | uart1: serial@4806a000 { |
cf3c79de | 211 | compatible = "ti,omap4-uart"; |
48420dbc BC |
212 | reg = <0x4806a000 0x100>; |
213 | interrupts = <0 72 0x4>; | |
cf3c79de RN |
214 | ti,hwmods = "uart1"; |
215 | clock-frequency = <48000000>; | |
216 | }; | |
217 | ||
19bfb76c | 218 | uart2: serial@4806c000 { |
cf3c79de | 219 | compatible = "ti,omap4-uart"; |
48420dbc BC |
220 | reg = <0x4806c000 0x100>; |
221 | interrupts = <0 73 0x4>; | |
cf3c79de RN |
222 | ti,hwmods = "uart2"; |
223 | clock-frequency = <48000000>; | |
224 | }; | |
225 | ||
19bfb76c | 226 | uart3: serial@48020000 { |
cf3c79de | 227 | compatible = "ti,omap4-uart"; |
48420dbc BC |
228 | reg = <0x48020000 0x100>; |
229 | interrupts = <0 74 0x4>; | |
cf3c79de RN |
230 | ti,hwmods = "uart3"; |
231 | clock-frequency = <48000000>; | |
232 | }; | |
233 | ||
19bfb76c | 234 | uart4: serial@4806e000 { |
cf3c79de | 235 | compatible = "ti,omap4-uart"; |
48420dbc BC |
236 | reg = <0x4806e000 0x100>; |
237 | interrupts = <0 70 0x4>; | |
cf3c79de RN |
238 | ti,hwmods = "uart4"; |
239 | clock-frequency = <48000000>; | |
240 | }; | |
58e778f9 BC |
241 | |
242 | i2c1: i2c@48070000 { | |
243 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
244 | reg = <0x48070000 0x100>; |
245 | interrupts = <0 56 0x4>; | |
58e778f9 BC |
246 | #address-cells = <1>; |
247 | #size-cells = <0>; | |
248 | ti,hwmods = "i2c1"; | |
249 | }; | |
250 | ||
251 | i2c2: i2c@48072000 { | |
252 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
253 | reg = <0x48072000 0x100>; |
254 | interrupts = <0 57 0x4>; | |
58e778f9 BC |
255 | #address-cells = <1>; |
256 | #size-cells = <0>; | |
257 | ti,hwmods = "i2c2"; | |
258 | }; | |
259 | ||
260 | i2c3: i2c@48060000 { | |
261 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
262 | reg = <0x48060000 0x100>; |
263 | interrupts = <0 61 0x4>; | |
58e778f9 BC |
264 | #address-cells = <1>; |
265 | #size-cells = <0>; | |
266 | ti,hwmods = "i2c3"; | |
267 | }; | |
268 | ||
269 | i2c4: i2c@48350000 { | |
270 | compatible = "ti,omap4-i2c"; | |
48420dbc BC |
271 | reg = <0x48350000 0x100>; |
272 | interrupts = <0 62 0x4>; | |
58e778f9 BC |
273 | #address-cells = <1>; |
274 | #size-cells = <0>; | |
275 | ti,hwmods = "i2c4"; | |
276 | }; | |
efcf1e50 BC |
277 | |
278 | mcspi1: spi@48098000 { | |
279 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
280 | reg = <0x48098000 0x200>; |
281 | interrupts = <0 65 0x4>; | |
efcf1e50 BC |
282 | #address-cells = <1>; |
283 | #size-cells = <0>; | |
284 | ti,hwmods = "mcspi1"; | |
285 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
286 | dmas = <&sdma 35>, |
287 | <&sdma 36>, | |
288 | <&sdma 37>, | |
289 | <&sdma 38>, | |
290 | <&sdma 39>, | |
291 | <&sdma 40>, | |
292 | <&sdma 41>, | |
293 | <&sdma 42>; | |
294 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
295 | "tx2", "rx2", "tx3", "rx3"; | |
efcf1e50 BC |
296 | }; |
297 | ||
298 | mcspi2: spi@4809a000 { | |
299 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
300 | reg = <0x4809a000 0x200>; |
301 | interrupts = <0 66 0x4>; | |
efcf1e50 BC |
302 | #address-cells = <1>; |
303 | #size-cells = <0>; | |
304 | ti,hwmods = "mcspi2"; | |
305 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
306 | dmas = <&sdma 43>, |
307 | <&sdma 44>, | |
308 | <&sdma 45>, | |
309 | <&sdma 46>; | |
310 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
efcf1e50 BC |
311 | }; |
312 | ||
313 | mcspi3: spi@480b8000 { | |
314 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
315 | reg = <0x480b8000 0x200>; |
316 | interrupts = <0 91 0x4>; | |
efcf1e50 BC |
317 | #address-cells = <1>; |
318 | #size-cells = <0>; | |
319 | ti,hwmods = "mcspi3"; | |
320 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
321 | dmas = <&sdma 15>, <&sdma 16>; |
322 | dma-names = "tx0", "rx0"; | |
efcf1e50 BC |
323 | }; |
324 | ||
325 | mcspi4: spi@480ba000 { | |
326 | compatible = "ti,omap4-mcspi"; | |
48420dbc BC |
327 | reg = <0x480ba000 0x200>; |
328 | interrupts = <0 48 0x4>; | |
efcf1e50 BC |
329 | #address-cells = <1>; |
330 | #size-cells = <0>; | |
331 | ti,hwmods = "mcspi4"; | |
332 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
333 | dmas = <&sdma 70>, <&sdma 71>; |
334 | dma-names = "tx0", "rx0"; | |
efcf1e50 | 335 | }; |
74981768 RN |
336 | |
337 | mmc1: mmc@4809c000 { | |
338 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
339 | reg = <0x4809c000 0x400>; |
340 | interrupts = <0 83 0x4>; | |
74981768 RN |
341 | ti,hwmods = "mmc1"; |
342 | ti,dual-volt; | |
343 | ti,needs-special-reset; | |
2c2dc545 JH |
344 | dmas = <&sdma 61>, <&sdma 62>; |
345 | dma-names = "tx", "rx"; | |
74981768 RN |
346 | }; |
347 | ||
348 | mmc2: mmc@480b4000 { | |
349 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
350 | reg = <0x480b4000 0x400>; |
351 | interrupts = <0 86 0x4>; | |
74981768 RN |
352 | ti,hwmods = "mmc2"; |
353 | ti,needs-special-reset; | |
2c2dc545 JH |
354 | dmas = <&sdma 47>, <&sdma 48>; |
355 | dma-names = "tx", "rx"; | |
74981768 RN |
356 | }; |
357 | ||
358 | mmc3: mmc@480ad000 { | |
359 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
360 | reg = <0x480ad000 0x400>; |
361 | interrupts = <0 94 0x4>; | |
74981768 RN |
362 | ti,hwmods = "mmc3"; |
363 | ti,needs-special-reset; | |
2c2dc545 JH |
364 | dmas = <&sdma 77>, <&sdma 78>; |
365 | dma-names = "tx", "rx"; | |
74981768 RN |
366 | }; |
367 | ||
368 | mmc4: mmc@480d1000 { | |
369 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
370 | reg = <0x480d1000 0x400>; |
371 | interrupts = <0 96 0x4>; | |
74981768 RN |
372 | ti,hwmods = "mmc4"; |
373 | ti,needs-special-reset; | |
2c2dc545 JH |
374 | dmas = <&sdma 57>, <&sdma 58>; |
375 | dma-names = "tx", "rx"; | |
74981768 RN |
376 | }; |
377 | ||
378 | mmc5: mmc@480d5000 { | |
379 | compatible = "ti,omap4-hsmmc"; | |
48420dbc BC |
380 | reg = <0x480d5000 0x400>; |
381 | interrupts = <0 59 0x4>; | |
74981768 RN |
382 | ti,hwmods = "mmc5"; |
383 | ti,needs-special-reset; | |
2c2dc545 JH |
384 | dmas = <&sdma 59>, <&sdma 60>; |
385 | dma-names = "tx", "rx"; | |
74981768 | 386 | }; |
94c30732 XJ |
387 | |
388 | wdt2: wdt@4a314000 { | |
389 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | |
48420dbc BC |
390 | reg = <0x4a314000 0x80>; |
391 | interrupts = <0 80 0x4>; | |
94c30732 XJ |
392 | ti,hwmods = "wd_timer2"; |
393 | }; | |
4f4b5c74 PU |
394 | |
395 | mcpdm: mcpdm@40132000 { | |
396 | compatible = "ti,omap4-mcpdm"; | |
397 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
398 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 399 | reg-names = "mpu", "dma"; |
4f4b5c74 | 400 | interrupts = <0 112 0x4>; |
4f4b5c74 | 401 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
402 | dmas = <&sdma 65>, |
403 | <&sdma 66>; | |
404 | dma-names = "up_link", "dn_link"; | |
4f4b5c74 | 405 | }; |
a4c38319 PU |
406 | |
407 | dmic: dmic@4012e000 { | |
408 | compatible = "ti,omap4-dmic"; | |
409 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
410 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
63467cf2 | 411 | reg-names = "mpu", "dma"; |
a4c38319 | 412 | interrupts = <0 114 0x4>; |
a4c38319 | 413 | ti,hwmods = "dmic"; |
4e4ead73 SG |
414 | dmas = <&sdma 67>; |
415 | dma-names = "up_link"; | |
a4c38319 | 416 | }; |
61bc3544 | 417 | |
2995a100 PU |
418 | mcbsp1: mcbsp@40122000 { |
419 | compatible = "ti,omap4-mcbsp"; | |
420 | reg = <0x40122000 0xff>, /* MPU private access */ | |
421 | <0x49022000 0xff>; /* L3 Interconnect */ | |
422 | reg-names = "mpu", "dma"; | |
423 | interrupts = <0 17 0x4>; | |
424 | interrupt-names = "common"; | |
2995a100 PU |
425 | ti,buffer-size = <128>; |
426 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
427 | dmas = <&sdma 33>, |
428 | <&sdma 34>; | |
429 | dma-names = "tx", "rx"; | |
2995a100 PU |
430 | }; |
431 | ||
432 | mcbsp2: mcbsp@40124000 { | |
433 | compatible = "ti,omap4-mcbsp"; | |
434 | reg = <0x40124000 0xff>, /* MPU private access */ | |
435 | <0x49024000 0xff>; /* L3 Interconnect */ | |
436 | reg-names = "mpu", "dma"; | |
437 | interrupts = <0 22 0x4>; | |
438 | interrupt-names = "common"; | |
2995a100 PU |
439 | ti,buffer-size = <128>; |
440 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
441 | dmas = <&sdma 17>, |
442 | <&sdma 18>; | |
443 | dma-names = "tx", "rx"; | |
2995a100 PU |
444 | }; |
445 | ||
446 | mcbsp3: mcbsp@40126000 { | |
447 | compatible = "ti,omap4-mcbsp"; | |
448 | reg = <0x40126000 0xff>, /* MPU private access */ | |
449 | <0x49026000 0xff>; /* L3 Interconnect */ | |
450 | reg-names = "mpu", "dma"; | |
451 | interrupts = <0 23 0x4>; | |
452 | interrupt-names = "common"; | |
2995a100 PU |
453 | ti,buffer-size = <128>; |
454 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
455 | dmas = <&sdma 19>, |
456 | <&sdma 20>; | |
457 | dma-names = "tx", "rx"; | |
2995a100 PU |
458 | }; |
459 | ||
460 | mcbsp4: mcbsp@48096000 { | |
461 | compatible = "ti,omap4-mcbsp"; | |
462 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | |
463 | reg-names = "mpu"; | |
464 | interrupts = <0 16 0x4>; | |
465 | interrupt-names = "common"; | |
2995a100 PU |
466 | ti,buffer-size = <128>; |
467 | ti,hwmods = "mcbsp4"; | |
4e4ead73 SG |
468 | dmas = <&sdma 31>, |
469 | <&sdma 32>; | |
470 | dma-names = "tx", "rx"; | |
2995a100 PU |
471 | }; |
472 | ||
61bc3544 SP |
473 | keypad: keypad@4a31c000 { |
474 | compatible = "ti,omap4-keypad"; | |
48420dbc BC |
475 | reg = <0x4a31c000 0x80>; |
476 | interrupts = <0 120 0x4>; | |
477 | reg-names = "mpu"; | |
61bc3544 SP |
478 | ti,hwmods = "kbd"; |
479 | }; | |
11c27069 A |
480 | |
481 | emif1: emif@4c000000 { | |
482 | compatible = "ti,emif-4d"; | |
48420dbc BC |
483 | reg = <0x4c000000 0x100>; |
484 | interrupts = <0 110 0x4>; | |
11c27069 A |
485 | ti,hwmods = "emif1"; |
486 | phy-type = <1>; | |
487 | hw-caps-read-idle-ctrl; | |
488 | hw-caps-ll-interface; | |
489 | hw-caps-temp-alert; | |
490 | }; | |
491 | ||
492 | emif2: emif@4d000000 { | |
493 | compatible = "ti,emif-4d"; | |
48420dbc BC |
494 | reg = <0x4d000000 0x100>; |
495 | interrupts = <0 111 0x4>; | |
11c27069 A |
496 | ti,hwmods = "emif2"; |
497 | phy-type = <1>; | |
498 | hw-caps-read-idle-ctrl; | |
499 | hw-caps-ll-interface; | |
500 | hw-caps-temp-alert; | |
501 | }; | |
8f446a7a | 502 | |
3ce0a99c | 503 | ocp2scp@4a0ad000 { |
59bafcf6 | 504 | compatible = "ti,omap-ocp2scp"; |
3ce0a99c | 505 | reg = <0x4a0ad000 0x1f>; |
59bafcf6 KVA |
506 | #address-cells = <1>; |
507 | #size-cells = <1>; | |
508 | ranges; | |
509 | ti,hwmods = "ocp2scp_usb_phy"; | |
cf0d869e KVA |
510 | usb2_phy: usb2phy@4a0ad080 { |
511 | compatible = "ti,omap-usb2"; | |
512 | reg = <0x4a0ad080 0x58>; | |
513 | ctrl-module = <&omap_control_usb>; | |
514 | }; | |
59bafcf6 | 515 | }; |
fab8ad0b JH |
516 | |
517 | timer1: timer@4a318000 { | |
002e1ec5 | 518 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
519 | reg = <0x4a318000 0x80>; |
520 | interrupts = <0 37 0x4>; | |
521 | ti,hwmods = "timer1"; | |
522 | ti,timer-alwon; | |
523 | }; | |
524 | ||
525 | timer2: timer@48032000 { | |
002e1ec5 | 526 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
527 | reg = <0x48032000 0x80>; |
528 | interrupts = <0 38 0x4>; | |
529 | ti,hwmods = "timer2"; | |
530 | }; | |
531 | ||
532 | timer3: timer@48034000 { | |
002e1ec5 | 533 | compatible = "ti,omap4430-timer"; |
fab8ad0b JH |
534 | reg = <0x48034000 0x80>; |
535 | interrupts = <0 39 0x4>; | |
536 | ti,hwmods = "timer3"; | |
537 | }; | |
538 | ||
539 | timer4: timer@48036000 { | |
002e1ec5 | 540 | compatible = "ti,omap4430-timer"; |
fab8ad0b JH |
541 | reg = <0x48036000 0x80>; |
542 | interrupts = <0 40 0x4>; | |
543 | ti,hwmods = "timer4"; | |
544 | }; | |
545 | ||
d03a93bb | 546 | timer5: timer@40138000 { |
002e1ec5 | 547 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
548 | reg = <0x40138000 0x80>, |
549 | <0x49038000 0x80>; | |
fab8ad0b JH |
550 | interrupts = <0 41 0x4>; |
551 | ti,hwmods = "timer5"; | |
552 | ti,timer-dsp; | |
553 | }; | |
554 | ||
d03a93bb | 555 | timer6: timer@4013a000 { |
002e1ec5 | 556 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
557 | reg = <0x4013a000 0x80>, |
558 | <0x4903a000 0x80>; | |
fab8ad0b JH |
559 | interrupts = <0 42 0x4>; |
560 | ti,hwmods = "timer6"; | |
561 | ti,timer-dsp; | |
562 | }; | |
563 | ||
d03a93bb | 564 | timer7: timer@4013c000 { |
002e1ec5 | 565 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
566 | reg = <0x4013c000 0x80>, |
567 | <0x4903c000 0x80>; | |
fab8ad0b JH |
568 | interrupts = <0 43 0x4>; |
569 | ti,hwmods = "timer7"; | |
570 | ti,timer-dsp; | |
571 | }; | |
572 | ||
d03a93bb | 573 | timer8: timer@4013e000 { |
002e1ec5 | 574 | compatible = "ti,omap4430-timer"; |
d03a93bb JH |
575 | reg = <0x4013e000 0x80>, |
576 | <0x4903e000 0x80>; | |
fab8ad0b JH |
577 | interrupts = <0 44 0x4>; |
578 | ti,hwmods = "timer8"; | |
579 | ti,timer-pwm; | |
580 | ti,timer-dsp; | |
581 | }; | |
582 | ||
583 | timer9: timer@4803e000 { | |
002e1ec5 | 584 | compatible = "ti,omap4430-timer"; |
fab8ad0b JH |
585 | reg = <0x4803e000 0x80>; |
586 | interrupts = <0 45 0x4>; | |
587 | ti,hwmods = "timer9"; | |
588 | ti,timer-pwm; | |
589 | }; | |
590 | ||
591 | timer10: timer@48086000 { | |
002e1ec5 | 592 | compatible = "ti,omap3430-timer"; |
fab8ad0b JH |
593 | reg = <0x48086000 0x80>; |
594 | interrupts = <0 46 0x4>; | |
595 | ti,hwmods = "timer10"; | |
596 | ti,timer-pwm; | |
597 | }; | |
598 | ||
599 | timer11: timer@48088000 { | |
002e1ec5 | 600 | compatible = "ti,omap4430-timer"; |
fab8ad0b JH |
601 | reg = <0x48088000 0x80>; |
602 | interrupts = <0 47 0x4>; | |
603 | ti,hwmods = "timer11"; | |
604 | ti,timer-pwm; | |
605 | }; | |
f17c8994 RQ |
606 | |
607 | usbhstll: usbhstll@4a062000 { | |
608 | compatible = "ti,usbhs-tll"; | |
609 | reg = <0x4a062000 0x1000>; | |
610 | interrupts = <0 78 0x4>; | |
611 | ti,hwmods = "usb_tll_hs"; | |
612 | }; | |
613 | ||
614 | usbhshost: usbhshost@4a064000 { | |
615 | compatible = "ti,usbhs-host"; | |
616 | reg = <0x4a064000 0x800>; | |
617 | ti,hwmods = "usb_host_hs"; | |
618 | #address-cells = <1>; | |
619 | #size-cells = <1>; | |
620 | ranges; | |
621 | ||
622 | usbhsohci: ohci@4a064800 { | |
623 | compatible = "ti,ohci-omap3", "usb-ohci"; | |
624 | reg = <0x4a064800 0x400>; | |
625 | interrupt-parent = <&gic>; | |
626 | interrupts = <0 76 0x4>; | |
627 | }; | |
628 | ||
629 | usbhsehci: ehci@4a064c00 { | |
630 | compatible = "ti,ehci-omap", "usb-ehci"; | |
631 | reg = <0x4a064c00 0x400>; | |
632 | interrupt-parent = <&gic>; | |
633 | interrupts = <0 77 0x4>; | |
634 | }; | |
635 | }; | |
840e5fd8 KVA |
636 | |
637 | omap_control_usb: omap-control-usb@4a002300 { | |
638 | compatible = "ti,omap-control-usb"; | |
639 | reg = <0x4a002300 0x4>, | |
640 | <0x4a00233c 0x4>; | |
641 | reg-names = "control_dev_conf", "otghs_control"; | |
642 | ti,type = <1>; | |
643 | }; | |
ad871c10 KVA |
644 | |
645 | usb_otg_hs: usb_otg_hs@4a0ab000 { | |
646 | compatible = "ti,omap4-musb"; | |
647 | reg = <0x4a0ab000 0x7ff>; | |
648 | interrupts = <0 92 0x4>, <0 93 0x4>; | |
649 | interrupt-names = "mc", "dma"; | |
650 | ti,hwmods = "usb_otg_hs"; | |
651 | usb-phy = <&usb2_phy>; | |
652 | multipoint = <1>; | |
653 | num-eps = <16>; | |
654 | ram-bits = <12>; | |
655 | ti,has-mailbox; | |
656 | }; | |
d9fda07a BC |
657 | }; |
658 | }; |