Commit | Line | Data |
---|---|---|
6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
6d624eab | 10 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 12 | #include <dt-bindings/pinctrl/omap.h> |
6b5de091 | 13 | |
98ef7957 | 14 | #include "skeleton.dtsi" |
6b5de091 S |
15 | |
16 | / { | |
ba1829bc SS |
17 | #address-cells = <1>; |
18 | #size-cells = <1>; | |
19 | ||
6b5de091 | 20 | compatible = "ti,omap5"; |
7136d457 | 21 | interrupt-parent = <&wakeupgen>; |
6b5de091 S |
22 | |
23 | aliases { | |
20b80942 NM |
24 | i2c0 = &i2c1; |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | i2c3 = &i2c4; | |
28 | i2c4 = &i2c5; | |
6b5de091 S |
29 | serial0 = &uart1; |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &uart6; | |
35 | }; | |
36 | ||
37 | cpus { | |
eeb25fd5 LP |
38 | #address-cells = <1>; |
39 | #size-cells = <0>; | |
40 | ||
b8981d71 | 41 | cpu0: cpu@0 { |
eeb25fd5 | 42 | device_type = "cpu"; |
6b5de091 | 43 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 44 | reg = <0x0>; |
6c24894d K |
45 | |
46 | operating-points = < | |
47 | /* kHz uV */ | |
6c24894d K |
48 | 1000000 1060000 |
49 | 1500000 1250000 | |
50 | >; | |
8d766fa2 NM |
51 | |
52 | clocks = <&dpll_mpu_ck>; | |
53 | clock-names = "cpu"; | |
54 | ||
55 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
56 | ||
2cd29f63 EV |
57 | /* cooling options */ |
58 | cooling-min-level = <0>; | |
59 | cooling-max-level = <2>; | |
60 | #cooling-cells = <2>; /* min followed by max */ | |
6b5de091 S |
61 | }; |
62 | cpu@1 { | |
eeb25fd5 | 63 | device_type = "cpu"; |
6b5de091 | 64 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 65 | reg = <0x1>; |
6b5de091 S |
66 | }; |
67 | }; | |
68 | ||
1b761fc5 EV |
69 | thermal-zones { |
70 | #include "omap4-cpu-thermal.dtsi" | |
71 | #include "omap5-gpu-thermal.dtsi" | |
72 | #include "omap5-core-thermal.dtsi" | |
73 | }; | |
74 | ||
b45ccc4e SS |
75 | timer { |
76 | compatible = "arm,armv7-timer"; | |
8fea7d5a FV |
77 | /* PPI secure/nonsecure IRQ */ |
78 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
79 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
80 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
81 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; | |
7136d457 | 82 | interrupt-parent = <&gic>; |
b45ccc4e SS |
83 | }; |
84 | ||
69a126cb NL |
85 | pmu { |
86 | compatible = "arm,cortex-a15-pmu"; | |
87 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
88 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
89 | }; | |
90 | ||
ba1829bc SS |
91 | gic: interrupt-controller@48211000 { |
92 | compatible = "arm,cortex-a15-gic"; | |
93 | interrupt-controller; | |
94 | #interrupt-cells = <3>; | |
95 | reg = <0x48211000 0x1000>, | |
0129c16c SS |
96 | <0x48212000 0x1000>, |
97 | <0x48214000 0x2000>, | |
98 | <0x48216000 0x2000>; | |
7136d457 MZ |
99 | interrupt-parent = <&gic>; |
100 | }; | |
101 | ||
102 | wakeupgen: interrupt-controller@48281000 { | |
103 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; | |
104 | interrupt-controller; | |
105 | #interrupt-cells = <3>; | |
106 | reg = <0x48281000 0x1000>; | |
107 | interrupt-parent = <&gic>; | |
ba1829bc SS |
108 | }; |
109 | ||
6b5de091 | 110 | /* |
5c5be9db | 111 | * The soc node represents the soc top level view. It is used for IPs |
6b5de091 S |
112 | * that are not memory mapped in the MPU view or for the MPU itself. |
113 | */ | |
114 | soc { | |
115 | compatible = "ti,omap-infra"; | |
116 | mpu { | |
1306c08a | 117 | compatible = "ti,omap4-mpu"; |
6b5de091 | 118 | ti,hwmods = "mpu"; |
1306c08a | 119 | sram = <&ocmcram>; |
6b5de091 S |
120 | }; |
121 | }; | |
122 | ||
123 | /* | |
124 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
125 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 126 | * Since it will not bring real advantage to represent that in DT for |
6b5de091 S |
127 | * the moment, just use a fake OCP bus entry to represent the whole bus |
128 | * hierarchy. | |
129 | */ | |
130 | ocp { | |
e7309c26 | 131 | compatible = "ti,omap5-l3-noc", "simple-bus"; |
6b5de091 S |
132 | #address-cells = <1>; |
133 | #size-cells = <1>; | |
134 | ranges; | |
135 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
20a60eaa SS |
136 | reg = <0x44000000 0x2000>, |
137 | <0x44800000 0x3000>, | |
138 | <0x45000000 0x4000>; | |
8fea7d5a FV |
139 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
140 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6b5de091 | 141 | |
ed8509ed TK |
142 | l4_cfg: l4@4a000000 { |
143 | compatible = "ti,omap5-l4-cfg", "simple-bus"; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <1>; | |
146 | ranges = <0 0x4a000000 0x22a000>; | |
85dc74e9 | 147 | |
ed8509ed TK |
148 | scm_core: scm@2000 { |
149 | compatible = "ti,omap5-scm-core", "simple-bus"; | |
150 | reg = <0x2000 0x1000>; | |
85dc74e9 | 151 | #address-cells = <1>; |
ed8509ed TK |
152 | #size-cells = <1>; |
153 | ranges = <0 0x2000 0x800>; | |
154 | ||
155 | scm_conf: scm_conf@0 { | |
156 | compatible = "syscon"; | |
157 | reg = <0x0 0x800>; | |
158 | #address-cells = <1>; | |
159 | #size-cells = <1>; | |
160 | }; | |
85dc74e9 TK |
161 | }; |
162 | ||
ed8509ed TK |
163 | scm_padconf_core: scm@2800 { |
164 | compatible = "ti,omap5-scm-padconf-core", | |
165 | "simple-bus"; | |
166 | #address-cells = <1>; | |
167 | #size-cells = <1>; | |
168 | ranges = <0 0x2800 0x800>; | |
169 | ||
170 | omap5_pmx_core: pinmux@40 { | |
171 | compatible = "ti,omap5-padconf", | |
172 | "pinctrl-single"; | |
173 | reg = <0x40 0x01b6>; | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | #interrupt-cells = <1>; | |
177 | interrupt-controller; | |
178 | pinctrl-single,register-width = <16>; | |
179 | pinctrl-single,function-mask = <0x7fff>; | |
180 | }; | |
181 | ||
182 | omap5_padconf_global: omap5_padconf_global@5a0 { | |
70caac3f KVA |
183 | compatible = "syscon", |
184 | "simple-bus"; | |
ed8509ed TK |
185 | reg = <0x5a0 0xec>; |
186 | #address-cells = <1>; | |
187 | #size-cells = <1>; | |
9a5e3f27 | 188 | ranges = <0 0x5a0 0xec>; |
ed8509ed TK |
189 | |
190 | pbias_regulator: pbias_regulator { | |
737f146f | 191 | compatible = "ti,pbias-omap5", "ti,pbias-omap"; |
ed8509ed TK |
192 | reg = <0x60 0x4>; |
193 | syscon = <&omap5_padconf_global>; | |
194 | pbias_mmc_reg: pbias_mmc_omap5 { | |
195 | regulator-name = "pbias_mmc_omap5"; | |
196 | regulator-min-microvolt = <1800000>; | |
197 | regulator-max-microvolt = <3000000>; | |
198 | }; | |
199 | }; | |
200 | }; | |
85dc74e9 | 201 | }; |
85dc74e9 | 202 | |
ed8509ed TK |
203 | cm_core_aon: cm_core_aon@4000 { |
204 | compatible = "ti,omap5-cm-core-aon"; | |
205 | reg = <0x4000 0x2000>; | |
85dc74e9 | 206 | |
ed8509ed TK |
207 | cm_core_aon_clocks: clocks { |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
210 | }; | |
85dc74e9 | 211 | |
ed8509ed TK |
212 | cm_core_aon_clockdomains: clockdomains { |
213 | }; | |
85dc74e9 | 214 | }; |
85dc74e9 | 215 | |
ed8509ed TK |
216 | cm_core: cm_core@8000 { |
217 | compatible = "ti,omap5-cm-core"; | |
218 | reg = <0x8000 0x3000>; | |
85dc74e9 | 219 | |
ed8509ed TK |
220 | cm_core_clocks: clocks { |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | }; | |
85dc74e9 | 224 | |
ed8509ed TK |
225 | cm_core_clockdomains: clockdomains { |
226 | }; | |
85dc74e9 TK |
227 | }; |
228 | }; | |
229 | ||
ed8509ed TK |
230 | l4_wkup: l4@4ae00000 { |
231 | compatible = "ti,omap5-l4-wkup", "simple-bus"; | |
232 | #address-cells = <1>; | |
233 | #size-cells = <1>; | |
234 | ranges = <0 0x4ae00000 0x2b000>; | |
85dc74e9 | 235 | |
ed8509ed TK |
236 | counter32k: counter@4000 { |
237 | compatible = "ti,omap-counter32k"; | |
238 | reg = <0x4000 0x40>; | |
239 | ti,hwmods = "counter_32k"; | |
85dc74e9 TK |
240 | }; |
241 | ||
ed8509ed TK |
242 | prm: prm@6000 { |
243 | compatible = "ti,omap5-prm"; | |
244 | reg = <0x6000 0x3000>; | |
245 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
246 | ||
247 | prm_clocks: clocks { | |
248 | #address-cells = <1>; | |
249 | #size-cells = <0>; | |
250 | }; | |
251 | ||
252 | prm_clockdomains: clockdomains { | |
253 | }; | |
85dc74e9 | 254 | }; |
85dc74e9 | 255 | |
ed8509ed TK |
256 | scrm: scrm@a000 { |
257 | compatible = "ti,omap5-scrm"; | |
258 | reg = <0xa000 0x2000>; | |
3b3132f7 | 259 | |
ed8509ed TK |
260 | scrm_clocks: clocks { |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
263 | }; | |
5da6a2d5 | 264 | |
ed8509ed TK |
265 | scrm_clockdomains: clockdomains { |
266 | }; | |
267 | }; | |
cd042fe5 | 268 | |
ed8509ed TK |
269 | omap5_pmx_wkup: pinmux@c840 { |
270 | compatible = "ti,omap5-padconf", | |
271 | "pinctrl-single"; | |
272 | reg = <0xc840 0x0038>; | |
273 | #address-cells = <1>; | |
274 | #size-cells = <0>; | |
275 | #interrupt-cells = <1>; | |
276 | interrupt-controller; | |
277 | pinctrl-single,register-width = <16>; | |
278 | pinctrl-single,function-mask = <0x7fff>; | |
cd042fe5 B |
279 | }; |
280 | }; | |
281 | ||
8b9a2810 RN |
282 | ocmcram: ocmcram@40300000 { |
283 | compatible = "mmio-sram"; | |
284 | reg = <0x40300000 0x20000>; /* 128k */ | |
285 | }; | |
286 | ||
2c2dc545 JH |
287 | sdma: dma-controller@4a056000 { |
288 | compatible = "ti,omap4430-sdma"; | |
289 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
290 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
291 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
292 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
293 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 | 294 | #dma-cells = <1>; |
951c1c04 PU |
295 | dma-channels = <32>; |
296 | dma-requests = <127>; | |
2c2dc545 JH |
297 | }; |
298 | ||
6b5de091 S |
299 | gpio1: gpio@4ae10000 { |
300 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 301 | reg = <0x4ae10000 0x200>; |
8fea7d5a | 302 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 | 303 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 304 | ti,gpio-always-on; |
6b5de091 S |
305 | gpio-controller; |
306 | #gpio-cells = <2>; | |
307 | interrupt-controller; | |
ff5c9059 | 308 | #interrupt-cells = <2>; |
6b5de091 S |
309 | }; |
310 | ||
311 | gpio2: gpio@48055000 { | |
312 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 313 | reg = <0x48055000 0x200>; |
8fea7d5a | 314 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
315 | ti,hwmods = "gpio2"; |
316 | gpio-controller; | |
317 | #gpio-cells = <2>; | |
318 | interrupt-controller; | |
ff5c9059 | 319 | #interrupt-cells = <2>; |
6b5de091 S |
320 | }; |
321 | ||
322 | gpio3: gpio@48057000 { | |
323 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 324 | reg = <0x48057000 0x200>; |
8fea7d5a | 325 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
326 | ti,hwmods = "gpio3"; |
327 | gpio-controller; | |
328 | #gpio-cells = <2>; | |
329 | interrupt-controller; | |
ff5c9059 | 330 | #interrupt-cells = <2>; |
6b5de091 S |
331 | }; |
332 | ||
333 | gpio4: gpio@48059000 { | |
334 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 335 | reg = <0x48059000 0x200>; |
8fea7d5a | 336 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
337 | ti,hwmods = "gpio4"; |
338 | gpio-controller; | |
339 | #gpio-cells = <2>; | |
340 | interrupt-controller; | |
ff5c9059 | 341 | #interrupt-cells = <2>; |
6b5de091 S |
342 | }; |
343 | ||
344 | gpio5: gpio@4805b000 { | |
345 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 346 | reg = <0x4805b000 0x200>; |
8fea7d5a | 347 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
348 | ti,hwmods = "gpio5"; |
349 | gpio-controller; | |
350 | #gpio-cells = <2>; | |
351 | interrupt-controller; | |
ff5c9059 | 352 | #interrupt-cells = <2>; |
6b5de091 S |
353 | }; |
354 | ||
355 | gpio6: gpio@4805d000 { | |
356 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 357 | reg = <0x4805d000 0x200>; |
8fea7d5a | 358 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
359 | ti,hwmods = "gpio6"; |
360 | gpio-controller; | |
361 | #gpio-cells = <2>; | |
362 | interrupt-controller; | |
ff5c9059 | 363 | #interrupt-cells = <2>; |
6b5de091 S |
364 | }; |
365 | ||
366 | gpio7: gpio@48051000 { | |
367 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 368 | reg = <0x48051000 0x200>; |
8fea7d5a | 369 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
370 | ti,hwmods = "gpio7"; |
371 | gpio-controller; | |
372 | #gpio-cells = <2>; | |
373 | interrupt-controller; | |
ff5c9059 | 374 | #interrupt-cells = <2>; |
6b5de091 S |
375 | }; |
376 | ||
377 | gpio8: gpio@48053000 { | |
378 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 379 | reg = <0x48053000 0x200>; |
8fea7d5a | 380 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
381 | ti,hwmods = "gpio8"; |
382 | gpio-controller; | |
383 | #gpio-cells = <2>; | |
384 | interrupt-controller; | |
ff5c9059 | 385 | #interrupt-cells = <2>; |
6b5de091 S |
386 | }; |
387 | ||
1c7dbb55 JH |
388 | gpmc: gpmc@50000000 { |
389 | compatible = "ti,omap4430-gpmc"; | |
390 | reg = <0x50000000 0x1000>; | |
391 | #address-cells = <2>; | |
392 | #size-cells = <1>; | |
8fea7d5a | 393 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
1c7dbb55 JH |
394 | gpmc,num-cs = <8>; |
395 | gpmc,num-waitpins = <4>; | |
396 | ti,hwmods = "gpmc"; | |
7b8b6af1 FV |
397 | clocks = <&l3_iclk_div>; |
398 | clock-names = "fck"; | |
1c7dbb55 JH |
399 | }; |
400 | ||
6e6a9a50 SP |
401 | i2c1: i2c@48070000 { |
402 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 403 | reg = <0x48070000 0x100>; |
8fea7d5a | 404 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
405 | #address-cells = <1>; |
406 | #size-cells = <0>; | |
407 | ti,hwmods = "i2c1"; | |
408 | }; | |
409 | ||
410 | i2c2: i2c@48072000 { | |
411 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 412 | reg = <0x48072000 0x100>; |
8fea7d5a | 413 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
414 | #address-cells = <1>; |
415 | #size-cells = <0>; | |
416 | ti,hwmods = "i2c2"; | |
417 | }; | |
418 | ||
419 | i2c3: i2c@48060000 { | |
420 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 421 | reg = <0x48060000 0x100>; |
8fea7d5a | 422 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
423 | #address-cells = <1>; |
424 | #size-cells = <0>; | |
425 | ti,hwmods = "i2c3"; | |
426 | }; | |
427 | ||
d7118bbd | 428 | i2c4: i2c@4807a000 { |
6e6a9a50 | 429 | compatible = "ti,omap4-i2c"; |
d7118bbd | 430 | reg = <0x4807a000 0x100>; |
8fea7d5a | 431 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
432 | #address-cells = <1>; |
433 | #size-cells = <0>; | |
434 | ti,hwmods = "i2c4"; | |
435 | }; | |
436 | ||
d7118bbd | 437 | i2c5: i2c@4807c000 { |
6e6a9a50 | 438 | compatible = "ti,omap4-i2c"; |
d7118bbd | 439 | reg = <0x4807c000 0x100>; |
8fea7d5a | 440 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
441 | #address-cells = <1>; |
442 | #size-cells = <0>; | |
443 | ti,hwmods = "i2c5"; | |
444 | }; | |
445 | ||
fe0e09e4 SA |
446 | hwspinlock: spinlock@4a0f6000 { |
447 | compatible = "ti,omap4-hwspinlock"; | |
448 | reg = <0x4a0f6000 0x1000>; | |
449 | ti,hwmods = "spinlock"; | |
34054213 | 450 | #hwlock-cells = <1>; |
fe0e09e4 SA |
451 | }; |
452 | ||
43286b11 FB |
453 | mcspi1: spi@48098000 { |
454 | compatible = "ti,omap4-mcspi"; | |
455 | reg = <0x48098000 0x200>; | |
8fea7d5a | 456 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
457 | #address-cells = <1>; |
458 | #size-cells = <0>; | |
459 | ti,hwmods = "mcspi1"; | |
460 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
461 | dmas = <&sdma 35>, |
462 | <&sdma 36>, | |
463 | <&sdma 37>, | |
464 | <&sdma 38>, | |
465 | <&sdma 39>, | |
466 | <&sdma 40>, | |
467 | <&sdma 41>, | |
468 | <&sdma 42>; | |
469 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
470 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
471 | }; |
472 | ||
473 | mcspi2: spi@4809a000 { | |
474 | compatible = "ti,omap4-mcspi"; | |
475 | reg = <0x4809a000 0x200>; | |
8fea7d5a | 476 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
477 | #address-cells = <1>; |
478 | #size-cells = <0>; | |
479 | ti,hwmods = "mcspi2"; | |
480 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
481 | dmas = <&sdma 43>, |
482 | <&sdma 44>, | |
483 | <&sdma 45>, | |
484 | <&sdma 46>; | |
485 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
486 | }; |
487 | ||
488 | mcspi3: spi@480b8000 { | |
489 | compatible = "ti,omap4-mcspi"; | |
490 | reg = <0x480b8000 0x200>; | |
8fea7d5a | 491 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
492 | #address-cells = <1>; |
493 | #size-cells = <0>; | |
494 | ti,hwmods = "mcspi3"; | |
495 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
496 | dmas = <&sdma 15>, <&sdma 16>; |
497 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
498 | }; |
499 | ||
500 | mcspi4: spi@480ba000 { | |
501 | compatible = "ti,omap4-mcspi"; | |
502 | reg = <0x480ba000 0x200>; | |
8fea7d5a | 503 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
504 | #address-cells = <1>; |
505 | #size-cells = <0>; | |
506 | ti,hwmods = "mcspi4"; | |
507 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
508 | dmas = <&sdma 70>, <&sdma 71>; |
509 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
510 | }; |
511 | ||
6b5de091 S |
512 | uart1: serial@4806a000 { |
513 | compatible = "ti,omap4-uart"; | |
8e80f660 | 514 | reg = <0x4806a000 0x100>; |
7136d457 | 515 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
516 | ti,hwmods = "uart1"; |
517 | clock-frequency = <48000000>; | |
518 | }; | |
519 | ||
520 | uart2: serial@4806c000 { | |
521 | compatible = "ti,omap4-uart"; | |
8e80f660 | 522 | reg = <0x4806c000 0x100>; |
7136d457 | 523 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
524 | ti,hwmods = "uart2"; |
525 | clock-frequency = <48000000>; | |
526 | }; | |
527 | ||
528 | uart3: serial@48020000 { | |
529 | compatible = "ti,omap4-uart"; | |
8e80f660 | 530 | reg = <0x48020000 0x100>; |
7136d457 | 531 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
532 | ti,hwmods = "uart3"; |
533 | clock-frequency = <48000000>; | |
534 | }; | |
535 | ||
536 | uart4: serial@4806e000 { | |
537 | compatible = "ti,omap4-uart"; | |
8e80f660 | 538 | reg = <0x4806e000 0x100>; |
7136d457 | 539 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
540 | ti,hwmods = "uart4"; |
541 | clock-frequency = <48000000>; | |
542 | }; | |
543 | ||
544 | uart5: serial@48066000 { | |
8e80f660 SG |
545 | compatible = "ti,omap4-uart"; |
546 | reg = <0x48066000 0x100>; | |
7136d457 | 547 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
548 | ti,hwmods = "uart5"; |
549 | clock-frequency = <48000000>; | |
550 | }; | |
551 | ||
552 | uart6: serial@48068000 { | |
8e80f660 SG |
553 | compatible = "ti,omap4-uart"; |
554 | reg = <0x48068000 0x100>; | |
7136d457 | 555 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
556 | ti,hwmods = "uart6"; |
557 | clock-frequency = <48000000>; | |
558 | }; | |
5dd18b01 B |
559 | |
560 | mmc1: mmc@4809c000 { | |
561 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 562 | reg = <0x4809c000 0x400>; |
8fea7d5a | 563 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
564 | ti,hwmods = "mmc1"; |
565 | ti,dual-volt; | |
566 | ti,needs-special-reset; | |
2c2dc545 JH |
567 | dmas = <&sdma 61>, <&sdma 62>; |
568 | dma-names = "tx", "rx"; | |
cd042fe5 | 569 | pbias-supply = <&pbias_mmc_reg>; |
5dd18b01 B |
570 | }; |
571 | ||
572 | mmc2: mmc@480b4000 { | |
573 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 574 | reg = <0x480b4000 0x400>; |
8fea7d5a | 575 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
576 | ti,hwmods = "mmc2"; |
577 | ti,needs-special-reset; | |
2c2dc545 JH |
578 | dmas = <&sdma 47>, <&sdma 48>; |
579 | dma-names = "tx", "rx"; | |
5dd18b01 B |
580 | }; |
581 | ||
582 | mmc3: mmc@480ad000 { | |
583 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 584 | reg = <0x480ad000 0x400>; |
8fea7d5a | 585 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
586 | ti,hwmods = "mmc3"; |
587 | ti,needs-special-reset; | |
2c2dc545 JH |
588 | dmas = <&sdma 77>, <&sdma 78>; |
589 | dma-names = "tx", "rx"; | |
5dd18b01 B |
590 | }; |
591 | ||
592 | mmc4: mmc@480d1000 { | |
593 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 594 | reg = <0x480d1000 0x400>; |
8fea7d5a | 595 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
596 | ti,hwmods = "mmc4"; |
597 | ti,needs-special-reset; | |
2c2dc545 JH |
598 | dmas = <&sdma 57>, <&sdma 58>; |
599 | dma-names = "tx", "rx"; | |
5dd18b01 B |
600 | }; |
601 | ||
602 | mmc5: mmc@480d5000 { | |
603 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 604 | reg = <0x480d5000 0x400>; |
8fea7d5a | 605 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
606 | ti,hwmods = "mmc5"; |
607 | ti,needs-special-reset; | |
2c2dc545 JH |
608 | dmas = <&sdma 59>, <&sdma 60>; |
609 | dma-names = "tx", "rx"; | |
5dd18b01 | 610 | }; |
5449fbc2 | 611 | |
2dcfa56e SA |
612 | mmu_dsp: mmu@4a066000 { |
613 | compatible = "ti,omap4-iommu"; | |
614 | reg = <0x4a066000 0x100>; | |
615 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
616 | ti,hwmods = "mmu_dsp"; | |
c1b5d0f6 | 617 | #iommu-cells = <0>; |
2dcfa56e SA |
618 | }; |
619 | ||
620 | mmu_ipu: mmu@55082000 { | |
621 | compatible = "ti,omap4-iommu"; | |
622 | reg = <0x55082000 0x100>; | |
623 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
624 | ti,hwmods = "mmu_ipu"; | |
c1b5d0f6 | 625 | #iommu-cells = <0>; |
2dcfa56e SA |
626 | ti,iommu-bus-err-back; |
627 | }; | |
628 | ||
5449fbc2 SP |
629 | keypad: keypad@4ae1c000 { |
630 | compatible = "ti,omap4-keypad"; | |
8cc8b89f | 631 | reg = <0x4ae1c000 0x400>; |
5449fbc2 SP |
632 | ti,hwmods = "kbd"; |
633 | }; | |
ffd5db24 | 634 | |
cbb57f07 PU |
635 | mcpdm: mcpdm@40132000 { |
636 | compatible = "ti,omap4-mcpdm"; | |
637 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
638 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
639 | reg-names = "mpu", "dma"; | |
8fea7d5a | 640 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 641 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
642 | dmas = <&sdma 65>, |
643 | <&sdma 66>; | |
644 | dma-names = "up_link", "dn_link"; | |
f15534ea | 645 | status = "disabled"; |
cbb57f07 PU |
646 | }; |
647 | ||
648 | dmic: dmic@4012e000 { | |
649 | compatible = "ti,omap4-dmic"; | |
650 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
651 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
652 | reg-names = "mpu", "dma"; | |
8fea7d5a | 653 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 654 | ti,hwmods = "dmic"; |
4e4ead73 SG |
655 | dmas = <&sdma 67>; |
656 | dma-names = "up_link"; | |
f15534ea | 657 | status = "disabled"; |
cbb57f07 PU |
658 | }; |
659 | ||
ffd5db24 PU |
660 | mcbsp1: mcbsp@40122000 { |
661 | compatible = "ti,omap4-mcbsp"; | |
662 | reg = <0x40122000 0xff>, /* MPU private access */ | |
663 | <0x49022000 0xff>; /* L3 Interconnect */ | |
664 | reg-names = "mpu", "dma"; | |
8fea7d5a | 665 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 666 | interrupt-names = "common"; |
ffd5db24 PU |
667 | ti,buffer-size = <128>; |
668 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
669 | dmas = <&sdma 33>, |
670 | <&sdma 34>; | |
671 | dma-names = "tx", "rx"; | |
f15534ea | 672 | status = "disabled"; |
ffd5db24 PU |
673 | }; |
674 | ||
675 | mcbsp2: mcbsp@40124000 { | |
676 | compatible = "ti,omap4-mcbsp"; | |
677 | reg = <0x40124000 0xff>, /* MPU private access */ | |
678 | <0x49024000 0xff>; /* L3 Interconnect */ | |
679 | reg-names = "mpu", "dma"; | |
8fea7d5a | 680 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 681 | interrupt-names = "common"; |
ffd5db24 PU |
682 | ti,buffer-size = <128>; |
683 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
684 | dmas = <&sdma 17>, |
685 | <&sdma 18>; | |
686 | dma-names = "tx", "rx"; | |
f15534ea | 687 | status = "disabled"; |
ffd5db24 PU |
688 | }; |
689 | ||
690 | mcbsp3: mcbsp@40126000 { | |
691 | compatible = "ti,omap4-mcbsp"; | |
692 | reg = <0x40126000 0xff>, /* MPU private access */ | |
693 | <0x49026000 0xff>; /* L3 Interconnect */ | |
694 | reg-names = "mpu", "dma"; | |
8fea7d5a | 695 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 696 | interrupt-names = "common"; |
ffd5db24 PU |
697 | ti,buffer-size = <128>; |
698 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
699 | dmas = <&sdma 19>, |
700 | <&sdma 20>; | |
701 | dma-names = "tx", "rx"; | |
f15534ea | 702 | status = "disabled"; |
ffd5db24 | 703 | }; |
df692a92 | 704 | |
84d89c31 SA |
705 | mailbox: mailbox@4a0f4000 { |
706 | compatible = "ti,omap4-mailbox"; | |
707 | reg = <0x4a0f4000 0x200>; | |
708 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
709 | ti,hwmods = "mailbox"; | |
24df0453 | 710 | #mbox-cells = <1>; |
41ffada1 SA |
711 | ti,mbox-num-users = <3>; |
712 | ti,mbox-num-fifos = <8>; | |
d27704d1 SA |
713 | mbox_ipu: mbox_ipu { |
714 | ti,mbox-tx = <0 0 0>; | |
715 | ti,mbox-rx = <1 0 0>; | |
716 | }; | |
717 | mbox_dsp: mbox_dsp { | |
718 | ti,mbox-tx = <3 0 0>; | |
719 | ti,mbox-rx = <2 0 0>; | |
720 | }; | |
84d89c31 SA |
721 | }; |
722 | ||
df692a92 | 723 | timer1: timer@4ae18000 { |
002e1ec5 | 724 | compatible = "ti,omap5430-timer"; |
df692a92 | 725 | reg = <0x4ae18000 0x80>; |
8fea7d5a | 726 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
727 | ti,hwmods = "timer1"; |
728 | ti,timer-alwon; | |
729 | }; | |
730 | ||
731 | timer2: timer@48032000 { | |
002e1ec5 | 732 | compatible = "ti,omap5430-timer"; |
df692a92 | 733 | reg = <0x48032000 0x80>; |
8fea7d5a | 734 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
735 | ti,hwmods = "timer2"; |
736 | }; | |
737 | ||
738 | timer3: timer@48034000 { | |
002e1ec5 | 739 | compatible = "ti,omap5430-timer"; |
df692a92 | 740 | reg = <0x48034000 0x80>; |
8fea7d5a | 741 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
742 | ti,hwmods = "timer3"; |
743 | }; | |
744 | ||
745 | timer4: timer@48036000 { | |
002e1ec5 | 746 | compatible = "ti,omap5430-timer"; |
df692a92 | 747 | reg = <0x48036000 0x80>; |
8fea7d5a | 748 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
749 | ti,hwmods = "timer4"; |
750 | }; | |
751 | ||
752 | timer5: timer@40138000 { | |
002e1ec5 | 753 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
754 | reg = <0x40138000 0x80>, |
755 | <0x49038000 0x80>; | |
8fea7d5a | 756 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
757 | ti,hwmods = "timer5"; |
758 | ti,timer-dsp; | |
8341613a | 759 | ti,timer-pwm; |
df692a92 JH |
760 | }; |
761 | ||
762 | timer6: timer@4013a000 { | |
002e1ec5 | 763 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
764 | reg = <0x4013a000 0x80>, |
765 | <0x4903a000 0x80>; | |
8fea7d5a | 766 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
767 | ti,hwmods = "timer6"; |
768 | ti,timer-dsp; | |
769 | ti,timer-pwm; | |
770 | }; | |
771 | ||
772 | timer7: timer@4013c000 { | |
002e1ec5 | 773 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
774 | reg = <0x4013c000 0x80>, |
775 | <0x4903c000 0x80>; | |
8fea7d5a | 776 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
777 | ti,hwmods = "timer7"; |
778 | ti,timer-dsp; | |
779 | }; | |
780 | ||
781 | timer8: timer@4013e000 { | |
002e1ec5 | 782 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
783 | reg = <0x4013e000 0x80>, |
784 | <0x4903e000 0x80>; | |
8fea7d5a | 785 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
786 | ti,hwmods = "timer8"; |
787 | ti,timer-dsp; | |
788 | ti,timer-pwm; | |
789 | }; | |
790 | ||
791 | timer9: timer@4803e000 { | |
002e1ec5 | 792 | compatible = "ti,omap5430-timer"; |
df692a92 | 793 | reg = <0x4803e000 0x80>; |
8fea7d5a | 794 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 795 | ti,hwmods = "timer9"; |
8341613a | 796 | ti,timer-pwm; |
df692a92 JH |
797 | }; |
798 | ||
799 | timer10: timer@48086000 { | |
002e1ec5 | 800 | compatible = "ti,omap5430-timer"; |
df692a92 | 801 | reg = <0x48086000 0x80>; |
8fea7d5a | 802 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 803 | ti,hwmods = "timer10"; |
8341613a | 804 | ti,timer-pwm; |
df692a92 JH |
805 | }; |
806 | ||
807 | timer11: timer@48088000 { | |
002e1ec5 | 808 | compatible = "ti,omap5430-timer"; |
df692a92 | 809 | reg = <0x48088000 0x80>; |
8fea7d5a | 810 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
811 | ti,hwmods = "timer11"; |
812 | ti,timer-pwm; | |
813 | }; | |
e6900ddf | 814 | |
55452197 LV |
815 | wdt2: wdt@4ae14000 { |
816 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | |
817 | reg = <0x4ae14000 0x80>; | |
8fea7d5a | 818 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
55452197 LV |
819 | ti,hwmods = "wd_timer2"; |
820 | }; | |
821 | ||
1a5fe3ca AT |
822 | dmm@4e000000 { |
823 | compatible = "ti,omap5-dmm"; | |
824 | reg = <0x4e000000 0x800>; | |
825 | interrupts = <0 113 0x4>; | |
826 | ti,hwmods = "dmm"; | |
827 | }; | |
828 | ||
8906d654 | 829 | emif1: emif@4c000000 { |
e6900ddf LV |
830 | compatible = "ti,emif-4d5"; |
831 | ti,hwmods = "emif1"; | |
f12ecbe2 | 832 | ti,no-idle-on-init; |
e6900ddf LV |
833 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
834 | reg = <0x4c000000 0x400>; | |
8fea7d5a | 835 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
836 | hw-caps-read-idle-ctrl; |
837 | hw-caps-ll-interface; | |
838 | hw-caps-temp-alert; | |
839 | }; | |
840 | ||
8906d654 | 841 | emif2: emif@4d000000 { |
e6900ddf LV |
842 | compatible = "ti,emif-4d5"; |
843 | ti,hwmods = "emif2"; | |
f12ecbe2 | 844 | ti,no-idle-on-init; |
e6900ddf LV |
845 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
846 | reg = <0x4d000000 0x400>; | |
8fea7d5a | 847 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
848 | hw-caps-read-idle-ctrl; |
849 | hw-caps-ll-interface; | |
850 | hw-caps-temp-alert; | |
851 | }; | |
fedc428e | 852 | |
b297c292 RQ |
853 | omap_control_usb2phy: control-phy@4a002300 { |
854 | compatible = "ti,control-phy-usb2"; | |
855 | reg = <0x4a002300 0x4>; | |
856 | reg-names = "power"; | |
857 | }; | |
858 | ||
859 | omap_control_usb3phy: control-phy@4a002370 { | |
860 | compatible = "ti,control-phy-pipe3"; | |
861 | reg = <0x4a002370 0x4>; | |
862 | reg-names = "power"; | |
fedc428e | 863 | }; |
e9831967 | 864 | |
e3a412c9 | 865 | usb3: omap_dwc3@4a020000 { |
72f6f957 KVA |
866 | compatible = "ti,dwc3"; |
867 | ti,hwmods = "usb_otg_ss"; | |
6f61ee23 | 868 | reg = <0x4a020000 0x10000>; |
8fea7d5a | 869 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
72f6f957 KVA |
870 | #address-cells = <1>; |
871 | #size-cells = <1>; | |
872 | utmi-mode = <2>; | |
873 | ranges; | |
874 | dwc3@4a030000 { | |
22a5aa17 | 875 | compatible = "snps,dwc3"; |
6f61ee23 | 876 | reg = <0x4a030000 0x10000>; |
8d33c093 RQ |
877 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
878 | <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, | |
879 | <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
880 | interrupt-names = "peripheral", | |
881 | "host", | |
882 | "otg"; | |
073addc8 KVA |
883 | phys = <&usb2_phy>, <&usb3_phy>; |
884 | phy-names = "usb2-phy", "usb3-phy"; | |
c47ee6ee | 885 | dr_mode = "peripheral"; |
72f6f957 KVA |
886 | tx-fifo-resize; |
887 | }; | |
888 | }; | |
889 | ||
b6731f78 | 890 | ocp2scp@4a080000 { |
e9831967 KVA |
891 | compatible = "ti,omap-ocp2scp"; |
892 | #address-cells = <1>; | |
893 | #size-cells = <1>; | |
b6731f78 | 894 | reg = <0x4a080000 0x20>; |
e9831967 KVA |
895 | ranges; |
896 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
897 | usb2_phy: usb2phy@4a084000 { |
898 | compatible = "ti,omap-usb2"; | |
899 | reg = <0x4a084000 0x7c>; | |
b297c292 | 900 | ctrl-module = <&omap_control_usb2phy>; |
c65d0ad5 RQ |
901 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
902 | clock-names = "wkupclk", "refclk"; | |
073addc8 | 903 | #phy-cells = <0>; |
ae6a32d2 KVA |
904 | }; |
905 | ||
906 | usb3_phy: usb3phy@4a084400 { | |
907 | compatible = "ti,omap-usb3"; | |
908 | reg = <0x4a084400 0x80>, | |
909 | <0x4a084800 0x64>, | |
910 | <0x4a084c00 0x40>; | |
911 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
b297c292 | 912 | ctrl-module = <&omap_control_usb3phy>; |
ada76576 RQ |
913 | clocks = <&usb_phy_cm_clk32k>, |
914 | <&sys_clkin>, | |
915 | <&usb_otg_ss_refclk960m>; | |
916 | clock-names = "wkupclk", | |
917 | "sysclk", | |
918 | "refclk"; | |
073addc8 | 919 | #phy-cells = <0>; |
ae6a32d2 | 920 | }; |
e9831967 | 921 | }; |
ed7f8e8a RQ |
922 | |
923 | usbhstll: usbhstll@4a062000 { | |
924 | compatible = "ti,usbhs-tll"; | |
925 | reg = <0x4a062000 0x1000>; | |
926 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
927 | ti,hwmods = "usb_tll_hs"; | |
928 | }; | |
929 | ||
930 | usbhshost: usbhshost@4a064000 { | |
931 | compatible = "ti,usbhs-host"; | |
932 | reg = <0x4a064000 0x800>; | |
933 | ti,hwmods = "usb_host_hs"; | |
934 | #address-cells = <1>; | |
935 | #size-cells = <1>; | |
936 | ranges; | |
051fc06d RQ |
937 | clocks = <&l3init_60m_fclk>, |
938 | <&xclk60mhsp1_ck>, | |
939 | <&xclk60mhsp2_ck>; | |
940 | clock-names = "refclk_60m_int", | |
941 | "refclk_60m_ext_p1", | |
942 | "refclk_60m_ext_p2"; | |
ed7f8e8a RQ |
943 | |
944 | usbhsohci: ohci@4a064800 { | |
a2525e54 | 945 | compatible = "ti,ohci-omap3"; |
ed7f8e8a | 946 | reg = <0x4a064800 0x400>; |
ed7f8e8a RQ |
947 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
948 | }; | |
949 | ||
950 | usbhsehci: ehci@4a064c00 { | |
a2525e54 | 951 | compatible = "ti,ehci-omap"; |
ed7f8e8a | 952 | reg = <0x4a064c00 0x400>; |
ed7f8e8a RQ |
953 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
954 | }; | |
955 | }; | |
cbad26db | 956 | |
1b761fc5 | 957 | bandgap: bandgap@4a0021e0 { |
cbad26db EV |
958 | reg = <0x4a0021e0 0xc |
959 | 0x4a00232c 0xc | |
960 | 0x4a002380 0x2c | |
961 | 0x4a0023C0 0x3c>; | |
962 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
963 | compatible = "ti,omap5430-bandgap"; | |
1b761fc5 EV |
964 | |
965 | #thermal-sensor-cells = <1>; | |
cbad26db | 966 | }; |
4f82952c B |
967 | |
968 | omap_control_sata: control-phy@4a002374 { | |
969 | compatible = "ti,control-phy-pipe3"; | |
970 | reg = <0x4a002374 0x4>; | |
971 | reg-names = "power"; | |
972 | clocks = <&sys_clkin>; | |
973 | clock-names = "sysclk"; | |
974 | }; | |
975 | ||
976 | /* OCP2SCP3 */ | |
977 | ocp2scp@4a090000 { | |
978 | compatible = "ti,omap-ocp2scp"; | |
979 | #address-cells = <1>; | |
980 | #size-cells = <1>; | |
981 | reg = <0x4a090000 0x20>; | |
982 | ranges; | |
983 | ti,hwmods = "ocp2scp3"; | |
984 | sata_phy: phy@4a096000 { | |
985 | compatible = "ti,phy-pipe3-sata"; | |
986 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
987 | <0x4A096400 0x64>, /* phy_tx */ | |
988 | <0x4A096800 0x40>; /* pll_ctrl */ | |
989 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
990 | ctrl-module = <&omap_control_sata>; | |
a0182724 RQ |
991 | clocks = <&sys_clkin>, <&sata_ref_clk>; |
992 | clock-names = "sysclk", "refclk"; | |
4f82952c B |
993 | #phy-cells = <0>; |
994 | }; | |
995 | }; | |
996 | ||
997 | sata: sata@4a141100 { | |
998 | compatible = "snps,dwc-ahci"; | |
999 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
1000 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
1001 | phys = <&sata_phy>; | |
1002 | phy-names = "sata-phy"; | |
1003 | clocks = <&sata_ref_clk>; | |
1004 | ti,hwmods = "sata"; | |
1005 | }; | |
1006 | ||
e7585c4f TV |
1007 | dss: dss@58000000 { |
1008 | compatible = "ti,omap5-dss"; | |
1009 | reg = <0x58000000 0x80>; | |
1010 | status = "disabled"; | |
1011 | ti,hwmods = "dss_core"; | |
1012 | clocks = <&dss_dss_clk>; | |
1013 | clock-names = "fck"; | |
1014 | #address-cells = <1>; | |
1015 | #size-cells = <1>; | |
1016 | ranges; | |
1017 | ||
1018 | dispc@58001000 { | |
1019 | compatible = "ti,omap5-dispc"; | |
1020 | reg = <0x58001000 0x1000>; | |
1021 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
1022 | ti,hwmods = "dss_dispc"; | |
1023 | clocks = <&dss_dss_clk>; | |
1024 | clock-names = "fck"; | |
1025 | }; | |
1026 | ||
84ace674 TV |
1027 | rfbi: encoder@58002000 { |
1028 | compatible = "ti,omap5-rfbi"; | |
1029 | reg = <0x58002000 0x100>; | |
1030 | status = "disabled"; | |
1031 | ti,hwmods = "dss_rfbi"; | |
1032 | clocks = <&dss_dss_clk>, <&l3_iclk_div>; | |
1033 | clock-names = "fck", "ick"; | |
1034 | }; | |
1035 | ||
e7585c4f TV |
1036 | dsi1: encoder@58004000 { |
1037 | compatible = "ti,omap5-dsi"; | |
1038 | reg = <0x58004000 0x200>, | |
1039 | <0x58004200 0x40>, | |
1040 | <0x58004300 0x40>; | |
1041 | reg-names = "proto", "phy", "pll"; | |
1042 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
1043 | status = "disabled"; | |
1044 | ti,hwmods = "dss_dsi1"; | |
1045 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1046 | clock-names = "fck", "sys_clk"; | |
1047 | }; | |
1048 | ||
1049 | dsi2: encoder@58005000 { | |
1050 | compatible = "ti,omap5-dsi"; | |
1051 | reg = <0x58009000 0x200>, | |
1052 | <0x58009200 0x40>, | |
1053 | <0x58009300 0x40>; | |
1054 | reg-names = "proto", "phy", "pll"; | |
1055 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
1056 | status = "disabled"; | |
1057 | ti,hwmods = "dss_dsi2"; | |
1058 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1059 | clock-names = "fck", "sys_clk"; | |
1060 | }; | |
1061 | ||
1062 | hdmi: encoder@58060000 { | |
1063 | compatible = "ti,omap5-hdmi"; | |
1064 | reg = <0x58040000 0x200>, | |
1065 | <0x58040200 0x80>, | |
1066 | <0x58040300 0x80>, | |
1067 | <0x58060000 0x19000>; | |
1068 | reg-names = "wp", "pll", "phy", "core"; | |
1069 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1070 | status = "disabled"; | |
1071 | ti,hwmods = "dss_hdmi"; | |
1072 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; | |
1073 | clock-names = "fck", "sys_clk"; | |
7d0fde39 JS |
1074 | dmas = <&sdma 76>; |
1075 | dma-names = "audio_tx"; | |
e7585c4f TV |
1076 | }; |
1077 | }; | |
07b9b3d9 AT |
1078 | |
1079 | abb_mpu: regulator-abb-mpu { | |
1080 | compatible = "ti,abb-v2"; | |
1081 | regulator-name = "abb_mpu"; | |
1082 | #address-cells = <0>; | |
1083 | #size-cells = <0>; | |
1084 | clocks = <&sys_clkin>; | |
1085 | ti,settling-time = <50>; | |
1086 | ti,clock-cycles = <16>; | |
1087 | ||
1088 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, | |
1089 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; | |
1090 | reg-names = "base-address", "int-address", | |
1091 | "efuse-address", "ldo-address"; | |
1092 | ti,tranxdone-status-mask = <0x80>; | |
1093 | /* LDOVBBMPU_MUX_CTRL */ | |
1094 | ti,ldovbb-override-mask = <0x400>; | |
1095 | /* LDOVBBMPU_VSET_OUT */ | |
1096 | ti,ldovbb-vset-mask = <0x1F>; | |
1097 | ||
1098 | /* | |
1099 | * NOTE: only FBB mode used but actual vset will | |
1100 | * determine final biasing | |
1101 | */ | |
1102 | ti,abb_info = < | |
1103 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1104 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
1105 | 1250000 0 0x4 0 0x02000000 0x01F00000 | |
1106 | >; | |
1107 | }; | |
1108 | ||
1109 | abb_mm: regulator-abb-mm { | |
1110 | compatible = "ti,abb-v2"; | |
1111 | regulator-name = "abb_mm"; | |
1112 | #address-cells = <0>; | |
1113 | #size-cells = <0>; | |
1114 | clocks = <&sys_clkin>; | |
1115 | ti,settling-time = <50>; | |
1116 | ti,clock-cycles = <16>; | |
1117 | ||
1118 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, | |
1119 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; | |
1120 | reg-names = "base-address", "int-address", | |
1121 | "efuse-address", "ldo-address"; | |
1122 | ti,tranxdone-status-mask = <0x80000000>; | |
1123 | /* LDOVBBMM_MUX_CTRL */ | |
1124 | ti,ldovbb-override-mask = <0x400>; | |
1125 | /* LDOVBBMM_VSET_OUT */ | |
1126 | ti,ldovbb-vset-mask = <0x1F>; | |
1127 | ||
1128 | /* | |
1129 | * NOTE: only FBB mode used but actual vset will | |
1130 | * determine final biasing | |
1131 | */ | |
1132 | ti,abb_info = < | |
1133 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1134 | 1025000 0 0x0 0 0x02000000 0x01F00000 | |
1135 | 1120000 0 0x4 0 0x02000000 0x01F00000 | |
1136 | >; | |
1137 | }; | |
6b5de091 S |
1138 | }; |
1139 | }; | |
85dc74e9 | 1140 | |
38f5c8ba TK |
1141 | &cpu_thermal { |
1142 | polling-delay = <500>; /* milliseconds */ | |
1143 | }; | |
1144 | ||
85dc74e9 | 1145 | /include/ "omap54xx-clocks.dtsi" |