Commit | Line | Data |
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6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Carveout for multimedia usecases | |
12 | * It should be the last 48MB of the first 512MB memory part | |
13 | * In theory, it should not even exist. That zone should be reserved | |
14 | * dynamically during the .reserve callback. | |
15 | */ | |
16 | /memreserve/ 0x9d000000 0x03000000; | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | compatible = "ti,omap5"; | |
22 | interrupt-parent = <&gic>; | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart1; | |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
29 | serial4 = &uart5; | |
30 | serial5 = &uart6; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | cpu@0 { | |
35 | compatible = "arm,cortex-a15"; | |
36 | }; | |
37 | cpu@1 { | |
38 | compatible = "arm,cortex-a15"; | |
39 | }; | |
40 | }; | |
41 | ||
b45ccc4e SS |
42 | timer { |
43 | compatible = "arm,armv7-timer"; | |
1496c15b RN |
44 | /* PPI secure/nonsecure IRQ, active low level-sensitive */ |
45 | interrupts = <1 13 0x308>, | |
46 | <1 14 0x308>; | |
b45ccc4e SS |
47 | clock-frequency = <6144000>; |
48 | }; | |
49 | ||
6b5de091 S |
50 | /* |
51 | * The soc node represents the soc top level view. It is uses for IPs | |
52 | * that are not memory mapped in the MPU view or for the MPU itself. | |
53 | */ | |
54 | soc { | |
55 | compatible = "ti,omap-infra"; | |
56 | mpu { | |
57 | compatible = "ti,omap5-mpu"; | |
58 | ti,hwmods = "mpu"; | |
59 | }; | |
60 | }; | |
61 | ||
62 | /* | |
63 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
64 | * The real OMAP interconnect network is quite complex. | |
65 | * Since that will not bring real advantage to represent that in DT for | |
66 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
67 | * hierarchy. | |
68 | */ | |
69 | ocp { | |
70 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
75 | ||
3b3132f7 JH |
76 | counter32k: counter@4ae04000 { |
77 | compatible = "ti,omap-counter32k"; | |
78 | reg = <0x4ae04000 0x40>; | |
79 | ti,hwmods = "counter_32k"; | |
80 | }; | |
81 | ||
5da6a2d5 PU |
82 | omap5_pmx_core: pinmux@4a002840 { |
83 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
84 | reg = <0x4a002840 0x01b6>; | |
85 | #address-cells = <1>; | |
86 | #size-cells = <0>; | |
87 | pinctrl-single,register-width = <16>; | |
88 | pinctrl-single,function-mask = <0x7fff>; | |
89 | }; | |
90 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
91 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
92 | reg = <0x4ae0c840 0x0038>; | |
93 | #address-cells = <1>; | |
94 | #size-cells = <0>; | |
95 | pinctrl-single,register-width = <16>; | |
96 | pinctrl-single,function-mask = <0x7fff>; | |
97 | }; | |
98 | ||
6b5de091 S |
99 | gic: interrupt-controller@48211000 { |
100 | compatible = "arm,cortex-a15-gic"; | |
101 | interrupt-controller; | |
102 | #interrupt-cells = <3>; | |
103 | reg = <0x48211000 0x1000>, | |
104 | <0x48212000 0x1000>; | |
105 | }; | |
106 | ||
2c2dc545 JH |
107 | sdma: dma-controller@4a056000 { |
108 | compatible = "ti,omap4430-sdma"; | |
109 | reg = <0x4a056000 0x1000>; | |
110 | interrupts = <0 12 0x4>, | |
111 | <0 13 0x4>, | |
112 | <0 14 0x4>, | |
113 | <0 15 0x4>; | |
114 | #dma-cells = <1>; | |
115 | #dma-channels = <32>; | |
116 | #dma-requests = <127>; | |
117 | }; | |
118 | ||
6b5de091 S |
119 | gpio1: gpio@4ae10000 { |
120 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
121 | reg = <0x4ae10000 0x200>; |
122 | interrupts = <0 29 0x4>; | |
6b5de091 S |
123 | ti,hwmods = "gpio1"; |
124 | gpio-controller; | |
125 | #gpio-cells = <2>; | |
126 | interrupt-controller; | |
ff5c9059 | 127 | #interrupt-cells = <2>; |
6b5de091 S |
128 | }; |
129 | ||
130 | gpio2: gpio@48055000 { | |
131 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
132 | reg = <0x48055000 0x200>; |
133 | interrupts = <0 30 0x4>; | |
6b5de091 S |
134 | ti,hwmods = "gpio2"; |
135 | gpio-controller; | |
136 | #gpio-cells = <2>; | |
137 | interrupt-controller; | |
ff5c9059 | 138 | #interrupt-cells = <2>; |
6b5de091 S |
139 | }; |
140 | ||
141 | gpio3: gpio@48057000 { | |
142 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
143 | reg = <0x48057000 0x200>; |
144 | interrupts = <0 31 0x4>; | |
6b5de091 S |
145 | ti,hwmods = "gpio3"; |
146 | gpio-controller; | |
147 | #gpio-cells = <2>; | |
148 | interrupt-controller; | |
ff5c9059 | 149 | #interrupt-cells = <2>; |
6b5de091 S |
150 | }; |
151 | ||
152 | gpio4: gpio@48059000 { | |
153 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
154 | reg = <0x48059000 0x200>; |
155 | interrupts = <0 32 0x4>; | |
6b5de091 S |
156 | ti,hwmods = "gpio4"; |
157 | gpio-controller; | |
158 | #gpio-cells = <2>; | |
159 | interrupt-controller; | |
ff5c9059 | 160 | #interrupt-cells = <2>; |
6b5de091 S |
161 | }; |
162 | ||
163 | gpio5: gpio@4805b000 { | |
164 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
165 | reg = <0x4805b000 0x200>; |
166 | interrupts = <0 33 0x4>; | |
6b5de091 S |
167 | ti,hwmods = "gpio5"; |
168 | gpio-controller; | |
169 | #gpio-cells = <2>; | |
170 | interrupt-controller; | |
ff5c9059 | 171 | #interrupt-cells = <2>; |
6b5de091 S |
172 | }; |
173 | ||
174 | gpio6: gpio@4805d000 { | |
175 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
176 | reg = <0x4805d000 0x200>; |
177 | interrupts = <0 34 0x4>; | |
6b5de091 S |
178 | ti,hwmods = "gpio6"; |
179 | gpio-controller; | |
180 | #gpio-cells = <2>; | |
181 | interrupt-controller; | |
ff5c9059 | 182 | #interrupt-cells = <2>; |
6b5de091 S |
183 | }; |
184 | ||
185 | gpio7: gpio@48051000 { | |
186 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
187 | reg = <0x48051000 0x200>; |
188 | interrupts = <0 35 0x4>; | |
6b5de091 S |
189 | ti,hwmods = "gpio7"; |
190 | gpio-controller; | |
191 | #gpio-cells = <2>; | |
192 | interrupt-controller; | |
ff5c9059 | 193 | #interrupt-cells = <2>; |
6b5de091 S |
194 | }; |
195 | ||
196 | gpio8: gpio@48053000 { | |
197 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
198 | reg = <0x48053000 0x200>; |
199 | interrupts = <0 121 0x4>; | |
6b5de091 S |
200 | ti,hwmods = "gpio8"; |
201 | gpio-controller; | |
202 | #gpio-cells = <2>; | |
203 | interrupt-controller; | |
ff5c9059 | 204 | #interrupt-cells = <2>; |
6b5de091 S |
205 | }; |
206 | ||
1c7dbb55 JH |
207 | gpmc: gpmc@50000000 { |
208 | compatible = "ti,omap4430-gpmc"; | |
209 | reg = <0x50000000 0x1000>; | |
210 | #address-cells = <2>; | |
211 | #size-cells = <1>; | |
212 | interrupts = <0 20 0x4>; | |
213 | gpmc,num-cs = <8>; | |
214 | gpmc,num-waitpins = <4>; | |
215 | ti,hwmods = "gpmc"; | |
216 | }; | |
217 | ||
6e6a9a50 SP |
218 | i2c1: i2c@48070000 { |
219 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
220 | reg = <0x48070000 0x100>; |
221 | interrupts = <0 56 0x4>; | |
6e6a9a50 SP |
222 | #address-cells = <1>; |
223 | #size-cells = <0>; | |
224 | ti,hwmods = "i2c1"; | |
225 | }; | |
226 | ||
227 | i2c2: i2c@48072000 { | |
228 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
229 | reg = <0x48072000 0x100>; |
230 | interrupts = <0 57 0x4>; | |
6e6a9a50 SP |
231 | #address-cells = <1>; |
232 | #size-cells = <0>; | |
233 | ti,hwmods = "i2c2"; | |
234 | }; | |
235 | ||
236 | i2c3: i2c@48060000 { | |
237 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
238 | reg = <0x48060000 0x100>; |
239 | interrupts = <0 61 0x4>; | |
6e6a9a50 SP |
240 | #address-cells = <1>; |
241 | #size-cells = <0>; | |
242 | ti,hwmods = "i2c3"; | |
243 | }; | |
244 | ||
d7118bbd | 245 | i2c4: i2c@4807a000 { |
6e6a9a50 | 246 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
247 | reg = <0x4807a000 0x100>; |
248 | interrupts = <0 62 0x4>; | |
6e6a9a50 SP |
249 | #address-cells = <1>; |
250 | #size-cells = <0>; | |
251 | ti,hwmods = "i2c4"; | |
252 | }; | |
253 | ||
d7118bbd | 254 | i2c5: i2c@4807c000 { |
6e6a9a50 | 255 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
256 | reg = <0x4807c000 0x100>; |
257 | interrupts = <0 60 0x4>; | |
6e6a9a50 SP |
258 | #address-cells = <1>; |
259 | #size-cells = <0>; | |
260 | ti,hwmods = "i2c5"; | |
261 | }; | |
262 | ||
43286b11 FB |
263 | mcspi1: spi@48098000 { |
264 | compatible = "ti,omap4-mcspi"; | |
265 | reg = <0x48098000 0x200>; | |
266 | interrupts = <0 65 0x4>; | |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | ti,hwmods = "mcspi1"; | |
270 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
271 | dmas = <&sdma 35>, |
272 | <&sdma 36>, | |
273 | <&sdma 37>, | |
274 | <&sdma 38>, | |
275 | <&sdma 39>, | |
276 | <&sdma 40>, | |
277 | <&sdma 41>, | |
278 | <&sdma 42>; | |
279 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
280 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
281 | }; |
282 | ||
283 | mcspi2: spi@4809a000 { | |
284 | compatible = "ti,omap4-mcspi"; | |
285 | reg = <0x4809a000 0x200>; | |
286 | interrupts = <0 66 0x4>; | |
287 | #address-cells = <1>; | |
288 | #size-cells = <0>; | |
289 | ti,hwmods = "mcspi2"; | |
290 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
291 | dmas = <&sdma 43>, |
292 | <&sdma 44>, | |
293 | <&sdma 45>, | |
294 | <&sdma 46>; | |
295 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
296 | }; |
297 | ||
298 | mcspi3: spi@480b8000 { | |
299 | compatible = "ti,omap4-mcspi"; | |
300 | reg = <0x480b8000 0x200>; | |
301 | interrupts = <0 91 0x4>; | |
302 | #address-cells = <1>; | |
303 | #size-cells = <0>; | |
304 | ti,hwmods = "mcspi3"; | |
305 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
306 | dmas = <&sdma 15>, <&sdma 16>; |
307 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
308 | }; |
309 | ||
310 | mcspi4: spi@480ba000 { | |
311 | compatible = "ti,omap4-mcspi"; | |
312 | reg = <0x480ba000 0x200>; | |
313 | interrupts = <0 48 0x4>; | |
314 | #address-cells = <1>; | |
315 | #size-cells = <0>; | |
316 | ti,hwmods = "mcspi4"; | |
317 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
318 | dmas = <&sdma 70>, <&sdma 71>; |
319 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
320 | }; |
321 | ||
6b5de091 S |
322 | uart1: serial@4806a000 { |
323 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
324 | reg = <0x4806a000 0x100>; |
325 | interrupts = <0 72 0x4>; | |
6b5de091 S |
326 | ti,hwmods = "uart1"; |
327 | clock-frequency = <48000000>; | |
328 | }; | |
329 | ||
330 | uart2: serial@4806c000 { | |
331 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
332 | reg = <0x4806c000 0x100>; |
333 | interrupts = <0 73 0x4>; | |
6b5de091 S |
334 | ti,hwmods = "uart2"; |
335 | clock-frequency = <48000000>; | |
336 | }; | |
337 | ||
338 | uart3: serial@48020000 { | |
339 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
340 | reg = <0x48020000 0x100>; |
341 | interrupts = <0 74 0x4>; | |
6b5de091 S |
342 | ti,hwmods = "uart3"; |
343 | clock-frequency = <48000000>; | |
344 | }; | |
345 | ||
346 | uart4: serial@4806e000 { | |
347 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
348 | reg = <0x4806e000 0x100>; |
349 | interrupts = <0 70 0x4>; | |
6b5de091 S |
350 | ti,hwmods = "uart4"; |
351 | clock-frequency = <48000000>; | |
352 | }; | |
353 | ||
354 | uart5: serial@48066000 { | |
8e80f660 SG |
355 | compatible = "ti,omap4-uart"; |
356 | reg = <0x48066000 0x100>; | |
357 | interrupts = <0 105 0x4>; | |
6b5de091 S |
358 | ti,hwmods = "uart5"; |
359 | clock-frequency = <48000000>; | |
360 | }; | |
361 | ||
362 | uart6: serial@48068000 { | |
8e80f660 SG |
363 | compatible = "ti,omap4-uart"; |
364 | reg = <0x48068000 0x100>; | |
365 | interrupts = <0 106 0x4>; | |
6b5de091 S |
366 | ti,hwmods = "uart6"; |
367 | clock-frequency = <48000000>; | |
368 | }; | |
5dd18b01 B |
369 | |
370 | mmc1: mmc@4809c000 { | |
371 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
372 | reg = <0x4809c000 0x400>; |
373 | interrupts = <0 83 0x4>; | |
5dd18b01 B |
374 | ti,hwmods = "mmc1"; |
375 | ti,dual-volt; | |
376 | ti,needs-special-reset; | |
2c2dc545 JH |
377 | dmas = <&sdma 61>, <&sdma 62>; |
378 | dma-names = "tx", "rx"; | |
5dd18b01 B |
379 | }; |
380 | ||
381 | mmc2: mmc@480b4000 { | |
382 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
383 | reg = <0x480b4000 0x400>; |
384 | interrupts = <0 86 0x4>; | |
5dd18b01 B |
385 | ti,hwmods = "mmc2"; |
386 | ti,needs-special-reset; | |
2c2dc545 JH |
387 | dmas = <&sdma 47>, <&sdma 48>; |
388 | dma-names = "tx", "rx"; | |
5dd18b01 B |
389 | }; |
390 | ||
391 | mmc3: mmc@480ad000 { | |
392 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
393 | reg = <0x480ad000 0x400>; |
394 | interrupts = <0 94 0x4>; | |
5dd18b01 B |
395 | ti,hwmods = "mmc3"; |
396 | ti,needs-special-reset; | |
2c2dc545 JH |
397 | dmas = <&sdma 77>, <&sdma 78>; |
398 | dma-names = "tx", "rx"; | |
5dd18b01 B |
399 | }; |
400 | ||
401 | mmc4: mmc@480d1000 { | |
402 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
403 | reg = <0x480d1000 0x400>; |
404 | interrupts = <0 96 0x4>; | |
5dd18b01 B |
405 | ti,hwmods = "mmc4"; |
406 | ti,needs-special-reset; | |
2c2dc545 JH |
407 | dmas = <&sdma 57>, <&sdma 58>; |
408 | dma-names = "tx", "rx"; | |
5dd18b01 B |
409 | }; |
410 | ||
411 | mmc5: mmc@480d5000 { | |
412 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
413 | reg = <0x480d5000 0x400>; |
414 | interrupts = <0 59 0x4>; | |
5dd18b01 B |
415 | ti,hwmods = "mmc5"; |
416 | ti,needs-special-reset; | |
2c2dc545 JH |
417 | dmas = <&sdma 59>, <&sdma 60>; |
418 | dma-names = "tx", "rx"; | |
5dd18b01 | 419 | }; |
5449fbc2 SP |
420 | |
421 | keypad: keypad@4ae1c000 { | |
422 | compatible = "ti,omap4-keypad"; | |
423 | ti,hwmods = "kbd"; | |
424 | }; | |
ffd5db24 | 425 | |
cbb57f07 PU |
426 | mcpdm: mcpdm@40132000 { |
427 | compatible = "ti,omap4-mcpdm"; | |
428 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
429 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
430 | reg-names = "mpu", "dma"; | |
431 | interrupts = <0 112 0x4>; | |
cbb57f07 | 432 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
433 | dmas = <&sdma 65>, |
434 | <&sdma 66>; | |
435 | dma-names = "up_link", "dn_link"; | |
cbb57f07 PU |
436 | }; |
437 | ||
438 | dmic: dmic@4012e000 { | |
439 | compatible = "ti,omap4-dmic"; | |
440 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
441 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
442 | reg-names = "mpu", "dma"; | |
443 | interrupts = <0 114 0x4>; | |
cbb57f07 | 444 | ti,hwmods = "dmic"; |
4e4ead73 SG |
445 | dmas = <&sdma 67>; |
446 | dma-names = "up_link"; | |
cbb57f07 PU |
447 | }; |
448 | ||
ffd5db24 PU |
449 | mcbsp1: mcbsp@40122000 { |
450 | compatible = "ti,omap4-mcbsp"; | |
451 | reg = <0x40122000 0xff>, /* MPU private access */ | |
452 | <0x49022000 0xff>; /* L3 Interconnect */ | |
453 | reg-names = "mpu", "dma"; | |
454 | interrupts = <0 17 0x4>; | |
455 | interrupt-names = "common"; | |
ffd5db24 PU |
456 | ti,buffer-size = <128>; |
457 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
458 | dmas = <&sdma 33>, |
459 | <&sdma 34>; | |
460 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
461 | }; |
462 | ||
463 | mcbsp2: mcbsp@40124000 { | |
464 | compatible = "ti,omap4-mcbsp"; | |
465 | reg = <0x40124000 0xff>, /* MPU private access */ | |
466 | <0x49024000 0xff>; /* L3 Interconnect */ | |
467 | reg-names = "mpu", "dma"; | |
468 | interrupts = <0 22 0x4>; | |
469 | interrupt-names = "common"; | |
ffd5db24 PU |
470 | ti,buffer-size = <128>; |
471 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
472 | dmas = <&sdma 17>, |
473 | <&sdma 18>; | |
474 | dma-names = "tx", "rx"; | |
ffd5db24 PU |
475 | }; |
476 | ||
477 | mcbsp3: mcbsp@40126000 { | |
478 | compatible = "ti,omap4-mcbsp"; | |
479 | reg = <0x40126000 0xff>, /* MPU private access */ | |
480 | <0x49026000 0xff>; /* L3 Interconnect */ | |
481 | reg-names = "mpu", "dma"; | |
482 | interrupts = <0 23 0x4>; | |
483 | interrupt-names = "common"; | |
ffd5db24 PU |
484 | ti,buffer-size = <128>; |
485 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
486 | dmas = <&sdma 19>, |
487 | <&sdma 20>; | |
488 | dma-names = "tx", "rx"; | |
ffd5db24 | 489 | }; |
df692a92 JH |
490 | |
491 | timer1: timer@4ae18000 { | |
492 | compatible = "ti,omap2-timer"; | |
493 | reg = <0x4ae18000 0x80>; | |
494 | interrupts = <0 37 0x4>; | |
495 | ti,hwmods = "timer1"; | |
496 | ti,timer-alwon; | |
497 | }; | |
498 | ||
499 | timer2: timer@48032000 { | |
500 | compatible = "ti,omap2-timer"; | |
501 | reg = <0x48032000 0x80>; | |
502 | interrupts = <0 38 0x4>; | |
503 | ti,hwmods = "timer2"; | |
504 | }; | |
505 | ||
506 | timer3: timer@48034000 { | |
507 | compatible = "ti,omap2-timer"; | |
508 | reg = <0x48034000 0x80>; | |
509 | interrupts = <0 39 0x4>; | |
510 | ti,hwmods = "timer3"; | |
511 | }; | |
512 | ||
513 | timer4: timer@48036000 { | |
514 | compatible = "ti,omap2-timer"; | |
515 | reg = <0x48036000 0x80>; | |
516 | interrupts = <0 40 0x4>; | |
517 | ti,hwmods = "timer4"; | |
518 | }; | |
519 | ||
520 | timer5: timer@40138000 { | |
521 | compatible = "ti,omap2-timer"; | |
522 | reg = <0x40138000 0x80>, | |
523 | <0x49038000 0x80>; | |
524 | interrupts = <0 41 0x4>; | |
525 | ti,hwmods = "timer5"; | |
526 | ti,timer-dsp; | |
527 | }; | |
528 | ||
529 | timer6: timer@4013a000 { | |
530 | compatible = "ti,omap2-timer"; | |
531 | reg = <0x4013a000 0x80>, | |
532 | <0x4903a000 0x80>; | |
533 | interrupts = <0 42 0x4>; | |
534 | ti,hwmods = "timer6"; | |
535 | ti,timer-dsp; | |
536 | ti,timer-pwm; | |
537 | }; | |
538 | ||
539 | timer7: timer@4013c000 { | |
540 | compatible = "ti,omap2-timer"; | |
541 | reg = <0x4013c000 0x80>, | |
542 | <0x4903c000 0x80>; | |
543 | interrupts = <0 43 0x4>; | |
544 | ti,hwmods = "timer7"; | |
545 | ti,timer-dsp; | |
546 | }; | |
547 | ||
548 | timer8: timer@4013e000 { | |
549 | compatible = "ti,omap2-timer"; | |
550 | reg = <0x4013e000 0x80>, | |
551 | <0x4903e000 0x80>; | |
552 | interrupts = <0 44 0x4>; | |
553 | ti,hwmods = "timer8"; | |
554 | ti,timer-dsp; | |
555 | ti,timer-pwm; | |
556 | }; | |
557 | ||
558 | timer9: timer@4803e000 { | |
559 | compatible = "ti,omap2-timer"; | |
560 | reg = <0x4803e000 0x80>; | |
561 | interrupts = <0 45 0x4>; | |
562 | ti,hwmods = "timer9"; | |
563 | }; | |
564 | ||
565 | timer10: timer@48086000 { | |
566 | compatible = "ti,omap2-timer"; | |
567 | reg = <0x48086000 0x80>; | |
568 | interrupts = <0 46 0x4>; | |
569 | ti,hwmods = "timer10"; | |
570 | }; | |
571 | ||
572 | timer11: timer@48088000 { | |
573 | compatible = "ti,omap2-timer"; | |
574 | reg = <0x48088000 0x80>; | |
575 | interrupts = <0 47 0x4>; | |
576 | ti,hwmods = "timer11"; | |
577 | ti,timer-pwm; | |
578 | }; | |
e6900ddf LV |
579 | |
580 | emif1: emif@0x4c000000 { | |
581 | compatible = "ti,emif-4d5"; | |
582 | ti,hwmods = "emif1"; | |
583 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
584 | reg = <0x4c000000 0x400>; | |
585 | interrupts = <0 110 0x4>; | |
586 | hw-caps-read-idle-ctrl; | |
587 | hw-caps-ll-interface; | |
588 | hw-caps-temp-alert; | |
589 | }; | |
590 | ||
591 | emif2: emif@0x4d000000 { | |
592 | compatible = "ti,emif-4d5"; | |
593 | ti,hwmods = "emif2"; | |
594 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
595 | reg = <0x4d000000 0x400>; | |
596 | interrupts = <0 111 0x4>; | |
597 | hw-caps-read-idle-ctrl; | |
598 | hw-caps-ll-interface; | |
599 | hw-caps-temp-alert; | |
600 | }; | |
fedc428e KVA |
601 | |
602 | omap_control_usb: omap-control-usb@4a002300 { | |
603 | compatible = "ti,omap-control-usb"; | |
604 | reg = <0x4a002300 0x4>, | |
605 | <0x4a002370 0x4>; | |
606 | reg-names = "control_dev_conf", "phy_power_usb"; | |
607 | ti,type = <2>; | |
608 | }; | |
e9831967 | 609 | |
72f6f957 KVA |
610 | omap_dwc3@4a020000 { |
611 | compatible = "ti,dwc3"; | |
612 | ti,hwmods = "usb_otg_ss"; | |
613 | reg = <0x4a020000 0x1000>; | |
614 | interrupts = <0 93 4>; | |
615 | #address-cells = <1>; | |
616 | #size-cells = <1>; | |
617 | utmi-mode = <2>; | |
618 | ranges; | |
619 | dwc3@4a030000 { | |
620 | compatible = "synopsys,dwc3"; | |
621 | reg = <0x4a030000 0x1000>; | |
622 | interrupts = <0 92 4>; | |
623 | usb-phy = <&usb2_phy>, <&usb3_phy>; | |
624 | tx-fifo-resize; | |
625 | }; | |
626 | }; | |
627 | ||
e9831967 KVA |
628 | ocp2scp { |
629 | compatible = "ti,omap-ocp2scp"; | |
630 | #address-cells = <1>; | |
631 | #size-cells = <1>; | |
632 | ranges; | |
633 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
634 | usb2_phy: usb2phy@4a084000 { |
635 | compatible = "ti,omap-usb2"; | |
636 | reg = <0x4a084000 0x7c>; | |
637 | ctrl-module = <&omap_control_usb>; | |
638 | }; | |
639 | ||
640 | usb3_phy: usb3phy@4a084400 { | |
641 | compatible = "ti,omap-usb3"; | |
642 | reg = <0x4a084400 0x80>, | |
643 | <0x4a084800 0x64>, | |
644 | <0x4a084c00 0x40>; | |
645 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
646 | ctrl-module = <&omap_control_usb>; | |
647 | }; | |
e9831967 | 648 | }; |
6b5de091 S |
649 | }; |
650 | }; |