Commit | Line | Data |
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6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
10 | /* | |
11 | * Carveout for multimedia usecases | |
12 | * It should be the last 48MB of the first 512MB memory part | |
13 | * In theory, it should not even exist. That zone should be reserved | |
14 | * dynamically during the .reserve callback. | |
15 | */ | |
16 | /memreserve/ 0x9d000000 0x03000000; | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | compatible = "ti,omap5"; | |
22 | interrupt-parent = <&gic>; | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart1; | |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
29 | serial4 = &uart5; | |
30 | serial5 = &uart6; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | cpu@0 { | |
35 | compatible = "arm,cortex-a15"; | |
3c7c5dab SS |
36 | timer { |
37 | compatible = "arm,armv7-timer"; | |
38 | /* 14th PPI IRQ, active low level-sensitive */ | |
39 | interrupts = <1 14 0x308>; | |
40 | clock-frequency = <6144000>; | |
41 | }; | |
6b5de091 S |
42 | }; |
43 | cpu@1 { | |
44 | compatible = "arm,cortex-a15"; | |
3c7c5dab SS |
45 | timer { |
46 | compatible = "arm,armv7-timer"; | |
47 | /* 14th PPI IRQ, active low level-sensitive */ | |
48 | interrupts = <1 14 0x308>; | |
49 | clock-frequency = <6144000>; | |
50 | }; | |
6b5de091 S |
51 | }; |
52 | }; | |
53 | ||
54 | /* | |
55 | * The soc node represents the soc top level view. It is uses for IPs | |
56 | * that are not memory mapped in the MPU view or for the MPU itself. | |
57 | */ | |
58 | soc { | |
59 | compatible = "ti,omap-infra"; | |
60 | mpu { | |
61 | compatible = "ti,omap5-mpu"; | |
62 | ti,hwmods = "mpu"; | |
63 | }; | |
64 | }; | |
65 | ||
66 | /* | |
67 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
68 | * The real OMAP interconnect network is quite complex. | |
69 | * Since that will not bring real advantage to represent that in DT for | |
70 | * the moment, just use a fake OCP bus entry to represent the whole bus | |
71 | * hierarchy. | |
72 | */ | |
73 | ocp { | |
74 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
75 | #address-cells = <1>; | |
76 | #size-cells = <1>; | |
77 | ranges; | |
78 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
79 | ||
3b3132f7 JH |
80 | counter32k: counter@4ae04000 { |
81 | compatible = "ti,omap-counter32k"; | |
82 | reg = <0x4ae04000 0x40>; | |
83 | ti,hwmods = "counter_32k"; | |
84 | }; | |
85 | ||
5da6a2d5 PU |
86 | omap5_pmx_core: pinmux@4a002840 { |
87 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
88 | reg = <0x4a002840 0x01b6>; | |
89 | #address-cells = <1>; | |
90 | #size-cells = <0>; | |
91 | pinctrl-single,register-width = <16>; | |
92 | pinctrl-single,function-mask = <0x7fff>; | |
93 | }; | |
94 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
95 | compatible = "ti,omap4-padconf", "pinctrl-single"; | |
96 | reg = <0x4ae0c840 0x0038>; | |
97 | #address-cells = <1>; | |
98 | #size-cells = <0>; | |
99 | pinctrl-single,register-width = <16>; | |
100 | pinctrl-single,function-mask = <0x7fff>; | |
101 | }; | |
102 | ||
6b5de091 S |
103 | gic: interrupt-controller@48211000 { |
104 | compatible = "arm,cortex-a15-gic"; | |
105 | interrupt-controller; | |
106 | #interrupt-cells = <3>; | |
107 | reg = <0x48211000 0x1000>, | |
108 | <0x48212000 0x1000>; | |
109 | }; | |
110 | ||
2c2dc545 JH |
111 | sdma: dma-controller@4a056000 { |
112 | compatible = "ti,omap4430-sdma"; | |
113 | reg = <0x4a056000 0x1000>; | |
114 | interrupts = <0 12 0x4>, | |
115 | <0 13 0x4>, | |
116 | <0 14 0x4>, | |
117 | <0 15 0x4>; | |
118 | #dma-cells = <1>; | |
119 | #dma-channels = <32>; | |
120 | #dma-requests = <127>; | |
121 | }; | |
122 | ||
6b5de091 S |
123 | gpio1: gpio@4ae10000 { |
124 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
125 | reg = <0x4ae10000 0x200>; |
126 | interrupts = <0 29 0x4>; | |
6b5de091 S |
127 | ti,hwmods = "gpio1"; |
128 | gpio-controller; | |
129 | #gpio-cells = <2>; | |
130 | interrupt-controller; | |
131 | #interrupt-cells = <1>; | |
132 | }; | |
133 | ||
134 | gpio2: gpio@48055000 { | |
135 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
136 | reg = <0x48055000 0x200>; |
137 | interrupts = <0 30 0x4>; | |
6b5de091 S |
138 | ti,hwmods = "gpio2"; |
139 | gpio-controller; | |
140 | #gpio-cells = <2>; | |
141 | interrupt-controller; | |
142 | #interrupt-cells = <1>; | |
143 | }; | |
144 | ||
145 | gpio3: gpio@48057000 { | |
146 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
147 | reg = <0x48057000 0x200>; |
148 | interrupts = <0 31 0x4>; | |
6b5de091 S |
149 | ti,hwmods = "gpio3"; |
150 | gpio-controller; | |
151 | #gpio-cells = <2>; | |
152 | interrupt-controller; | |
153 | #interrupt-cells = <1>; | |
154 | }; | |
155 | ||
156 | gpio4: gpio@48059000 { | |
157 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
158 | reg = <0x48059000 0x200>; |
159 | interrupts = <0 32 0x4>; | |
6b5de091 S |
160 | ti,hwmods = "gpio4"; |
161 | gpio-controller; | |
162 | #gpio-cells = <2>; | |
163 | interrupt-controller; | |
164 | #interrupt-cells = <1>; | |
165 | }; | |
166 | ||
167 | gpio5: gpio@4805b000 { | |
168 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
169 | reg = <0x4805b000 0x200>; |
170 | interrupts = <0 33 0x4>; | |
6b5de091 S |
171 | ti,hwmods = "gpio5"; |
172 | gpio-controller; | |
173 | #gpio-cells = <2>; | |
174 | interrupt-controller; | |
175 | #interrupt-cells = <1>; | |
176 | }; | |
177 | ||
178 | gpio6: gpio@4805d000 { | |
179 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
180 | reg = <0x4805d000 0x200>; |
181 | interrupts = <0 34 0x4>; | |
6b5de091 S |
182 | ti,hwmods = "gpio6"; |
183 | gpio-controller; | |
184 | #gpio-cells = <2>; | |
185 | interrupt-controller; | |
186 | #interrupt-cells = <1>; | |
187 | }; | |
188 | ||
189 | gpio7: gpio@48051000 { | |
190 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
191 | reg = <0x48051000 0x200>; |
192 | interrupts = <0 35 0x4>; | |
6b5de091 S |
193 | ti,hwmods = "gpio7"; |
194 | gpio-controller; | |
195 | #gpio-cells = <2>; | |
196 | interrupt-controller; | |
197 | #interrupt-cells = <1>; | |
198 | }; | |
199 | ||
200 | gpio8: gpio@48053000 { | |
201 | compatible = "ti,omap4-gpio"; | |
f4b224f2 SG |
202 | reg = <0x48053000 0x200>; |
203 | interrupts = <0 121 0x4>; | |
6b5de091 S |
204 | ti,hwmods = "gpio8"; |
205 | gpio-controller; | |
206 | #gpio-cells = <2>; | |
207 | interrupt-controller; | |
208 | #interrupt-cells = <1>; | |
209 | }; | |
210 | ||
1c7dbb55 JH |
211 | gpmc: gpmc@50000000 { |
212 | compatible = "ti,omap4430-gpmc"; | |
213 | reg = <0x50000000 0x1000>; | |
214 | #address-cells = <2>; | |
215 | #size-cells = <1>; | |
216 | interrupts = <0 20 0x4>; | |
217 | gpmc,num-cs = <8>; | |
218 | gpmc,num-waitpins = <4>; | |
219 | ti,hwmods = "gpmc"; | |
220 | }; | |
221 | ||
6e6a9a50 SP |
222 | i2c1: i2c@48070000 { |
223 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
224 | reg = <0x48070000 0x100>; |
225 | interrupts = <0 56 0x4>; | |
6e6a9a50 SP |
226 | #address-cells = <1>; |
227 | #size-cells = <0>; | |
228 | ti,hwmods = "i2c1"; | |
229 | }; | |
230 | ||
231 | i2c2: i2c@48072000 { | |
232 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
233 | reg = <0x48072000 0x100>; |
234 | interrupts = <0 57 0x4>; | |
6e6a9a50 SP |
235 | #address-cells = <1>; |
236 | #size-cells = <0>; | |
237 | ti,hwmods = "i2c2"; | |
238 | }; | |
239 | ||
240 | i2c3: i2c@48060000 { | |
241 | compatible = "ti,omap4-i2c"; | |
d7118bbd SG |
242 | reg = <0x48060000 0x100>; |
243 | interrupts = <0 61 0x4>; | |
6e6a9a50 SP |
244 | #address-cells = <1>; |
245 | #size-cells = <0>; | |
246 | ti,hwmods = "i2c3"; | |
247 | }; | |
248 | ||
d7118bbd | 249 | i2c4: i2c@4807a000 { |
6e6a9a50 | 250 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
251 | reg = <0x4807a000 0x100>; |
252 | interrupts = <0 62 0x4>; | |
6e6a9a50 SP |
253 | #address-cells = <1>; |
254 | #size-cells = <0>; | |
255 | ti,hwmods = "i2c4"; | |
256 | }; | |
257 | ||
d7118bbd | 258 | i2c5: i2c@4807c000 { |
6e6a9a50 | 259 | compatible = "ti,omap4-i2c"; |
d7118bbd SG |
260 | reg = <0x4807c000 0x100>; |
261 | interrupts = <0 60 0x4>; | |
6e6a9a50 SP |
262 | #address-cells = <1>; |
263 | #size-cells = <0>; | |
264 | ti,hwmods = "i2c5"; | |
265 | }; | |
266 | ||
43286b11 FB |
267 | mcspi1: spi@48098000 { |
268 | compatible = "ti,omap4-mcspi"; | |
269 | reg = <0x48098000 0x200>; | |
270 | interrupts = <0 65 0x4>; | |
271 | #address-cells = <1>; | |
272 | #size-cells = <0>; | |
273 | ti,hwmods = "mcspi1"; | |
274 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
275 | dmas = <&sdma 35>, |
276 | <&sdma 36>, | |
277 | <&sdma 37>, | |
278 | <&sdma 38>, | |
279 | <&sdma 39>, | |
280 | <&sdma 40>, | |
281 | <&sdma 41>, | |
282 | <&sdma 42>; | |
283 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
284 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
285 | }; |
286 | ||
287 | mcspi2: spi@4809a000 { | |
288 | compatible = "ti,omap4-mcspi"; | |
289 | reg = <0x4809a000 0x200>; | |
290 | interrupts = <0 66 0x4>; | |
291 | #address-cells = <1>; | |
292 | #size-cells = <0>; | |
293 | ti,hwmods = "mcspi2"; | |
294 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
295 | dmas = <&sdma 43>, |
296 | <&sdma 44>, | |
297 | <&sdma 45>, | |
298 | <&sdma 46>; | |
299 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
300 | }; |
301 | ||
302 | mcspi3: spi@480b8000 { | |
303 | compatible = "ti,omap4-mcspi"; | |
304 | reg = <0x480b8000 0x200>; | |
305 | interrupts = <0 91 0x4>; | |
306 | #address-cells = <1>; | |
307 | #size-cells = <0>; | |
308 | ti,hwmods = "mcspi3"; | |
309 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
310 | dmas = <&sdma 15>, <&sdma 16>; |
311 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
312 | }; |
313 | ||
314 | mcspi4: spi@480ba000 { | |
315 | compatible = "ti,omap4-mcspi"; | |
316 | reg = <0x480ba000 0x200>; | |
317 | interrupts = <0 48 0x4>; | |
318 | #address-cells = <1>; | |
319 | #size-cells = <0>; | |
320 | ti,hwmods = "mcspi4"; | |
321 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
322 | dmas = <&sdma 70>, <&sdma 71>; |
323 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
324 | }; |
325 | ||
6b5de091 S |
326 | uart1: serial@4806a000 { |
327 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
328 | reg = <0x4806a000 0x100>; |
329 | interrupts = <0 72 0x4>; | |
6b5de091 S |
330 | ti,hwmods = "uart1"; |
331 | clock-frequency = <48000000>; | |
332 | }; | |
333 | ||
334 | uart2: serial@4806c000 { | |
335 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
336 | reg = <0x4806c000 0x100>; |
337 | interrupts = <0 73 0x4>; | |
6b5de091 S |
338 | ti,hwmods = "uart2"; |
339 | clock-frequency = <48000000>; | |
340 | }; | |
341 | ||
342 | uart3: serial@48020000 { | |
343 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
344 | reg = <0x48020000 0x100>; |
345 | interrupts = <0 74 0x4>; | |
6b5de091 S |
346 | ti,hwmods = "uart3"; |
347 | clock-frequency = <48000000>; | |
348 | }; | |
349 | ||
350 | uart4: serial@4806e000 { | |
351 | compatible = "ti,omap4-uart"; | |
8e80f660 SG |
352 | reg = <0x4806e000 0x100>; |
353 | interrupts = <0 70 0x4>; | |
6b5de091 S |
354 | ti,hwmods = "uart4"; |
355 | clock-frequency = <48000000>; | |
356 | }; | |
357 | ||
358 | uart5: serial@48066000 { | |
8e80f660 SG |
359 | compatible = "ti,omap4-uart"; |
360 | reg = <0x48066000 0x100>; | |
361 | interrupts = <0 105 0x4>; | |
6b5de091 S |
362 | ti,hwmods = "uart5"; |
363 | clock-frequency = <48000000>; | |
364 | }; | |
365 | ||
366 | uart6: serial@48068000 { | |
8e80f660 SG |
367 | compatible = "ti,omap4-uart"; |
368 | reg = <0x48068000 0x100>; | |
369 | interrupts = <0 106 0x4>; | |
6b5de091 S |
370 | ti,hwmods = "uart6"; |
371 | clock-frequency = <48000000>; | |
372 | }; | |
5dd18b01 B |
373 | |
374 | mmc1: mmc@4809c000 { | |
375 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
376 | reg = <0x4809c000 0x400>; |
377 | interrupts = <0 83 0x4>; | |
5dd18b01 B |
378 | ti,hwmods = "mmc1"; |
379 | ti,dual-volt; | |
380 | ti,needs-special-reset; | |
2c2dc545 JH |
381 | dmas = <&sdma 61>, <&sdma 62>; |
382 | dma-names = "tx", "rx"; | |
5dd18b01 B |
383 | }; |
384 | ||
385 | mmc2: mmc@480b4000 { | |
386 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
387 | reg = <0x480b4000 0x400>; |
388 | interrupts = <0 86 0x4>; | |
5dd18b01 B |
389 | ti,hwmods = "mmc2"; |
390 | ti,needs-special-reset; | |
2c2dc545 JH |
391 | dmas = <&sdma 47>, <&sdma 48>; |
392 | dma-names = "tx", "rx"; | |
5dd18b01 B |
393 | }; |
394 | ||
395 | mmc3: mmc@480ad000 { | |
396 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
397 | reg = <0x480ad000 0x400>; |
398 | interrupts = <0 94 0x4>; | |
5dd18b01 B |
399 | ti,hwmods = "mmc3"; |
400 | ti,needs-special-reset; | |
2c2dc545 JH |
401 | dmas = <&sdma 77>, <&sdma 78>; |
402 | dma-names = "tx", "rx"; | |
5dd18b01 B |
403 | }; |
404 | ||
405 | mmc4: mmc@480d1000 { | |
406 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
407 | reg = <0x480d1000 0x400>; |
408 | interrupts = <0 96 0x4>; | |
5dd18b01 B |
409 | ti,hwmods = "mmc4"; |
410 | ti,needs-special-reset; | |
2c2dc545 JH |
411 | dmas = <&sdma 57>, <&sdma 58>; |
412 | dma-names = "tx", "rx"; | |
5dd18b01 B |
413 | }; |
414 | ||
415 | mmc5: mmc@480d5000 { | |
416 | compatible = "ti,omap4-hsmmc"; | |
9a642362 SG |
417 | reg = <0x480d5000 0x400>; |
418 | interrupts = <0 59 0x4>; | |
5dd18b01 B |
419 | ti,hwmods = "mmc5"; |
420 | ti,needs-special-reset; | |
2c2dc545 JH |
421 | dmas = <&sdma 59>, <&sdma 60>; |
422 | dma-names = "tx", "rx"; | |
5dd18b01 | 423 | }; |
5449fbc2 SP |
424 | |
425 | keypad: keypad@4ae1c000 { | |
426 | compatible = "ti,omap4-keypad"; | |
427 | ti,hwmods = "kbd"; | |
428 | }; | |
ffd5db24 | 429 | |
cbb57f07 PU |
430 | mcpdm: mcpdm@40132000 { |
431 | compatible = "ti,omap4-mcpdm"; | |
432 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
433 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
434 | reg-names = "mpu", "dma"; | |
435 | interrupts = <0 112 0x4>; | |
cbb57f07 PU |
436 | ti,hwmods = "mcpdm"; |
437 | }; | |
438 | ||
439 | dmic: dmic@4012e000 { | |
440 | compatible = "ti,omap4-dmic"; | |
441 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
442 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
443 | reg-names = "mpu", "dma"; | |
444 | interrupts = <0 114 0x4>; | |
cbb57f07 PU |
445 | ti,hwmods = "dmic"; |
446 | }; | |
447 | ||
ffd5db24 PU |
448 | mcbsp1: mcbsp@40122000 { |
449 | compatible = "ti,omap4-mcbsp"; | |
450 | reg = <0x40122000 0xff>, /* MPU private access */ | |
451 | <0x49022000 0xff>; /* L3 Interconnect */ | |
452 | reg-names = "mpu", "dma"; | |
453 | interrupts = <0 17 0x4>; | |
454 | interrupt-names = "common"; | |
ffd5db24 PU |
455 | ti,buffer-size = <128>; |
456 | ti,hwmods = "mcbsp1"; | |
457 | }; | |
458 | ||
459 | mcbsp2: mcbsp@40124000 { | |
460 | compatible = "ti,omap4-mcbsp"; | |
461 | reg = <0x40124000 0xff>, /* MPU private access */ | |
462 | <0x49024000 0xff>; /* L3 Interconnect */ | |
463 | reg-names = "mpu", "dma"; | |
464 | interrupts = <0 22 0x4>; | |
465 | interrupt-names = "common"; | |
ffd5db24 PU |
466 | ti,buffer-size = <128>; |
467 | ti,hwmods = "mcbsp2"; | |
468 | }; | |
469 | ||
470 | mcbsp3: mcbsp@40126000 { | |
471 | compatible = "ti,omap4-mcbsp"; | |
472 | reg = <0x40126000 0xff>, /* MPU private access */ | |
473 | <0x49026000 0xff>; /* L3 Interconnect */ | |
474 | reg-names = "mpu", "dma"; | |
475 | interrupts = <0 23 0x4>; | |
476 | interrupt-names = "common"; | |
ffd5db24 PU |
477 | ti,buffer-size = <128>; |
478 | ti,hwmods = "mcbsp3"; | |
479 | }; | |
df692a92 JH |
480 | |
481 | timer1: timer@4ae18000 { | |
482 | compatible = "ti,omap2-timer"; | |
483 | reg = <0x4ae18000 0x80>; | |
484 | interrupts = <0 37 0x4>; | |
485 | ti,hwmods = "timer1"; | |
486 | ti,timer-alwon; | |
487 | }; | |
488 | ||
489 | timer2: timer@48032000 { | |
490 | compatible = "ti,omap2-timer"; | |
491 | reg = <0x48032000 0x80>; | |
492 | interrupts = <0 38 0x4>; | |
493 | ti,hwmods = "timer2"; | |
494 | }; | |
495 | ||
496 | timer3: timer@48034000 { | |
497 | compatible = "ti,omap2-timer"; | |
498 | reg = <0x48034000 0x80>; | |
499 | interrupts = <0 39 0x4>; | |
500 | ti,hwmods = "timer3"; | |
501 | }; | |
502 | ||
503 | timer4: timer@48036000 { | |
504 | compatible = "ti,omap2-timer"; | |
505 | reg = <0x48036000 0x80>; | |
506 | interrupts = <0 40 0x4>; | |
507 | ti,hwmods = "timer4"; | |
508 | }; | |
509 | ||
510 | timer5: timer@40138000 { | |
511 | compatible = "ti,omap2-timer"; | |
512 | reg = <0x40138000 0x80>, | |
513 | <0x49038000 0x80>; | |
514 | interrupts = <0 41 0x4>; | |
515 | ti,hwmods = "timer5"; | |
516 | ti,timer-dsp; | |
517 | }; | |
518 | ||
519 | timer6: timer@4013a000 { | |
520 | compatible = "ti,omap2-timer"; | |
521 | reg = <0x4013a000 0x80>, | |
522 | <0x4903a000 0x80>; | |
523 | interrupts = <0 42 0x4>; | |
524 | ti,hwmods = "timer6"; | |
525 | ti,timer-dsp; | |
526 | ti,timer-pwm; | |
527 | }; | |
528 | ||
529 | timer7: timer@4013c000 { | |
530 | compatible = "ti,omap2-timer"; | |
531 | reg = <0x4013c000 0x80>, | |
532 | <0x4903c000 0x80>; | |
533 | interrupts = <0 43 0x4>; | |
534 | ti,hwmods = "timer7"; | |
535 | ti,timer-dsp; | |
536 | }; | |
537 | ||
538 | timer8: timer@4013e000 { | |
539 | compatible = "ti,omap2-timer"; | |
540 | reg = <0x4013e000 0x80>, | |
541 | <0x4903e000 0x80>; | |
542 | interrupts = <0 44 0x4>; | |
543 | ti,hwmods = "timer8"; | |
544 | ti,timer-dsp; | |
545 | ti,timer-pwm; | |
546 | }; | |
547 | ||
548 | timer9: timer@4803e000 { | |
549 | compatible = "ti,omap2-timer"; | |
550 | reg = <0x4803e000 0x80>; | |
551 | interrupts = <0 45 0x4>; | |
552 | ti,hwmods = "timer9"; | |
553 | }; | |
554 | ||
555 | timer10: timer@48086000 { | |
556 | compatible = "ti,omap2-timer"; | |
557 | reg = <0x48086000 0x80>; | |
558 | interrupts = <0 46 0x4>; | |
559 | ti,hwmods = "timer10"; | |
560 | }; | |
561 | ||
562 | timer11: timer@48088000 { | |
563 | compatible = "ti,omap2-timer"; | |
564 | reg = <0x48088000 0x80>; | |
565 | interrupts = <0 47 0x4>; | |
566 | ti,hwmods = "timer11"; | |
567 | ti,timer-pwm; | |
568 | }; | |
e6900ddf LV |
569 | |
570 | emif1: emif@0x4c000000 { | |
571 | compatible = "ti,emif-4d5"; | |
572 | ti,hwmods = "emif1"; | |
573 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
574 | reg = <0x4c000000 0x400>; | |
575 | interrupts = <0 110 0x4>; | |
576 | hw-caps-read-idle-ctrl; | |
577 | hw-caps-ll-interface; | |
578 | hw-caps-temp-alert; | |
579 | }; | |
580 | ||
581 | emif2: emif@0x4d000000 { | |
582 | compatible = "ti,emif-4d5"; | |
583 | ti,hwmods = "emif2"; | |
584 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | |
585 | reg = <0x4d000000 0x400>; | |
586 | interrupts = <0 111 0x4>; | |
587 | hw-caps-read-idle-ctrl; | |
588 | hw-caps-ll-interface; | |
589 | hw-caps-temp-alert; | |
590 | }; | |
fedc428e KVA |
591 | |
592 | omap_control_usb: omap-control-usb@4a002300 { | |
593 | compatible = "ti,omap-control-usb"; | |
594 | reg = <0x4a002300 0x4>, | |
595 | <0x4a002370 0x4>; | |
596 | reg-names = "control_dev_conf", "phy_power_usb"; | |
597 | ti,type = <2>; | |
598 | }; | |
e9831967 | 599 | |
72f6f957 KVA |
600 | omap_dwc3@4a020000 { |
601 | compatible = "ti,dwc3"; | |
602 | ti,hwmods = "usb_otg_ss"; | |
603 | reg = <0x4a020000 0x1000>; | |
604 | interrupts = <0 93 4>; | |
605 | #address-cells = <1>; | |
606 | #size-cells = <1>; | |
607 | utmi-mode = <2>; | |
608 | ranges; | |
609 | dwc3@4a030000 { | |
610 | compatible = "synopsys,dwc3"; | |
611 | reg = <0x4a030000 0x1000>; | |
612 | interrupts = <0 92 4>; | |
613 | usb-phy = <&usb2_phy>, <&usb3_phy>; | |
614 | tx-fifo-resize; | |
615 | }; | |
616 | }; | |
617 | ||
e9831967 KVA |
618 | ocp2scp { |
619 | compatible = "ti,omap-ocp2scp"; | |
620 | #address-cells = <1>; | |
621 | #size-cells = <1>; | |
622 | ranges; | |
623 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
624 | usb2_phy: usb2phy@4a084000 { |
625 | compatible = "ti,omap-usb2"; | |
626 | reg = <0x4a084000 0x7c>; | |
627 | ctrl-module = <&omap_control_usb>; | |
628 | }; | |
629 | ||
630 | usb3_phy: usb3phy@4a084400 { | |
631 | compatible = "ti,omap-usb3"; | |
632 | reg = <0x4a084400 0x80>, | |
633 | <0x4a084800 0x64>, | |
634 | <0x4a084c00 0x40>; | |
635 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
636 | ctrl-module = <&omap_control_usb>; | |
637 | }; | |
e9831967 | 638 | }; |
6b5de091 S |
639 | }; |
640 | }; |