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[deliverable/linux.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
30 };
31
32 cpus {
eeb25fd5
LP		 33 #address-cells = <1>;
34 #size-cells = <0>;
35
6b5de091 36 cpu@0 {
eeb25fd5 37 device_type = "cpu";
6b5de091 38 compatible = "arm,cortex-a15";
eeb25fd5 39 reg = <0x0>;
6b5de091
S		 40 };
41 cpu@1 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x1>;
6b5de091
S		 45 };
46 };
47
b45ccc4e
SS		 48 timer {
49 compatible = "arm,armv7-timer";
8fea7d5a
FV		 50 /* PPI secure/nonsecure IRQ */
51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 55 clock-frequency = <6144000>;
56 };
57
ba1829bc
SS		 58 gic: interrupt-controller@48211000 {
59 compatible = "arm,cortex-a15-gic";
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 reg = <0x48211000 0x1000>,
0129c16c
SS		 63 <0x48212000 0x1000>,
64 <0x48214000 0x2000>,
65 <0x48216000 0x2000>;
ba1829bc
SS		 66 };
67
6b5de091
S		 68 /*
69 * The soc node represents the soc top level view. It is uses for IPs
70 * that are not memory mapped in the MPU view or for the MPU itself.
71 */
72 soc {
73 compatible = "ti,omap-infra";
74 mpu {
75 compatible = "ti,omap5-mpu";
76 ti,hwmods = "mpu";
77 };
78 };
79
80 /*
81 * XXX: Use a flat representation of the OMAP3 interconnect.
82 * The real OMAP interconnect network is quite complex.
83 * Since that will not bring real advantage to represent that in DT for
84 * the moment, just use a fake OCP bus entry to represent the whole bus
85 * hierarchy.
86 */
87 ocp {
88 compatible = "ti,omap4-l3-noc", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 93 reg = <0x44000000 0x2000>,
94 <0x44800000 0x3000>,
95 <0x45000000 0x4000>;
8fea7d5a
FV		 96 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 98
3b3132f7
JH		 99 counter32k: counter@4ae04000 {
100 compatible = "ti,omap-counter32k";
101 reg = <0x4ae04000 0x40>;
102 ti,hwmods = "counter_32k";
103 };
104
5da6a2d5
PU		 105 omap5_pmx_core: pinmux@4a002840 {
106 compatible = "ti,omap4-padconf", "pinctrl-single";
107 reg = <0x4a002840 0x01b6>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 pinctrl-single,register-width = <16>;
111 pinctrl-single,function-mask = <0x7fff>;
112 };
113 omap5_pmx_wkup: pinmux@4ae0c840 {
114 compatible = "ti,omap4-padconf", "pinctrl-single";
115 reg = <0x4ae0c840 0x0038>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 pinctrl-single,register-width = <16>;
119 pinctrl-single,function-mask = <0x7fff>;
120 };
121
2c2dc545
JH		 122 sdma: dma-controller@4a056000 {
123 compatible = "ti,omap4430-sdma";
124 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 125 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 129 #dma-cells = <1>;
130 #dma-channels = <32>;
131 #dma-requests = <127>;
132 };
133
6b5de091
S		 134 gpio1: gpio@4ae10000 {
135 compatible = "ti,omap4-gpio";
f4b224f2 136 reg = <0x4ae10000 0x200>;
8fea7d5a 137 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 138 ti,hwmods = "gpio1";
e4b9b9f3 139 ti,gpio-always-on;
6b5de091
S		 140 gpio-controller;
141 #gpio-cells = <2>;
142 interrupt-controller;
ff5c9059 143 #interrupt-cells = <2>;
6b5de091
S		 144 };
145
146 gpio2: gpio@48055000 {
147 compatible = "ti,omap4-gpio";
f4b224f2 148 reg = <0x48055000 0x200>;
8fea7d5a 149 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 150 ti,hwmods = "gpio2";
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
ff5c9059 154 #interrupt-cells = <2>;
6b5de091
S		 155 };
156
157 gpio3: gpio@48057000 {
158 compatible = "ti,omap4-gpio";
f4b224f2 159 reg = <0x48057000 0x200>;
8fea7d5a 160 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 161 ti,hwmods = "gpio3";
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
ff5c9059 165 #interrupt-cells = <2>;
6b5de091
S		 166 };
167
168 gpio4: gpio@48059000 {
169 compatible = "ti,omap4-gpio";
f4b224f2 170 reg = <0x48059000 0x200>;
8fea7d5a 171 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 172 ti,hwmods = "gpio4";
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
ff5c9059 176 #interrupt-cells = <2>;
6b5de091
S		 177 };
178
179 gpio5: gpio@4805b000 {
180 compatible = "ti,omap4-gpio";
f4b224f2 181 reg = <0x4805b000 0x200>;
8fea7d5a 182 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 183 ti,hwmods = "gpio5";
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
ff5c9059 187 #interrupt-cells = <2>;
6b5de091
S		 188 };
189
190 gpio6: gpio@4805d000 {
191 compatible = "ti,omap4-gpio";
f4b224f2 192 reg = <0x4805d000 0x200>;
8fea7d5a 193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 194 ti,hwmods = "gpio6";
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
ff5c9059 198 #interrupt-cells = <2>;
6b5de091
S		 199 };
200
201 gpio7: gpio@48051000 {
202 compatible = "ti,omap4-gpio";
f4b224f2 203 reg = <0x48051000 0x200>;
8fea7d5a 204 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 205 ti,hwmods = "gpio7";
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
ff5c9059 209 #interrupt-cells = <2>;
6b5de091
S		 210 };
211
212 gpio8: gpio@48053000 {
213 compatible = "ti,omap4-gpio";
f4b224f2 214 reg = <0x48053000 0x200>;
8fea7d5a 215 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 216 ti,hwmods = "gpio8";
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
ff5c9059 220 #interrupt-cells = <2>;
6b5de091
S		 221 };
222
1c7dbb55
JH		 223 gpmc: gpmc@50000000 {
224 compatible = "ti,omap4430-gpmc";
225 reg = <0x50000000 0x1000>;
226 #address-cells = <2>;
227 #size-cells = <1>;
8fea7d5a 228 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 229 gpmc,num-cs = <8>;
230 gpmc,num-waitpins = <4>;
231 ti,hwmods = "gpmc";
232 };
233
6e6a9a50
SP		 234 i2c1: i2c@48070000 {
235 compatible = "ti,omap4-i2c";
d7118bbd 236 reg = <0x48070000 0x100>;
8fea7d5a 237 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 238 #address-cells = <1>;
239 #size-cells = <0>;
240 ti,hwmods = "i2c1";
241 };
242
243 i2c2: i2c@48072000 {
244 compatible = "ti,omap4-i2c";
d7118bbd 245 reg = <0x48072000 0x100>;
8fea7d5a 246 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 247 #address-cells = <1>;
248 #size-cells = <0>;
249 ti,hwmods = "i2c2";
250 };
251
252 i2c3: i2c@48060000 {
253 compatible = "ti,omap4-i2c";
d7118bbd 254 reg = <0x48060000 0x100>;
8fea7d5a 255 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 256 #address-cells = <1>;
257 #size-cells = <0>;
258 ti,hwmods = "i2c3";
259 };
260
d7118bbd 261 i2c4: i2c@4807a000 {
6e6a9a50 262 compatible = "ti,omap4-i2c";
d7118bbd 263 reg = <0x4807a000 0x100>;
8fea7d5a 264 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 265 #address-cells = <1>;
266 #size-cells = <0>;
267 ti,hwmods = "i2c4";
268 };
269
d7118bbd 270 i2c5: i2c@4807c000 {
6e6a9a50 271 compatible = "ti,omap4-i2c";
d7118bbd 272 reg = <0x4807c000 0x100>;
8fea7d5a 273 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 274 #address-cells = <1>;
275 #size-cells = <0>;
276 ti,hwmods = "i2c5";
277 };
278
43286b11
FB		 279 mcspi1: spi@48098000 {
280 compatible = "ti,omap4-mcspi";
281 reg = <0x48098000 0x200>;
8fea7d5a 282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 283 #address-cells = <1>;
284 #size-cells = <0>;
285 ti,hwmods = "mcspi1";
286 ti,spi-num-cs = <4>;
2c2dc545
JH		 287 dmas = <&sdma 35>,
288 <&sdma 36>,
289 <&sdma 37>,
290 <&sdma 38>,
291 <&sdma 39>,
292 <&sdma 40>,
293 <&sdma 41>,
294 <&sdma 42>;
295 dma-names = "tx0", "rx0", "tx1", "rx1",
296 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 297 };
298
299 mcspi2: spi@4809a000 {
300 compatible = "ti,omap4-mcspi";
301 reg = <0x4809a000 0x200>;
8fea7d5a 302 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 303 #address-cells = <1>;
304 #size-cells = <0>;
305 ti,hwmods = "mcspi2";
306 ti,spi-num-cs = <2>;
2c2dc545
JH		 307 dmas = <&sdma 43>,
308 <&sdma 44>,
309 <&sdma 45>,
310 <&sdma 46>;
311 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 312 };
313
314 mcspi3: spi@480b8000 {
315 compatible = "ti,omap4-mcspi";
316 reg = <0x480b8000 0x200>;
8fea7d5a 317 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 318 #address-cells = <1>;
319 #size-cells = <0>;
320 ti,hwmods = "mcspi3";
321 ti,spi-num-cs = <2>;
2c2dc545
JH		 322 dmas = <&sdma 15>, <&sdma 16>;
323 dma-names = "tx0", "rx0";
43286b11
FB		 324 };
325
326 mcspi4: spi@480ba000 {
327 compatible = "ti,omap4-mcspi";
328 reg = <0x480ba000 0x200>;
8fea7d5a 329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 330 #address-cells = <1>;
331 #size-cells = <0>;
332 ti,hwmods = "mcspi4";
333 ti,spi-num-cs = <1>;
2c2dc545
JH		 334 dmas = <&sdma 70>, <&sdma 71>;
335 dma-names = "tx0", "rx0";
43286b11
FB		 336 };
337
6b5de091
S		 338 uart1: serial@4806a000 {
339 compatible = "ti,omap4-uart";
8e80f660 340 reg = <0x4806a000 0x100>;
8fea7d5a 341 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 342 ti,hwmods = "uart1";
343 clock-frequency = <48000000>;
344 };
345
346 uart2: serial@4806c000 {
347 compatible = "ti,omap4-uart";
8e80f660 348 reg = <0x4806c000 0x100>;
8fea7d5a 349 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 350 ti,hwmods = "uart2";
351 clock-frequency = <48000000>;
352 };
353
354 uart3: serial@48020000 {
355 compatible = "ti,omap4-uart";
8e80f660 356 reg = <0x48020000 0x100>;
8fea7d5a 357 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 358 ti,hwmods = "uart3";
359 clock-frequency = <48000000>;
360 };
361
362 uart4: serial@4806e000 {
363 compatible = "ti,omap4-uart";
8e80f660 364 reg = <0x4806e000 0x100>;
8fea7d5a 365 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 366 ti,hwmods = "uart4";
367 clock-frequency = <48000000>;
368 };
369
370 uart5: serial@48066000 {
8e80f660
SG		 371 compatible = "ti,omap4-uart";
372 reg = <0x48066000 0x100>;
8fea7d5a 373 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 374 ti,hwmods = "uart5";
375 clock-frequency = <48000000>;
376 };
377
378 uart6: serial@48068000 {
8e80f660
SG		 379 compatible = "ti,omap4-uart";
380 reg = <0x48068000 0x100>;
8fea7d5a 381 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 382 ti,hwmods = "uart6";
383 clock-frequency = <48000000>;
384 };
5dd18b01
B		 385
386 mmc1: mmc@4809c000 {
387 compatible = "ti,omap4-hsmmc";
9a642362 388 reg = <0x4809c000 0x400>;
8fea7d5a 389 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 390 ti,hwmods = "mmc1";
391 ti,dual-volt;
392 ti,needs-special-reset;
2c2dc545
JH		 393 dmas = <&sdma 61>, <&sdma 62>;
394 dma-names = "tx", "rx";
5dd18b01
B		 395 };
396
397 mmc2: mmc@480b4000 {
398 compatible = "ti,omap4-hsmmc";
9a642362 399 reg = <0x480b4000 0x400>;
8fea7d5a 400 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 401 ti,hwmods = "mmc2";
402 ti,needs-special-reset;
2c2dc545
JH		 403 dmas = <&sdma 47>, <&sdma 48>;
404 dma-names = "tx", "rx";
5dd18b01
B		 405 };
406
407 mmc3: mmc@480ad000 {
408 compatible = "ti,omap4-hsmmc";
9a642362 409 reg = <0x480ad000 0x400>;
8fea7d5a 410 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 411 ti,hwmods = "mmc3";
412 ti,needs-special-reset;
2c2dc545
JH		 413 dmas = <&sdma 77>, <&sdma 78>;
414 dma-names = "tx", "rx";
5dd18b01
B		 415 };
416
417 mmc4: mmc@480d1000 {
418 compatible = "ti,omap4-hsmmc";
9a642362 419 reg = <0x480d1000 0x400>;
8fea7d5a 420 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 421 ti,hwmods = "mmc4";
422 ti,needs-special-reset;
2c2dc545
JH		 423 dmas = <&sdma 57>, <&sdma 58>;
424 dma-names = "tx", "rx";
5dd18b01
B		 425 };
426
427 mmc5: mmc@480d5000 {
428 compatible = "ti,omap4-hsmmc";
9a642362 429 reg = <0x480d5000 0x400>;
8fea7d5a 430 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 431 ti,hwmods = "mmc5";
432 ti,needs-special-reset;
2c2dc545
JH		 433 dmas = <&sdma 59>, <&sdma 60>;
434 dma-names = "tx", "rx";
5dd18b01 435 };
5449fbc2
SP		 436
437 keypad: keypad@4ae1c000 {
438 compatible = "ti,omap4-keypad";
8cc8b89f 439 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 440 ti,hwmods = "kbd";
441 };
ffd5db24 442
cbb57f07
PU		 443 mcpdm: mcpdm@40132000 {
444 compatible = "ti,omap4-mcpdm";
445 reg = <0x40132000 0x7f>, /* MPU private access */
446 <0x49032000 0x7f>; /* L3 Interconnect */
447 reg-names = "mpu", "dma";
8fea7d5a 448 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 449 ti,hwmods = "mcpdm";
4e4ead73
SG		 450 dmas = <&sdma 65>,
451 <&sdma 66>;
452 dma-names = "up_link", "dn_link";
cbb57f07
PU		 453 };
454
455 dmic: dmic@4012e000 {
456 compatible = "ti,omap4-dmic";
457 reg = <0x4012e000 0x7f>, /* MPU private access */
458 <0x4902e000 0x7f>; /* L3 Interconnect */
459 reg-names = "mpu", "dma";
8fea7d5a 460 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 461 ti,hwmods = "dmic";
4e4ead73
SG		 462 dmas = <&sdma 67>;
463 dma-names = "up_link";
cbb57f07
PU		 464 };
465
ffd5db24
PU		 466 mcbsp1: mcbsp@40122000 {
467 compatible = "ti,omap4-mcbsp";
468 reg = <0x40122000 0xff>, /* MPU private access */
469 <0x49022000 0xff>; /* L3 Interconnect */
470 reg-names = "mpu", "dma";
8fea7d5a 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 472 interrupt-names = "common";
ffd5db24
PU		 473 ti,buffer-size = <128>;
474 ti,hwmods = "mcbsp1";
4e4ead73
SG		 475 dmas = <&sdma 33>,
476 <&sdma 34>;
477 dma-names = "tx", "rx";
ffd5db24
PU		 478 };
479
480 mcbsp2: mcbsp@40124000 {
481 compatible = "ti,omap4-mcbsp";
482 reg = <0x40124000 0xff>, /* MPU private access */
483 <0x49024000 0xff>; /* L3 Interconnect */
484 reg-names = "mpu", "dma";
8fea7d5a 485 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 486 interrupt-names = "common";
ffd5db24
PU		 487 ti,buffer-size = <128>;
488 ti,hwmods = "mcbsp2";
4e4ead73
SG		 489 dmas = <&sdma 17>,
490 <&sdma 18>;
491 dma-names = "tx", "rx";
ffd5db24
PU		 492 };
493
494 mcbsp3: mcbsp@40126000 {
495 compatible = "ti,omap4-mcbsp";
496 reg = <0x40126000 0xff>, /* MPU private access */
497 <0x49026000 0xff>; /* L3 Interconnect */
498 reg-names = "mpu", "dma";
8fea7d5a 499 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 500 interrupt-names = "common";
ffd5db24
PU		 501 ti,buffer-size = <128>;
502 ti,hwmods = "mcbsp3";
4e4ead73
SG		 503 dmas = <&sdma 19>,
504 <&sdma 20>;
505 dma-names = "tx", "rx";
ffd5db24 506 };
df692a92
JH		 507
508 timer1: timer@4ae18000 {
002e1ec5 509 compatible = "ti,omap5430-timer";
df692a92 510 reg = <0x4ae18000 0x80>;
8fea7d5a 511 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 512 ti,hwmods = "timer1";
513 ti,timer-alwon;
514 };
515
516 timer2: timer@48032000 {
002e1ec5 517 compatible = "ti,omap5430-timer";
df692a92 518 reg = <0x48032000 0x80>;
8fea7d5a 519 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 520 ti,hwmods = "timer2";
521 };
522
523 timer3: timer@48034000 {
002e1ec5 524 compatible = "ti,omap5430-timer";
df692a92 525 reg = <0x48034000 0x80>;
8fea7d5a 526 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 527 ti,hwmods = "timer3";
528 };
529
530 timer4: timer@48036000 {
002e1ec5 531 compatible = "ti,omap5430-timer";
df692a92 532 reg = <0x48036000 0x80>;
8fea7d5a 533 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 534 ti,hwmods = "timer4";
535 };
536
537 timer5: timer@40138000 {
002e1ec5 538 compatible = "ti,omap5430-timer";
df692a92
JH		 539 reg = <0x40138000 0x80>,
540 <0x49038000 0x80>;
8fea7d5a 541 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 542 ti,hwmods = "timer5";
543 ti,timer-dsp;
8341613a 544 ti,timer-pwm;
df692a92
JH		 545 };
546
547 timer6: timer@4013a000 {
002e1ec5 548 compatible = "ti,omap5430-timer";
df692a92
JH		 549 reg = <0x4013a000 0x80>,
550 <0x4903a000 0x80>;
8fea7d5a 551 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 552 ti,hwmods = "timer6";
553 ti,timer-dsp;
554 ti,timer-pwm;
555 };
556
557 timer7: timer@4013c000 {
002e1ec5 558 compatible = "ti,omap5430-timer";
df692a92
JH		 559 reg = <0x4013c000 0x80>,
560 <0x4903c000 0x80>;
8fea7d5a 561 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 562 ti,hwmods = "timer7";
563 ti,timer-dsp;
564 };
565
566 timer8: timer@4013e000 {
002e1ec5 567 compatible = "ti,omap5430-timer";
df692a92
JH		 568 reg = <0x4013e000 0x80>,
569 <0x4903e000 0x80>;
8fea7d5a 570 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 571 ti,hwmods = "timer8";
572 ti,timer-dsp;
573 ti,timer-pwm;
574 };
575
576 timer9: timer@4803e000 {
002e1ec5 577 compatible = "ti,omap5430-timer";
df692a92 578 reg = <0x4803e000 0x80>;
8fea7d5a 579 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 580 ti,hwmods = "timer9";
8341613a 581 ti,timer-pwm;
df692a92
JH		 582 };
583
584 timer10: timer@48086000 {
002e1ec5 585 compatible = "ti,omap5430-timer";
df692a92 586 reg = <0x48086000 0x80>;
8fea7d5a 587 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 588 ti,hwmods = "timer10";
8341613a 589 ti,timer-pwm;
df692a92
JH		 590 };
591
592 timer11: timer@48088000 {
002e1ec5 593 compatible = "ti,omap5430-timer";
df692a92 594 reg = <0x48088000 0x80>;
8fea7d5a 595 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 596 ti,hwmods = "timer11";
597 ti,timer-pwm;
598 };
e6900ddf 599
55452197
LV		 600 wdt2: wdt@4ae14000 {
601 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
602 reg = <0x4ae14000 0x80>;
8fea7d5a 603 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 604 ti,hwmods = "wd_timer2";
605 };
606
e6900ddf
LV		 607 emif1: emif@0x4c000000 {
608 compatible = "ti,emif-4d5";
609 ti,hwmods = "emif1";
610 phy-type = <2>; /* DDR PHY type: Intelli PHY */
611 reg = <0x4c000000 0x400>;
8fea7d5a 612 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 613 hw-caps-read-idle-ctrl;
614 hw-caps-ll-interface;
615 hw-caps-temp-alert;
616 };
617
618 emif2: emif@0x4d000000 {
619 compatible = "ti,emif-4d5";
620 ti,hwmods = "emif2";
621 phy-type = <2>; /* DDR PHY type: Intelli PHY */
622 reg = <0x4d000000 0x400>;
8fea7d5a 623 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 624 hw-caps-read-idle-ctrl;
625 hw-caps-ll-interface;
626 hw-caps-temp-alert;
627 };
fedc428e
KVA		 628
629 omap_control_usb: omap-control-usb@4a002300 {
630 compatible = "ti,omap-control-usb";
631 reg = <0x4a002300 0x4>,
632 <0x4a002370 0x4>;
633 reg-names = "control_dev_conf", "phy_power_usb";
634 ti,type = <2>;
635 };
e9831967 636
72f6f957
KVA		 637 omap_dwc3@4a020000 {
638 compatible = "ti,dwc3";
639 ti,hwmods = "usb_otg_ss";
640 reg = <0x4a020000 0x1000>;
8fea7d5a 641 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 642 #address-cells = <1>;
643 #size-cells = <1>;
644 utmi-mode = <2>;
645 ranges;
646 dwc3@4a030000 {
22a5aa17 647 compatible = "snps,dwc3";
72f6f957 648 reg = <0x4a030000 0x1000>;
8fea7d5a 649 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 650 usb-phy = <&usb2_phy>, <&usb3_phy>;
651 tx-fifo-resize;
652 };
653 };
654
e9831967
KVA		 655 ocp2scp {
656 compatible = "ti,omap-ocp2scp";
657 #address-cells = <1>;
658 #size-cells = <1>;
659 ranges;
660 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 661 usb2_phy: usb2phy@4a084000 {
662 compatible = "ti,omap-usb2";
663 reg = <0x4a084000 0x7c>;
664 ctrl-module = <&omap_control_usb>;
665 };
666
667 usb3_phy: usb3phy@4a084400 {
668 compatible = "ti,omap-usb3";
669 reg = <0x4a084400 0x80>,
670 <0x4a084800 0x64>,
671 <0x4a084c00 0x40>;
672 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
673 ctrl-module = <&omap_control_usb>;
674 };
e9831967 675 };
ed7f8e8a
RQ		 676
677 usbhstll: usbhstll@4a062000 {
678 compatible = "ti,usbhs-tll";
679 reg = <0x4a062000 0x1000>;
680 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
681 ti,hwmods = "usb_tll_hs";
682 };
683
684 usbhshost: usbhshost@4a064000 {
685 compatible = "ti,usbhs-host";
686 reg = <0x4a064000 0x800>;
687 ti,hwmods = "usb_host_hs";
688 #address-cells = <1>;
689 #size-cells = <1>;
690 ranges;
691
692 usbhsohci: ohci@4a064800 {
693 compatible = "ti,ohci-omap3", "usb-ohci";
694 reg = <0x4a064800 0x400>;
695 interrupt-parent = <&gic>;
696 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
697 };
698
699 usbhsehci: ehci@4a064c00 {
700 compatible = "ti,ehci-omap", "usb-ehci";
701 reg = <0x4a064c00 0x400>;
702 interrupt-parent = <&gic>;
703 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
704 };
705 };
cbad26db
EV		 706
707 bandgap@4a0021e0 {
708 reg = <0x4a0021e0 0xc
709 0x4a00232c 0xc
710 0x4a002380 0x2c
711 0x4a0023C0 0x3c>;
712 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
713 compatible = "ti,omap5430-bandgap";
714 };
6b5de091
S		 715 };
716};
Linux kernel - Deliverables
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