Commit | Line | Data |
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6b5de091 S |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * Based on "omap4.dtsi" | |
8 | */ | |
9 | ||
6d624eab | 10 | #include <dt-bindings/gpio/gpio.h> |
8fea7d5a | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
bcd3cca7 | 12 | #include <dt-bindings/pinctrl/omap.h> |
6b5de091 | 13 | |
98ef7957 | 14 | #include "skeleton.dtsi" |
6b5de091 S |
15 | |
16 | / { | |
ba1829bc SS |
17 | #address-cells = <1>; |
18 | #size-cells = <1>; | |
19 | ||
6b5de091 S |
20 | compatible = "ti,omap5"; |
21 | interrupt-parent = <&gic>; | |
22 | ||
23 | aliases { | |
20b80942 NM |
24 | i2c0 = &i2c1; |
25 | i2c1 = &i2c2; | |
26 | i2c2 = &i2c3; | |
27 | i2c3 = &i2c4; | |
28 | i2c4 = &i2c5; | |
6b5de091 S |
29 | serial0 = &uart1; |
30 | serial1 = &uart2; | |
31 | serial2 = &uart3; | |
32 | serial3 = &uart4; | |
33 | serial4 = &uart5; | |
34 | serial5 = &uart6; | |
35 | }; | |
36 | ||
37 | cpus { | |
eeb25fd5 LP |
38 | #address-cells = <1>; |
39 | #size-cells = <0>; | |
40 | ||
b8981d71 | 41 | cpu0: cpu@0 { |
eeb25fd5 | 42 | device_type = "cpu"; |
6b5de091 | 43 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 44 | reg = <0x0>; |
6c24894d K |
45 | |
46 | operating-points = < | |
47 | /* kHz uV */ | |
6c24894d K |
48 | 1000000 1060000 |
49 | 1500000 1250000 | |
50 | >; | |
8d766fa2 NM |
51 | |
52 | clocks = <&dpll_mpu_ck>; | |
53 | clock-names = "cpu"; | |
54 | ||
55 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
56 | ||
2cd29f63 EV |
57 | /* cooling options */ |
58 | cooling-min-level = <0>; | |
59 | cooling-max-level = <2>; | |
60 | #cooling-cells = <2>; /* min followed by max */ | |
6b5de091 S |
61 | }; |
62 | cpu@1 { | |
eeb25fd5 | 63 | device_type = "cpu"; |
6b5de091 | 64 | compatible = "arm,cortex-a15"; |
eeb25fd5 | 65 | reg = <0x1>; |
6b5de091 S |
66 | }; |
67 | }; | |
68 | ||
1b761fc5 EV |
69 | thermal-zones { |
70 | #include "omap4-cpu-thermal.dtsi" | |
71 | #include "omap5-gpu-thermal.dtsi" | |
72 | #include "omap5-core-thermal.dtsi" | |
73 | }; | |
74 | ||
b45ccc4e SS |
75 | timer { |
76 | compatible = "arm,armv7-timer"; | |
8fea7d5a FV |
77 | /* PPI secure/nonsecure IRQ */ |
78 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
79 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
80 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, | |
81 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; | |
b45ccc4e SS |
82 | }; |
83 | ||
69a126cb NL |
84 | pmu { |
85 | compatible = "arm,cortex-a15-pmu"; | |
86 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
87 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
88 | }; | |
89 | ||
ba1829bc SS |
90 | gic: interrupt-controller@48211000 { |
91 | compatible = "arm,cortex-a15-gic"; | |
92 | interrupt-controller; | |
93 | #interrupt-cells = <3>; | |
94 | reg = <0x48211000 0x1000>, | |
0129c16c SS |
95 | <0x48212000 0x1000>, |
96 | <0x48214000 0x2000>, | |
97 | <0x48216000 0x2000>; | |
ba1829bc SS |
98 | }; |
99 | ||
6b5de091 | 100 | /* |
5c5be9db | 101 | * The soc node represents the soc top level view. It is used for IPs |
6b5de091 S |
102 | * that are not memory mapped in the MPU view or for the MPU itself. |
103 | */ | |
104 | soc { | |
105 | compatible = "ti,omap-infra"; | |
106 | mpu { | |
1306c08a | 107 | compatible = "ti,omap4-mpu"; |
6b5de091 | 108 | ti,hwmods = "mpu"; |
1306c08a | 109 | sram = <&ocmcram>; |
6b5de091 S |
110 | }; |
111 | }; | |
112 | ||
113 | /* | |
114 | * XXX: Use a flat representation of the OMAP3 interconnect. | |
115 | * The real OMAP interconnect network is quite complex. | |
b7ab524b | 116 | * Since it will not bring real advantage to represent that in DT for |
6b5de091 S |
117 | * the moment, just use a fake OCP bus entry to represent the whole bus |
118 | * hierarchy. | |
119 | */ | |
120 | ocp { | |
121 | compatible = "ti,omap4-l3-noc", "simple-bus"; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <1>; | |
124 | ranges; | |
125 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | |
20a60eaa SS |
126 | reg = <0x44000000 0x2000>, |
127 | <0x44800000 0x3000>, | |
128 | <0x45000000 0x4000>; | |
8fea7d5a FV |
129 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
130 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
6b5de091 | 131 | |
85dc74e9 TK |
132 | prm: prm@4ae06000 { |
133 | compatible = "ti,omap5-prm"; | |
134 | reg = <0x4ae06000 0x3000>; | |
5081ce62 | 135 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
85dc74e9 TK |
136 | |
137 | prm_clocks: clocks { | |
138 | #address-cells = <1>; | |
139 | #size-cells = <0>; | |
140 | }; | |
141 | ||
142 | prm_clockdomains: clockdomains { | |
143 | }; | |
144 | }; | |
145 | ||
146 | cm_core_aon: cm_core_aon@4a004000 { | |
147 | compatible = "ti,omap5-cm-core-aon"; | |
148 | reg = <0x4a004000 0x2000>; | |
149 | ||
150 | cm_core_aon_clocks: clocks { | |
151 | #address-cells = <1>; | |
152 | #size-cells = <0>; | |
153 | }; | |
154 | ||
155 | cm_core_aon_clockdomains: clockdomains { | |
156 | }; | |
157 | }; | |
158 | ||
159 | scrm: scrm@4ae0a000 { | |
160 | compatible = "ti,omap5-scrm"; | |
161 | reg = <0x4ae0a000 0x2000>; | |
162 | ||
163 | scrm_clocks: clocks { | |
164 | #address-cells = <1>; | |
165 | #size-cells = <0>; | |
166 | }; | |
167 | ||
168 | scrm_clockdomains: clockdomains { | |
169 | }; | |
170 | }; | |
171 | ||
172 | cm_core: cm_core@4a008000 { | |
173 | compatible = "ti,omap5-cm-core"; | |
174 | reg = <0x4a008000 0x3000>; | |
175 | ||
176 | cm_core_clocks: clocks { | |
177 | #address-cells = <1>; | |
178 | #size-cells = <0>; | |
179 | }; | |
180 | ||
181 | cm_core_clockdomains: clockdomains { | |
182 | }; | |
183 | }; | |
184 | ||
3b3132f7 JH |
185 | counter32k: counter@4ae04000 { |
186 | compatible = "ti,omap-counter32k"; | |
187 | reg = <0x4ae04000 0x40>; | |
188 | ti,hwmods = "counter_32k"; | |
189 | }; | |
190 | ||
5da6a2d5 | 191 | omap5_pmx_core: pinmux@4a002840 { |
924c31cc | 192 | compatible = "ti,omap5-padconf", "pinctrl-single"; |
5da6a2d5 PU |
193 | reg = <0x4a002840 0x01b6>; |
194 | #address-cells = <1>; | |
195 | #size-cells = <0>; | |
924c31cc NM |
196 | #interrupt-cells = <1>; |
197 | interrupt-controller; | |
5da6a2d5 PU |
198 | pinctrl-single,register-width = <16>; |
199 | pinctrl-single,function-mask = <0x7fff>; | |
200 | }; | |
201 | omap5_pmx_wkup: pinmux@4ae0c840 { | |
924c31cc | 202 | compatible = "ti,omap5-padconf", "pinctrl-single"; |
5da6a2d5 PU |
203 | reg = <0x4ae0c840 0x0038>; |
204 | #address-cells = <1>; | |
205 | #size-cells = <0>; | |
924c31cc NM |
206 | #interrupt-cells = <1>; |
207 | interrupt-controller; | |
5da6a2d5 PU |
208 | pinctrl-single,register-width = <16>; |
209 | pinctrl-single,function-mask = <0x7fff>; | |
210 | }; | |
211 | ||
cd042fe5 B |
212 | omap5_padconf_global: tisyscon@4a002da0 { |
213 | compatible = "syscon"; | |
214 | reg = <0x4A002da0 0xec>; | |
215 | }; | |
216 | ||
217 | pbias_regulator: pbias_regulator { | |
218 | compatible = "ti,pbias-omap"; | |
219 | reg = <0x60 0x4>; | |
220 | syscon = <&omap5_padconf_global>; | |
221 | pbias_mmc_reg: pbias_mmc_omap5 { | |
222 | regulator-name = "pbias_mmc_omap5"; | |
223 | regulator-min-microvolt = <1800000>; | |
224 | regulator-max-microvolt = <3000000>; | |
225 | }; | |
226 | }; | |
227 | ||
8b9a2810 RN |
228 | ocmcram: ocmcram@40300000 { |
229 | compatible = "mmio-sram"; | |
230 | reg = <0x40300000 0x20000>; /* 128k */ | |
231 | }; | |
232 | ||
2c2dc545 JH |
233 | sdma: dma-controller@4a056000 { |
234 | compatible = "ti,omap4430-sdma"; | |
235 | reg = <0x4a056000 0x1000>; | |
8fea7d5a FV |
236 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
237 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
238 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
239 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
2c2dc545 | 240 | #dma-cells = <1>; |
951c1c04 PU |
241 | dma-channels = <32>; |
242 | dma-requests = <127>; | |
2c2dc545 JH |
243 | }; |
244 | ||
6b5de091 S |
245 | gpio1: gpio@4ae10000 { |
246 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 247 | reg = <0x4ae10000 0x200>; |
8fea7d5a | 248 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 | 249 | ti,hwmods = "gpio1"; |
e4b9b9f3 | 250 | ti,gpio-always-on; |
6b5de091 S |
251 | gpio-controller; |
252 | #gpio-cells = <2>; | |
253 | interrupt-controller; | |
ff5c9059 | 254 | #interrupt-cells = <2>; |
6b5de091 S |
255 | }; |
256 | ||
257 | gpio2: gpio@48055000 { | |
258 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 259 | reg = <0x48055000 0x200>; |
8fea7d5a | 260 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
261 | ti,hwmods = "gpio2"; |
262 | gpio-controller; | |
263 | #gpio-cells = <2>; | |
264 | interrupt-controller; | |
ff5c9059 | 265 | #interrupt-cells = <2>; |
6b5de091 S |
266 | }; |
267 | ||
268 | gpio3: gpio@48057000 { | |
269 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 270 | reg = <0x48057000 0x200>; |
8fea7d5a | 271 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
272 | ti,hwmods = "gpio3"; |
273 | gpio-controller; | |
274 | #gpio-cells = <2>; | |
275 | interrupt-controller; | |
ff5c9059 | 276 | #interrupt-cells = <2>; |
6b5de091 S |
277 | }; |
278 | ||
279 | gpio4: gpio@48059000 { | |
280 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 281 | reg = <0x48059000 0x200>; |
8fea7d5a | 282 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
283 | ti,hwmods = "gpio4"; |
284 | gpio-controller; | |
285 | #gpio-cells = <2>; | |
286 | interrupt-controller; | |
ff5c9059 | 287 | #interrupt-cells = <2>; |
6b5de091 S |
288 | }; |
289 | ||
290 | gpio5: gpio@4805b000 { | |
291 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 292 | reg = <0x4805b000 0x200>; |
8fea7d5a | 293 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
294 | ti,hwmods = "gpio5"; |
295 | gpio-controller; | |
296 | #gpio-cells = <2>; | |
297 | interrupt-controller; | |
ff5c9059 | 298 | #interrupt-cells = <2>; |
6b5de091 S |
299 | }; |
300 | ||
301 | gpio6: gpio@4805d000 { | |
302 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 303 | reg = <0x4805d000 0x200>; |
8fea7d5a | 304 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
305 | ti,hwmods = "gpio6"; |
306 | gpio-controller; | |
307 | #gpio-cells = <2>; | |
308 | interrupt-controller; | |
ff5c9059 | 309 | #interrupt-cells = <2>; |
6b5de091 S |
310 | }; |
311 | ||
312 | gpio7: gpio@48051000 { | |
313 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 314 | reg = <0x48051000 0x200>; |
8fea7d5a | 315 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
316 | ti,hwmods = "gpio7"; |
317 | gpio-controller; | |
318 | #gpio-cells = <2>; | |
319 | interrupt-controller; | |
ff5c9059 | 320 | #interrupt-cells = <2>; |
6b5de091 S |
321 | }; |
322 | ||
323 | gpio8: gpio@48053000 { | |
324 | compatible = "ti,omap4-gpio"; | |
f4b224f2 | 325 | reg = <0x48053000 0x200>; |
8fea7d5a | 326 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
327 | ti,hwmods = "gpio8"; |
328 | gpio-controller; | |
329 | #gpio-cells = <2>; | |
330 | interrupt-controller; | |
ff5c9059 | 331 | #interrupt-cells = <2>; |
6b5de091 S |
332 | }; |
333 | ||
1c7dbb55 JH |
334 | gpmc: gpmc@50000000 { |
335 | compatible = "ti,omap4430-gpmc"; | |
336 | reg = <0x50000000 0x1000>; | |
337 | #address-cells = <2>; | |
338 | #size-cells = <1>; | |
8fea7d5a | 339 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
1c7dbb55 JH |
340 | gpmc,num-cs = <8>; |
341 | gpmc,num-waitpins = <4>; | |
342 | ti,hwmods = "gpmc"; | |
7b8b6af1 FV |
343 | clocks = <&l3_iclk_div>; |
344 | clock-names = "fck"; | |
1c7dbb55 JH |
345 | }; |
346 | ||
6e6a9a50 SP |
347 | i2c1: i2c@48070000 { |
348 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 349 | reg = <0x48070000 0x100>; |
8fea7d5a | 350 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
351 | #address-cells = <1>; |
352 | #size-cells = <0>; | |
353 | ti,hwmods = "i2c1"; | |
354 | }; | |
355 | ||
356 | i2c2: i2c@48072000 { | |
357 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 358 | reg = <0x48072000 0x100>; |
8fea7d5a | 359 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
360 | #address-cells = <1>; |
361 | #size-cells = <0>; | |
362 | ti,hwmods = "i2c2"; | |
363 | }; | |
364 | ||
365 | i2c3: i2c@48060000 { | |
366 | compatible = "ti,omap4-i2c"; | |
d7118bbd | 367 | reg = <0x48060000 0x100>; |
8fea7d5a | 368 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
369 | #address-cells = <1>; |
370 | #size-cells = <0>; | |
371 | ti,hwmods = "i2c3"; | |
372 | }; | |
373 | ||
d7118bbd | 374 | i2c4: i2c@4807a000 { |
6e6a9a50 | 375 | compatible = "ti,omap4-i2c"; |
d7118bbd | 376 | reg = <0x4807a000 0x100>; |
8fea7d5a | 377 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
378 | #address-cells = <1>; |
379 | #size-cells = <0>; | |
380 | ti,hwmods = "i2c4"; | |
381 | }; | |
382 | ||
d7118bbd | 383 | i2c5: i2c@4807c000 { |
6e6a9a50 | 384 | compatible = "ti,omap4-i2c"; |
d7118bbd | 385 | reg = <0x4807c000 0x100>; |
8fea7d5a | 386 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
6e6a9a50 SP |
387 | #address-cells = <1>; |
388 | #size-cells = <0>; | |
389 | ti,hwmods = "i2c5"; | |
390 | }; | |
391 | ||
fe0e09e4 SA |
392 | hwspinlock: spinlock@4a0f6000 { |
393 | compatible = "ti,omap4-hwspinlock"; | |
394 | reg = <0x4a0f6000 0x1000>; | |
395 | ti,hwmods = "spinlock"; | |
34054213 | 396 | #hwlock-cells = <1>; |
fe0e09e4 SA |
397 | }; |
398 | ||
43286b11 FB |
399 | mcspi1: spi@48098000 { |
400 | compatible = "ti,omap4-mcspi"; | |
401 | reg = <0x48098000 0x200>; | |
8fea7d5a | 402 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
403 | #address-cells = <1>; |
404 | #size-cells = <0>; | |
405 | ti,hwmods = "mcspi1"; | |
406 | ti,spi-num-cs = <4>; | |
2c2dc545 JH |
407 | dmas = <&sdma 35>, |
408 | <&sdma 36>, | |
409 | <&sdma 37>, | |
410 | <&sdma 38>, | |
411 | <&sdma 39>, | |
412 | <&sdma 40>, | |
413 | <&sdma 41>, | |
414 | <&sdma 42>; | |
415 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
416 | "tx2", "rx2", "tx3", "rx3"; | |
43286b11 FB |
417 | }; |
418 | ||
419 | mcspi2: spi@4809a000 { | |
420 | compatible = "ti,omap4-mcspi"; | |
421 | reg = <0x4809a000 0x200>; | |
8fea7d5a | 422 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
423 | #address-cells = <1>; |
424 | #size-cells = <0>; | |
425 | ti,hwmods = "mcspi2"; | |
426 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
427 | dmas = <&sdma 43>, |
428 | <&sdma 44>, | |
429 | <&sdma 45>, | |
430 | <&sdma 46>; | |
431 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
43286b11 FB |
432 | }; |
433 | ||
434 | mcspi3: spi@480b8000 { | |
435 | compatible = "ti,omap4-mcspi"; | |
436 | reg = <0x480b8000 0x200>; | |
8fea7d5a | 437 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
438 | #address-cells = <1>; |
439 | #size-cells = <0>; | |
440 | ti,hwmods = "mcspi3"; | |
441 | ti,spi-num-cs = <2>; | |
2c2dc545 JH |
442 | dmas = <&sdma 15>, <&sdma 16>; |
443 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
444 | }; |
445 | ||
446 | mcspi4: spi@480ba000 { | |
447 | compatible = "ti,omap4-mcspi"; | |
448 | reg = <0x480ba000 0x200>; | |
8fea7d5a | 449 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
43286b11 FB |
450 | #address-cells = <1>; |
451 | #size-cells = <0>; | |
452 | ti,hwmods = "mcspi4"; | |
453 | ti,spi-num-cs = <1>; | |
2c2dc545 JH |
454 | dmas = <&sdma 70>, <&sdma 71>; |
455 | dma-names = "tx0", "rx0"; | |
43286b11 FB |
456 | }; |
457 | ||
6b5de091 S |
458 | uart1: serial@4806a000 { |
459 | compatible = "ti,omap4-uart"; | |
8e80f660 | 460 | reg = <0x4806a000 0x100>; |
e2265abe | 461 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
462 | ti,hwmods = "uart1"; |
463 | clock-frequency = <48000000>; | |
464 | }; | |
465 | ||
466 | uart2: serial@4806c000 { | |
467 | compatible = "ti,omap4-uart"; | |
8e80f660 | 468 | reg = <0x4806c000 0x100>; |
e2265abe | 469 | interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
470 | ti,hwmods = "uart2"; |
471 | clock-frequency = <48000000>; | |
472 | }; | |
473 | ||
474 | uart3: serial@48020000 { | |
475 | compatible = "ti,omap4-uart"; | |
8e80f660 | 476 | reg = <0x48020000 0x100>; |
e2265abe | 477 | interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
478 | ti,hwmods = "uart3"; |
479 | clock-frequency = <48000000>; | |
480 | }; | |
481 | ||
482 | uart4: serial@4806e000 { | |
483 | compatible = "ti,omap4-uart"; | |
8e80f660 | 484 | reg = <0x4806e000 0x100>; |
e2265abe | 485 | interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
486 | ti,hwmods = "uart4"; |
487 | clock-frequency = <48000000>; | |
488 | }; | |
489 | ||
490 | uart5: serial@48066000 { | |
8e80f660 SG |
491 | compatible = "ti,omap4-uart"; |
492 | reg = <0x48066000 0x100>; | |
e2265abe | 493 | interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
494 | ti,hwmods = "uart5"; |
495 | clock-frequency = <48000000>; | |
496 | }; | |
497 | ||
498 | uart6: serial@48068000 { | |
8e80f660 SG |
499 | compatible = "ti,omap4-uart"; |
500 | reg = <0x48068000 0x100>; | |
e2265abe | 501 | interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
6b5de091 S |
502 | ti,hwmods = "uart6"; |
503 | clock-frequency = <48000000>; | |
504 | }; | |
5dd18b01 B |
505 | |
506 | mmc1: mmc@4809c000 { | |
507 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 508 | reg = <0x4809c000 0x400>; |
8fea7d5a | 509 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
510 | ti,hwmods = "mmc1"; |
511 | ti,dual-volt; | |
512 | ti,needs-special-reset; | |
2c2dc545 JH |
513 | dmas = <&sdma 61>, <&sdma 62>; |
514 | dma-names = "tx", "rx"; | |
cd042fe5 | 515 | pbias-supply = <&pbias_mmc_reg>; |
5dd18b01 B |
516 | }; |
517 | ||
518 | mmc2: mmc@480b4000 { | |
519 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 520 | reg = <0x480b4000 0x400>; |
8fea7d5a | 521 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
522 | ti,hwmods = "mmc2"; |
523 | ti,needs-special-reset; | |
2c2dc545 JH |
524 | dmas = <&sdma 47>, <&sdma 48>; |
525 | dma-names = "tx", "rx"; | |
5dd18b01 B |
526 | }; |
527 | ||
528 | mmc3: mmc@480ad000 { | |
529 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 530 | reg = <0x480ad000 0x400>; |
8fea7d5a | 531 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
532 | ti,hwmods = "mmc3"; |
533 | ti,needs-special-reset; | |
2c2dc545 JH |
534 | dmas = <&sdma 77>, <&sdma 78>; |
535 | dma-names = "tx", "rx"; | |
5dd18b01 B |
536 | }; |
537 | ||
538 | mmc4: mmc@480d1000 { | |
539 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 540 | reg = <0x480d1000 0x400>; |
8fea7d5a | 541 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
542 | ti,hwmods = "mmc4"; |
543 | ti,needs-special-reset; | |
2c2dc545 JH |
544 | dmas = <&sdma 57>, <&sdma 58>; |
545 | dma-names = "tx", "rx"; | |
5dd18b01 B |
546 | }; |
547 | ||
548 | mmc5: mmc@480d5000 { | |
549 | compatible = "ti,omap4-hsmmc"; | |
9a642362 | 550 | reg = <0x480d5000 0x400>; |
8fea7d5a | 551 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
5dd18b01 B |
552 | ti,hwmods = "mmc5"; |
553 | ti,needs-special-reset; | |
2c2dc545 JH |
554 | dmas = <&sdma 59>, <&sdma 60>; |
555 | dma-names = "tx", "rx"; | |
5dd18b01 | 556 | }; |
5449fbc2 | 557 | |
2dcfa56e SA |
558 | mmu_dsp: mmu@4a066000 { |
559 | compatible = "ti,omap4-iommu"; | |
560 | reg = <0x4a066000 0x100>; | |
561 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
562 | ti,hwmods = "mmu_dsp"; | |
563 | }; | |
564 | ||
565 | mmu_ipu: mmu@55082000 { | |
566 | compatible = "ti,omap4-iommu"; | |
567 | reg = <0x55082000 0x100>; | |
568 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
569 | ti,hwmods = "mmu_ipu"; | |
570 | ti,iommu-bus-err-back; | |
571 | }; | |
572 | ||
5449fbc2 SP |
573 | keypad: keypad@4ae1c000 { |
574 | compatible = "ti,omap4-keypad"; | |
8cc8b89f | 575 | reg = <0x4ae1c000 0x400>; |
5449fbc2 SP |
576 | ti,hwmods = "kbd"; |
577 | }; | |
ffd5db24 | 578 | |
cbb57f07 PU |
579 | mcpdm: mcpdm@40132000 { |
580 | compatible = "ti,omap4-mcpdm"; | |
581 | reg = <0x40132000 0x7f>, /* MPU private access */ | |
582 | <0x49032000 0x7f>; /* L3 Interconnect */ | |
583 | reg-names = "mpu", "dma"; | |
8fea7d5a | 584 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 585 | ti,hwmods = "mcpdm"; |
4e4ead73 SG |
586 | dmas = <&sdma 65>, |
587 | <&sdma 66>; | |
588 | dma-names = "up_link", "dn_link"; | |
f15534ea | 589 | status = "disabled"; |
cbb57f07 PU |
590 | }; |
591 | ||
592 | dmic: dmic@4012e000 { | |
593 | compatible = "ti,omap4-dmic"; | |
594 | reg = <0x4012e000 0x7f>, /* MPU private access */ | |
595 | <0x4902e000 0x7f>; /* L3 Interconnect */ | |
596 | reg-names = "mpu", "dma"; | |
8fea7d5a | 597 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
cbb57f07 | 598 | ti,hwmods = "dmic"; |
4e4ead73 SG |
599 | dmas = <&sdma 67>; |
600 | dma-names = "up_link"; | |
f15534ea | 601 | status = "disabled"; |
cbb57f07 PU |
602 | }; |
603 | ||
ffd5db24 PU |
604 | mcbsp1: mcbsp@40122000 { |
605 | compatible = "ti,omap4-mcbsp"; | |
606 | reg = <0x40122000 0xff>, /* MPU private access */ | |
607 | <0x49022000 0xff>; /* L3 Interconnect */ | |
608 | reg-names = "mpu", "dma"; | |
8fea7d5a | 609 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 610 | interrupt-names = "common"; |
ffd5db24 PU |
611 | ti,buffer-size = <128>; |
612 | ti,hwmods = "mcbsp1"; | |
4e4ead73 SG |
613 | dmas = <&sdma 33>, |
614 | <&sdma 34>; | |
615 | dma-names = "tx", "rx"; | |
f15534ea | 616 | status = "disabled"; |
ffd5db24 PU |
617 | }; |
618 | ||
619 | mcbsp2: mcbsp@40124000 { | |
620 | compatible = "ti,omap4-mcbsp"; | |
621 | reg = <0x40124000 0xff>, /* MPU private access */ | |
622 | <0x49024000 0xff>; /* L3 Interconnect */ | |
623 | reg-names = "mpu", "dma"; | |
8fea7d5a | 624 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 625 | interrupt-names = "common"; |
ffd5db24 PU |
626 | ti,buffer-size = <128>; |
627 | ti,hwmods = "mcbsp2"; | |
4e4ead73 SG |
628 | dmas = <&sdma 17>, |
629 | <&sdma 18>; | |
630 | dma-names = "tx", "rx"; | |
f15534ea | 631 | status = "disabled"; |
ffd5db24 PU |
632 | }; |
633 | ||
634 | mcbsp3: mcbsp@40126000 { | |
635 | compatible = "ti,omap4-mcbsp"; | |
636 | reg = <0x40126000 0xff>, /* MPU private access */ | |
637 | <0x49026000 0xff>; /* L3 Interconnect */ | |
638 | reg-names = "mpu", "dma"; | |
8fea7d5a | 639 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
ffd5db24 | 640 | interrupt-names = "common"; |
ffd5db24 PU |
641 | ti,buffer-size = <128>; |
642 | ti,hwmods = "mcbsp3"; | |
4e4ead73 SG |
643 | dmas = <&sdma 19>, |
644 | <&sdma 20>; | |
645 | dma-names = "tx", "rx"; | |
f15534ea | 646 | status = "disabled"; |
ffd5db24 | 647 | }; |
df692a92 | 648 | |
84d89c31 SA |
649 | mailbox: mailbox@4a0f4000 { |
650 | compatible = "ti,omap4-mailbox"; | |
651 | reg = <0x4a0f4000 0x200>; | |
652 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
653 | ti,hwmods = "mailbox"; | |
24df0453 | 654 | #mbox-cells = <1>; |
41ffada1 SA |
655 | ti,mbox-num-users = <3>; |
656 | ti,mbox-num-fifos = <8>; | |
d27704d1 SA |
657 | mbox_ipu: mbox_ipu { |
658 | ti,mbox-tx = <0 0 0>; | |
659 | ti,mbox-rx = <1 0 0>; | |
660 | }; | |
661 | mbox_dsp: mbox_dsp { | |
662 | ti,mbox-tx = <3 0 0>; | |
663 | ti,mbox-rx = <2 0 0>; | |
664 | }; | |
84d89c31 SA |
665 | }; |
666 | ||
df692a92 | 667 | timer1: timer@4ae18000 { |
002e1ec5 | 668 | compatible = "ti,omap5430-timer"; |
df692a92 | 669 | reg = <0x4ae18000 0x80>; |
8fea7d5a | 670 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
671 | ti,hwmods = "timer1"; |
672 | ti,timer-alwon; | |
673 | }; | |
674 | ||
675 | timer2: timer@48032000 { | |
002e1ec5 | 676 | compatible = "ti,omap5430-timer"; |
df692a92 | 677 | reg = <0x48032000 0x80>; |
8fea7d5a | 678 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
679 | ti,hwmods = "timer2"; |
680 | }; | |
681 | ||
682 | timer3: timer@48034000 { | |
002e1ec5 | 683 | compatible = "ti,omap5430-timer"; |
df692a92 | 684 | reg = <0x48034000 0x80>; |
8fea7d5a | 685 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
686 | ti,hwmods = "timer3"; |
687 | }; | |
688 | ||
689 | timer4: timer@48036000 { | |
002e1ec5 | 690 | compatible = "ti,omap5430-timer"; |
df692a92 | 691 | reg = <0x48036000 0x80>; |
8fea7d5a | 692 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
693 | ti,hwmods = "timer4"; |
694 | }; | |
695 | ||
696 | timer5: timer@40138000 { | |
002e1ec5 | 697 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
698 | reg = <0x40138000 0x80>, |
699 | <0x49038000 0x80>; | |
8fea7d5a | 700 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
701 | ti,hwmods = "timer5"; |
702 | ti,timer-dsp; | |
8341613a | 703 | ti,timer-pwm; |
df692a92 JH |
704 | }; |
705 | ||
706 | timer6: timer@4013a000 { | |
002e1ec5 | 707 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
708 | reg = <0x4013a000 0x80>, |
709 | <0x4903a000 0x80>; | |
8fea7d5a | 710 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
711 | ti,hwmods = "timer6"; |
712 | ti,timer-dsp; | |
713 | ti,timer-pwm; | |
714 | }; | |
715 | ||
716 | timer7: timer@4013c000 { | |
002e1ec5 | 717 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
718 | reg = <0x4013c000 0x80>, |
719 | <0x4903c000 0x80>; | |
8fea7d5a | 720 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
721 | ti,hwmods = "timer7"; |
722 | ti,timer-dsp; | |
723 | }; | |
724 | ||
725 | timer8: timer@4013e000 { | |
002e1ec5 | 726 | compatible = "ti,omap5430-timer"; |
df692a92 JH |
727 | reg = <0x4013e000 0x80>, |
728 | <0x4903e000 0x80>; | |
8fea7d5a | 729 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
730 | ti,hwmods = "timer8"; |
731 | ti,timer-dsp; | |
732 | ti,timer-pwm; | |
733 | }; | |
734 | ||
735 | timer9: timer@4803e000 { | |
002e1ec5 | 736 | compatible = "ti,omap5430-timer"; |
df692a92 | 737 | reg = <0x4803e000 0x80>; |
8fea7d5a | 738 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 739 | ti,hwmods = "timer9"; |
8341613a | 740 | ti,timer-pwm; |
df692a92 JH |
741 | }; |
742 | ||
743 | timer10: timer@48086000 { | |
002e1ec5 | 744 | compatible = "ti,omap5430-timer"; |
df692a92 | 745 | reg = <0x48086000 0x80>; |
8fea7d5a | 746 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 | 747 | ti,hwmods = "timer10"; |
8341613a | 748 | ti,timer-pwm; |
df692a92 JH |
749 | }; |
750 | ||
751 | timer11: timer@48088000 { | |
002e1ec5 | 752 | compatible = "ti,omap5430-timer"; |
df692a92 | 753 | reg = <0x48088000 0x80>; |
8fea7d5a | 754 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
df692a92 JH |
755 | ti,hwmods = "timer11"; |
756 | ti,timer-pwm; | |
757 | }; | |
e6900ddf | 758 | |
55452197 LV |
759 | wdt2: wdt@4ae14000 { |
760 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | |
761 | reg = <0x4ae14000 0x80>; | |
8fea7d5a | 762 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
55452197 LV |
763 | ti,hwmods = "wd_timer2"; |
764 | }; | |
765 | ||
1a5fe3ca AT |
766 | dmm@4e000000 { |
767 | compatible = "ti,omap5-dmm"; | |
768 | reg = <0x4e000000 0x800>; | |
769 | interrupts = <0 113 0x4>; | |
770 | ti,hwmods = "dmm"; | |
771 | }; | |
772 | ||
8906d654 | 773 | emif1: emif@4c000000 { |
e6900ddf LV |
774 | compatible = "ti,emif-4d5"; |
775 | ti,hwmods = "emif1"; | |
f12ecbe2 | 776 | ti,no-idle-on-init; |
e6900ddf LV |
777 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
778 | reg = <0x4c000000 0x400>; | |
8fea7d5a | 779 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
780 | hw-caps-read-idle-ctrl; |
781 | hw-caps-ll-interface; | |
782 | hw-caps-temp-alert; | |
783 | }; | |
784 | ||
8906d654 | 785 | emif2: emif@4d000000 { |
e6900ddf LV |
786 | compatible = "ti,emif-4d5"; |
787 | ti,hwmods = "emif2"; | |
f12ecbe2 | 788 | ti,no-idle-on-init; |
e6900ddf LV |
789 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
790 | reg = <0x4d000000 0x400>; | |
8fea7d5a | 791 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
e6900ddf LV |
792 | hw-caps-read-idle-ctrl; |
793 | hw-caps-ll-interface; | |
794 | hw-caps-temp-alert; | |
795 | }; | |
fedc428e | 796 | |
b297c292 RQ |
797 | omap_control_usb2phy: control-phy@4a002300 { |
798 | compatible = "ti,control-phy-usb2"; | |
799 | reg = <0x4a002300 0x4>; | |
800 | reg-names = "power"; | |
801 | }; | |
802 | ||
803 | omap_control_usb3phy: control-phy@4a002370 { | |
804 | compatible = "ti,control-phy-pipe3"; | |
805 | reg = <0x4a002370 0x4>; | |
806 | reg-names = "power"; | |
fedc428e | 807 | }; |
e9831967 | 808 | |
e3a412c9 | 809 | usb3: omap_dwc3@4a020000 { |
72f6f957 KVA |
810 | compatible = "ti,dwc3"; |
811 | ti,hwmods = "usb_otg_ss"; | |
6f61ee23 | 812 | reg = <0x4a020000 0x10000>; |
8fea7d5a | 813 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
72f6f957 KVA |
814 | #address-cells = <1>; |
815 | #size-cells = <1>; | |
816 | utmi-mode = <2>; | |
817 | ranges; | |
818 | dwc3@4a030000 { | |
22a5aa17 | 819 | compatible = "snps,dwc3"; |
6f61ee23 | 820 | reg = <0x4a030000 0x10000>; |
8fea7d5a | 821 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
073addc8 KVA |
822 | phys = <&usb2_phy>, <&usb3_phy>; |
823 | phy-names = "usb2-phy", "usb3-phy"; | |
c47ee6ee | 824 | dr_mode = "peripheral"; |
72f6f957 KVA |
825 | tx-fifo-resize; |
826 | }; | |
827 | }; | |
828 | ||
b6731f78 | 829 | ocp2scp@4a080000 { |
e9831967 KVA |
830 | compatible = "ti,omap-ocp2scp"; |
831 | #address-cells = <1>; | |
832 | #size-cells = <1>; | |
b6731f78 | 833 | reg = <0x4a080000 0x20>; |
e9831967 KVA |
834 | ranges; |
835 | ti,hwmods = "ocp2scp1"; | |
ae6a32d2 KVA |
836 | usb2_phy: usb2phy@4a084000 { |
837 | compatible = "ti,omap-usb2"; | |
838 | reg = <0x4a084000 0x7c>; | |
b297c292 | 839 | ctrl-module = <&omap_control_usb2phy>; |
c65d0ad5 RQ |
840 | clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; |
841 | clock-names = "wkupclk", "refclk"; | |
073addc8 | 842 | #phy-cells = <0>; |
ae6a32d2 KVA |
843 | }; |
844 | ||
845 | usb3_phy: usb3phy@4a084400 { | |
846 | compatible = "ti,omap-usb3"; | |
847 | reg = <0x4a084400 0x80>, | |
848 | <0x4a084800 0x64>, | |
849 | <0x4a084c00 0x40>; | |
850 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
b297c292 | 851 | ctrl-module = <&omap_control_usb3phy>; |
ada76576 RQ |
852 | clocks = <&usb_phy_cm_clk32k>, |
853 | <&sys_clkin>, | |
854 | <&usb_otg_ss_refclk960m>; | |
855 | clock-names = "wkupclk", | |
856 | "sysclk", | |
857 | "refclk"; | |
073addc8 | 858 | #phy-cells = <0>; |
ae6a32d2 | 859 | }; |
e9831967 | 860 | }; |
ed7f8e8a RQ |
861 | |
862 | usbhstll: usbhstll@4a062000 { | |
863 | compatible = "ti,usbhs-tll"; | |
864 | reg = <0x4a062000 0x1000>; | |
865 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
866 | ti,hwmods = "usb_tll_hs"; | |
867 | }; | |
868 | ||
869 | usbhshost: usbhshost@4a064000 { | |
870 | compatible = "ti,usbhs-host"; | |
871 | reg = <0x4a064000 0x800>; | |
872 | ti,hwmods = "usb_host_hs"; | |
873 | #address-cells = <1>; | |
874 | #size-cells = <1>; | |
875 | ranges; | |
051fc06d RQ |
876 | clocks = <&l3init_60m_fclk>, |
877 | <&xclk60mhsp1_ck>, | |
878 | <&xclk60mhsp2_ck>; | |
879 | clock-names = "refclk_60m_int", | |
880 | "refclk_60m_ext_p1", | |
881 | "refclk_60m_ext_p2"; | |
ed7f8e8a RQ |
882 | |
883 | usbhsohci: ohci@4a064800 { | |
a2525e54 | 884 | compatible = "ti,ohci-omap3"; |
ed7f8e8a RQ |
885 | reg = <0x4a064800 0x400>; |
886 | interrupt-parent = <&gic>; | |
887 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
888 | }; | |
889 | ||
890 | usbhsehci: ehci@4a064c00 { | |
a2525e54 | 891 | compatible = "ti,ehci-omap"; |
ed7f8e8a RQ |
892 | reg = <0x4a064c00 0x400>; |
893 | interrupt-parent = <&gic>; | |
894 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
895 | }; | |
896 | }; | |
cbad26db | 897 | |
1b761fc5 | 898 | bandgap: bandgap@4a0021e0 { |
cbad26db EV |
899 | reg = <0x4a0021e0 0xc |
900 | 0x4a00232c 0xc | |
901 | 0x4a002380 0x2c | |
902 | 0x4a0023C0 0x3c>; | |
903 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
904 | compatible = "ti,omap5430-bandgap"; | |
1b761fc5 EV |
905 | |
906 | #thermal-sensor-cells = <1>; | |
cbad26db | 907 | }; |
4f82952c B |
908 | |
909 | omap_control_sata: control-phy@4a002374 { | |
910 | compatible = "ti,control-phy-pipe3"; | |
911 | reg = <0x4a002374 0x4>; | |
912 | reg-names = "power"; | |
913 | clocks = <&sys_clkin>; | |
914 | clock-names = "sysclk"; | |
915 | }; | |
916 | ||
917 | /* OCP2SCP3 */ | |
918 | ocp2scp@4a090000 { | |
919 | compatible = "ti,omap-ocp2scp"; | |
920 | #address-cells = <1>; | |
921 | #size-cells = <1>; | |
922 | reg = <0x4a090000 0x20>; | |
923 | ranges; | |
924 | ti,hwmods = "ocp2scp3"; | |
925 | sata_phy: phy@4a096000 { | |
926 | compatible = "ti,phy-pipe3-sata"; | |
927 | reg = <0x4A096000 0x80>, /* phy_rx */ | |
928 | <0x4A096400 0x64>, /* phy_tx */ | |
929 | <0x4A096800 0x40>; /* pll_ctrl */ | |
930 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
931 | ctrl-module = <&omap_control_sata>; | |
a0182724 RQ |
932 | clocks = <&sys_clkin>, <&sata_ref_clk>; |
933 | clock-names = "sysclk", "refclk"; | |
4f82952c B |
934 | #phy-cells = <0>; |
935 | }; | |
936 | }; | |
937 | ||
938 | sata: sata@4a141100 { | |
939 | compatible = "snps,dwc-ahci"; | |
940 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; | |
941 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
942 | phys = <&sata_phy>; | |
943 | phy-names = "sata-phy"; | |
944 | clocks = <&sata_ref_clk>; | |
945 | ti,hwmods = "sata"; | |
946 | }; | |
947 | ||
e7585c4f TV |
948 | dss: dss@58000000 { |
949 | compatible = "ti,omap5-dss"; | |
950 | reg = <0x58000000 0x80>; | |
951 | status = "disabled"; | |
952 | ti,hwmods = "dss_core"; | |
953 | clocks = <&dss_dss_clk>; | |
954 | clock-names = "fck"; | |
955 | #address-cells = <1>; | |
956 | #size-cells = <1>; | |
957 | ranges; | |
958 | ||
959 | dispc@58001000 { | |
960 | compatible = "ti,omap5-dispc"; | |
961 | reg = <0x58001000 0x1000>; | |
962 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
963 | ti,hwmods = "dss_dispc"; | |
964 | clocks = <&dss_dss_clk>; | |
965 | clock-names = "fck"; | |
966 | }; | |
967 | ||
84ace674 TV |
968 | rfbi: encoder@58002000 { |
969 | compatible = "ti,omap5-rfbi"; | |
970 | reg = <0x58002000 0x100>; | |
971 | status = "disabled"; | |
972 | ti,hwmods = "dss_rfbi"; | |
973 | clocks = <&dss_dss_clk>, <&l3_iclk_div>; | |
974 | clock-names = "fck", "ick"; | |
975 | }; | |
976 | ||
e7585c4f TV |
977 | dsi1: encoder@58004000 { |
978 | compatible = "ti,omap5-dsi"; | |
979 | reg = <0x58004000 0x200>, | |
980 | <0x58004200 0x40>, | |
981 | <0x58004300 0x40>; | |
982 | reg-names = "proto", "phy", "pll"; | |
983 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
984 | status = "disabled"; | |
985 | ti,hwmods = "dss_dsi1"; | |
986 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
987 | clock-names = "fck", "sys_clk"; | |
988 | }; | |
989 | ||
990 | dsi2: encoder@58005000 { | |
991 | compatible = "ti,omap5-dsi"; | |
992 | reg = <0x58009000 0x200>, | |
993 | <0x58009200 0x40>, | |
994 | <0x58009300 0x40>; | |
995 | reg-names = "proto", "phy", "pll"; | |
996 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
997 | status = "disabled"; | |
998 | ti,hwmods = "dss_dsi2"; | |
999 | clocks = <&dss_dss_clk>, <&dss_sys_clk>; | |
1000 | clock-names = "fck", "sys_clk"; | |
1001 | }; | |
1002 | ||
1003 | hdmi: encoder@58060000 { | |
1004 | compatible = "ti,omap5-hdmi"; | |
1005 | reg = <0x58040000 0x200>, | |
1006 | <0x58040200 0x80>, | |
1007 | <0x58040300 0x80>, | |
1008 | <0x58060000 0x19000>; | |
1009 | reg-names = "wp", "pll", "phy", "core"; | |
1010 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1011 | status = "disabled"; | |
1012 | ti,hwmods = "dss_hdmi"; | |
1013 | clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; | |
1014 | clock-names = "fck", "sys_clk"; | |
7d0fde39 JS |
1015 | dmas = <&sdma 76>; |
1016 | dma-names = "audio_tx"; | |
e7585c4f TV |
1017 | }; |
1018 | }; | |
07b9b3d9 AT |
1019 | |
1020 | abb_mpu: regulator-abb-mpu { | |
1021 | compatible = "ti,abb-v2"; | |
1022 | regulator-name = "abb_mpu"; | |
1023 | #address-cells = <0>; | |
1024 | #size-cells = <0>; | |
1025 | clocks = <&sys_clkin>; | |
1026 | ti,settling-time = <50>; | |
1027 | ti,clock-cycles = <16>; | |
1028 | ||
1029 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, | |
1030 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; | |
1031 | reg-names = "base-address", "int-address", | |
1032 | "efuse-address", "ldo-address"; | |
1033 | ti,tranxdone-status-mask = <0x80>; | |
1034 | /* LDOVBBMPU_MUX_CTRL */ | |
1035 | ti,ldovbb-override-mask = <0x400>; | |
1036 | /* LDOVBBMPU_VSET_OUT */ | |
1037 | ti,ldovbb-vset-mask = <0x1F>; | |
1038 | ||
1039 | /* | |
1040 | * NOTE: only FBB mode used but actual vset will | |
1041 | * determine final biasing | |
1042 | */ | |
1043 | ti,abb_info = < | |
1044 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1045 | 1060000 0 0x0 0 0x02000000 0x01F00000 | |
1046 | 1250000 0 0x4 0 0x02000000 0x01F00000 | |
1047 | >; | |
1048 | }; | |
1049 | ||
1050 | abb_mm: regulator-abb-mm { | |
1051 | compatible = "ti,abb-v2"; | |
1052 | regulator-name = "abb_mm"; | |
1053 | #address-cells = <0>; | |
1054 | #size-cells = <0>; | |
1055 | clocks = <&sys_clkin>; | |
1056 | ti,settling-time = <50>; | |
1057 | ti,clock-cycles = <16>; | |
1058 | ||
1059 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, | |
1060 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; | |
1061 | reg-names = "base-address", "int-address", | |
1062 | "efuse-address", "ldo-address"; | |
1063 | ti,tranxdone-status-mask = <0x80000000>; | |
1064 | /* LDOVBBMM_MUX_CTRL */ | |
1065 | ti,ldovbb-override-mask = <0x400>; | |
1066 | /* LDOVBBMM_VSET_OUT */ | |
1067 | ti,ldovbb-vset-mask = <0x1F>; | |
1068 | ||
1069 | /* | |
1070 | * NOTE: only FBB mode used but actual vset will | |
1071 | * determine final biasing | |
1072 | */ | |
1073 | ti,abb_info = < | |
1074 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | |
1075 | 1025000 0 0x0 0 0x02000000 0x01F00000 | |
1076 | 1120000 0 0x4 0 0x02000000 0x01F00000 | |
1077 | >; | |
1078 | }; | |
6b5de091 S |
1079 | }; |
1080 | }; | |
85dc74e9 | 1081 | |
38f5c8ba TK |
1082 | &cpu_thermal { |
1083 | polling-delay = <500>; /* milliseconds */ | |
1084 | }; | |
1085 | ||
85dc74e9 | 1086 | /include/ "omap54xx-clocks.dtsi" |