Commit | Line | Data |
---|---|---|
85dc74e9 TK |
1 | /* |
2 | * Device Tree Source for OMAP5 clock data | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | &cm_core_aon_clocks { | |
11 | pad_clks_src_ck: pad_clks_src_ck { | |
12 | #clock-cells = <0>; | |
13 | compatible = "fixed-clock"; | |
14 | clock-frequency = <12000000>; | |
15 | }; | |
16 | ||
17 | pad_clks_ck: pad_clks_ck { | |
18 | #clock-cells = <0>; | |
19 | compatible = "ti,gate-clock"; | |
20 | clocks = <&pad_clks_src_ck>; | |
21 | ti,bit-shift = <8>; | |
22 | reg = <0x0108>; | |
23 | }; | |
24 | ||
25 | secure_32k_clk_src_ck: secure_32k_clk_src_ck { | |
26 | #clock-cells = <0>; | |
27 | compatible = "fixed-clock"; | |
28 | clock-frequency = <32768>; | |
29 | }; | |
30 | ||
31 | slimbus_src_clk: slimbus_src_clk { | |
32 | #clock-cells = <0>; | |
33 | compatible = "fixed-clock"; | |
34 | clock-frequency = <12000000>; | |
35 | }; | |
36 | ||
37 | slimbus_clk: slimbus_clk { | |
38 | #clock-cells = <0>; | |
39 | compatible = "ti,gate-clock"; | |
40 | clocks = <&slimbus_src_clk>; | |
41 | ti,bit-shift = <10>; | |
42 | reg = <0x0108>; | |
43 | }; | |
44 | ||
45 | sys_32k_ck: sys_32k_ck { | |
46 | #clock-cells = <0>; | |
47 | compatible = "fixed-clock"; | |
48 | clock-frequency = <32768>; | |
49 | }; | |
50 | ||
51 | virt_12000000_ck: virt_12000000_ck { | |
52 | #clock-cells = <0>; | |
53 | compatible = "fixed-clock"; | |
54 | clock-frequency = <12000000>; | |
55 | }; | |
56 | ||
57 | virt_13000000_ck: virt_13000000_ck { | |
58 | #clock-cells = <0>; | |
59 | compatible = "fixed-clock"; | |
60 | clock-frequency = <13000000>; | |
61 | }; | |
62 | ||
63 | virt_16800000_ck: virt_16800000_ck { | |
64 | #clock-cells = <0>; | |
65 | compatible = "fixed-clock"; | |
66 | clock-frequency = <16800000>; | |
67 | }; | |
68 | ||
69 | virt_19200000_ck: virt_19200000_ck { | |
70 | #clock-cells = <0>; | |
71 | compatible = "fixed-clock"; | |
72 | clock-frequency = <19200000>; | |
73 | }; | |
74 | ||
75 | virt_26000000_ck: virt_26000000_ck { | |
76 | #clock-cells = <0>; | |
77 | compatible = "fixed-clock"; | |
78 | clock-frequency = <26000000>; | |
79 | }; | |
80 | ||
81 | virt_27000000_ck: virt_27000000_ck { | |
82 | #clock-cells = <0>; | |
83 | compatible = "fixed-clock"; | |
84 | clock-frequency = <27000000>; | |
85 | }; | |
86 | ||
87 | virt_38400000_ck: virt_38400000_ck { | |
88 | #clock-cells = <0>; | |
89 | compatible = "fixed-clock"; | |
90 | clock-frequency = <38400000>; | |
91 | }; | |
92 | ||
93 | xclk60mhsp1_ck: xclk60mhsp1_ck { | |
94 | #clock-cells = <0>; | |
95 | compatible = "fixed-clock"; | |
96 | clock-frequency = <60000000>; | |
97 | }; | |
98 | ||
99 | xclk60mhsp2_ck: xclk60mhsp2_ck { | |
100 | #clock-cells = <0>; | |
101 | compatible = "fixed-clock"; | |
102 | clock-frequency = <60000000>; | |
103 | }; | |
104 | ||
105 | dpll_abe_ck: dpll_abe_ck { | |
106 | #clock-cells = <0>; | |
107 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
108 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
109 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
110 | }; | |
111 | ||
112 | dpll_abe_x2_ck: dpll_abe_x2_ck { | |
113 | #clock-cells = <0>; | |
114 | compatible = "ti,omap4-dpll-x2-clock"; | |
115 | clocks = <&dpll_abe_ck>; | |
116 | }; | |
117 | ||
118 | dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { | |
119 | #clock-cells = <0>; | |
120 | compatible = "ti,divider-clock"; | |
121 | clocks = <&dpll_abe_x2_ck>; | |
122 | ti,max-div = <31>; | |
85dc74e9 TK |
123 | reg = <0x01f0>; |
124 | ti,index-starts-at-one; | |
85dc74e9 TK |
125 | }; |
126 | ||
127 | abe_24m_fclk: abe_24m_fclk { | |
128 | #clock-cells = <0>; | |
129 | compatible = "fixed-factor-clock"; | |
130 | clocks = <&dpll_abe_m2x2_ck>; | |
131 | clock-mult = <1>; | |
132 | clock-div = <8>; | |
133 | }; | |
134 | ||
135 | abe_clk: abe_clk { | |
136 | #clock-cells = <0>; | |
137 | compatible = "ti,divider-clock"; | |
138 | clocks = <&dpll_abe_m2x2_ck>; | |
139 | ti,max-div = <4>; | |
140 | reg = <0x0108>; | |
141 | ti,index-power-of-two; | |
142 | }; | |
143 | ||
144 | abe_iclk: abe_iclk { | |
145 | #clock-cells = <0>; | |
0922b339 PU |
146 | compatible = "ti,divider-clock"; |
147 | clocks = <&aess_fclk>; | |
148 | ti,bit-shift = <24>; | |
149 | reg = <0x0528>; | |
150 | ti,dividers = <2>, <1>; | |
85dc74e9 TK |
151 | }; |
152 | ||
153 | abe_lp_clk_div: abe_lp_clk_div { | |
154 | #clock-cells = <0>; | |
155 | compatible = "fixed-factor-clock"; | |
156 | clocks = <&dpll_abe_m2x2_ck>; | |
157 | clock-mult = <1>; | |
158 | clock-div = <16>; | |
159 | }; | |
160 | ||
161 | dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { | |
162 | #clock-cells = <0>; | |
163 | compatible = "ti,divider-clock"; | |
164 | clocks = <&dpll_abe_x2_ck>; | |
165 | ti,max-div = <31>; | |
85dc74e9 TK |
166 | reg = <0x01f4>; |
167 | ti,index-starts-at-one; | |
85dc74e9 TK |
168 | }; |
169 | ||
170 | dpll_core_ck: dpll_core_ck { | |
171 | #clock-cells = <0>; | |
172 | compatible = "ti,omap4-dpll-core-clock"; | |
173 | clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; | |
174 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; | |
175 | }; | |
176 | ||
177 | dpll_core_x2_ck: dpll_core_x2_ck { | |
178 | #clock-cells = <0>; | |
179 | compatible = "ti,omap4-dpll-x2-clock"; | |
180 | clocks = <&dpll_core_ck>; | |
181 | }; | |
182 | ||
183 | dpll_core_h21x2_ck: dpll_core_h21x2_ck { | |
184 | #clock-cells = <0>; | |
185 | compatible = "ti,divider-clock"; | |
186 | clocks = <&dpll_core_x2_ck>; | |
187 | ti,max-div = <63>; | |
85dc74e9 TK |
188 | reg = <0x0150>; |
189 | ti,index-starts-at-one; | |
85dc74e9 TK |
190 | }; |
191 | ||
192 | c2c_fclk: c2c_fclk { | |
193 | #clock-cells = <0>; | |
194 | compatible = "fixed-factor-clock"; | |
195 | clocks = <&dpll_core_h21x2_ck>; | |
196 | clock-mult = <1>; | |
197 | clock-div = <1>; | |
198 | }; | |
199 | ||
200 | c2c_iclk: c2c_iclk { | |
201 | #clock-cells = <0>; | |
202 | compatible = "fixed-factor-clock"; | |
203 | clocks = <&c2c_fclk>; | |
204 | clock-mult = <1>; | |
205 | clock-div = <2>; | |
206 | }; | |
207 | ||
208 | dpll_core_h11x2_ck: dpll_core_h11x2_ck { | |
209 | #clock-cells = <0>; | |
210 | compatible = "ti,divider-clock"; | |
211 | clocks = <&dpll_core_x2_ck>; | |
212 | ti,max-div = <63>; | |
85dc74e9 TK |
213 | reg = <0x0138>; |
214 | ti,index-starts-at-one; | |
85dc74e9 TK |
215 | }; |
216 | ||
217 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { | |
218 | #clock-cells = <0>; | |
219 | compatible = "ti,divider-clock"; | |
220 | clocks = <&dpll_core_x2_ck>; | |
221 | ti,max-div = <63>; | |
85dc74e9 TK |
222 | reg = <0x013c>; |
223 | ti,index-starts-at-one; | |
85dc74e9 TK |
224 | }; |
225 | ||
226 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { | |
227 | #clock-cells = <0>; | |
228 | compatible = "ti,divider-clock"; | |
229 | clocks = <&dpll_core_x2_ck>; | |
230 | ti,max-div = <63>; | |
85dc74e9 TK |
231 | reg = <0x0140>; |
232 | ti,index-starts-at-one; | |
85dc74e9 TK |
233 | }; |
234 | ||
235 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { | |
236 | #clock-cells = <0>; | |
237 | compatible = "ti,divider-clock"; | |
238 | clocks = <&dpll_core_x2_ck>; | |
239 | ti,max-div = <63>; | |
85dc74e9 TK |
240 | reg = <0x0144>; |
241 | ti,index-starts-at-one; | |
85dc74e9 TK |
242 | }; |
243 | ||
244 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { | |
245 | #clock-cells = <0>; | |
246 | compatible = "ti,divider-clock"; | |
247 | clocks = <&dpll_core_x2_ck>; | |
248 | ti,max-div = <63>; | |
85dc74e9 TK |
249 | reg = <0x0154>; |
250 | ti,index-starts-at-one; | |
85dc74e9 TK |
251 | }; |
252 | ||
253 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { | |
254 | #clock-cells = <0>; | |
255 | compatible = "ti,divider-clock"; | |
256 | clocks = <&dpll_core_x2_ck>; | |
257 | ti,max-div = <63>; | |
85dc74e9 TK |
258 | reg = <0x0158>; |
259 | ti,index-starts-at-one; | |
85dc74e9 TK |
260 | }; |
261 | ||
262 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { | |
263 | #clock-cells = <0>; | |
264 | compatible = "ti,divider-clock"; | |
265 | clocks = <&dpll_core_x2_ck>; | |
266 | ti,max-div = <63>; | |
85dc74e9 TK |
267 | reg = <0x015c>; |
268 | ti,index-starts-at-one; | |
85dc74e9 TK |
269 | }; |
270 | ||
271 | dpll_core_m2_ck: dpll_core_m2_ck { | |
272 | #clock-cells = <0>; | |
273 | compatible = "ti,divider-clock"; | |
274 | clocks = <&dpll_core_ck>; | |
275 | ti,max-div = <31>; | |
85dc74e9 TK |
276 | reg = <0x0130>; |
277 | ti,index-starts-at-one; | |
85dc74e9 TK |
278 | }; |
279 | ||
280 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { | |
281 | #clock-cells = <0>; | |
282 | compatible = "ti,divider-clock"; | |
283 | clocks = <&dpll_core_x2_ck>; | |
284 | ti,max-div = <31>; | |
85dc74e9 TK |
285 | reg = <0x0134>; |
286 | ti,index-starts-at-one; | |
85dc74e9 TK |
287 | }; |
288 | ||
289 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | |
290 | #clock-cells = <0>; | |
291 | compatible = "fixed-factor-clock"; | |
292 | clocks = <&dpll_core_h12x2_ck>; | |
293 | clock-mult = <1>; | |
294 | clock-div = <1>; | |
295 | }; | |
296 | ||
297 | dpll_iva_ck: dpll_iva_ck { | |
298 | #clock-cells = <0>; | |
299 | compatible = "ti,omap4-dpll-clock"; | |
300 | clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; | |
301 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; | |
302 | }; | |
303 | ||
304 | dpll_iva_x2_ck: dpll_iva_x2_ck { | |
305 | #clock-cells = <0>; | |
306 | compatible = "ti,omap4-dpll-x2-clock"; | |
307 | clocks = <&dpll_iva_ck>; | |
308 | }; | |
309 | ||
310 | dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { | |
311 | #clock-cells = <0>; | |
312 | compatible = "ti,divider-clock"; | |
313 | clocks = <&dpll_iva_x2_ck>; | |
314 | ti,max-div = <63>; | |
85dc74e9 TK |
315 | reg = <0x01b8>; |
316 | ti,index-starts-at-one; | |
85dc74e9 TK |
317 | }; |
318 | ||
319 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { | |
320 | #clock-cells = <0>; | |
321 | compatible = "ti,divider-clock"; | |
322 | clocks = <&dpll_iva_x2_ck>; | |
323 | ti,max-div = <63>; | |
85dc74e9 TK |
324 | reg = <0x01bc>; |
325 | ti,index-starts-at-one; | |
85dc74e9 TK |
326 | }; |
327 | ||
328 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | |
329 | #clock-cells = <0>; | |
330 | compatible = "fixed-factor-clock"; | |
331 | clocks = <&dpll_core_h12x2_ck>; | |
332 | clock-mult = <1>; | |
333 | clock-div = <1>; | |
334 | }; | |
335 | ||
336 | dpll_mpu_ck: dpll_mpu_ck { | |
337 | #clock-cells = <0>; | |
7e148070 | 338 | compatible = "ti,omap5-mpu-dpll-clock"; |
85dc74e9 TK |
339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; |
340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
341 | }; | |
342 | ||
343 | dpll_mpu_m2_ck: dpll_mpu_m2_ck { | |
344 | #clock-cells = <0>; | |
345 | compatible = "ti,divider-clock"; | |
346 | clocks = <&dpll_mpu_ck>; | |
347 | ti,max-div = <31>; | |
85dc74e9 TK |
348 | reg = <0x0170>; |
349 | ti,index-starts-at-one; | |
85dc74e9 TK |
350 | }; |
351 | ||
352 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | |
353 | #clock-cells = <0>; | |
354 | compatible = "fixed-factor-clock"; | |
355 | clocks = <&dpll_abe_m3x2_ck>; | |
356 | clock-mult = <1>; | |
357 | clock-div = <2>; | |
358 | }; | |
359 | ||
360 | usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { | |
361 | #clock-cells = <0>; | |
362 | compatible = "fixed-factor-clock"; | |
363 | clocks = <&dpll_abe_m3x2_ck>; | |
364 | clock-mult = <1>; | |
365 | clock-div = <3>; | |
366 | }; | |
367 | ||
368 | l3_iclk_div: l3_iclk_div { | |
369 | #clock-cells = <0>; | |
8fd46439 TK |
370 | compatible = "ti,divider-clock"; |
371 | ti,max-div = <2>; | |
372 | ti,bit-shift = <4>; | |
373 | reg = <0x100>; | |
85dc74e9 | 374 | clocks = <&dpll_core_h12x2_ck>; |
8fd46439 | 375 | ti,index-power-of-two; |
85dc74e9 TK |
376 | }; |
377 | ||
378 | gpu_l3_iclk: gpu_l3_iclk { | |
379 | #clock-cells = <0>; | |
380 | compatible = "fixed-factor-clock"; | |
381 | clocks = <&l3_iclk_div>; | |
382 | clock-mult = <1>; | |
383 | clock-div = <1>; | |
384 | }; | |
385 | ||
386 | l4_root_clk_div: l4_root_clk_div { | |
387 | #clock-cells = <0>; | |
8fd46439 TK |
388 | compatible = "ti,divider-clock"; |
389 | ti,max-div = <2>; | |
390 | ti,bit-shift = <8>; | |
391 | reg = <0x100>; | |
85dc74e9 | 392 | clocks = <&l3_iclk_div>; |
8fd46439 | 393 | ti,index-power-of-two; |
85dc74e9 TK |
394 | }; |
395 | ||
396 | slimbus1_slimbus_clk: slimbus1_slimbus_clk { | |
397 | #clock-cells = <0>; | |
398 | compatible = "ti,gate-clock"; | |
399 | clocks = <&slimbus_clk>; | |
400 | ti,bit-shift = <11>; | |
401 | reg = <0x0560>; | |
402 | }; | |
403 | ||
404 | aess_fclk: aess_fclk { | |
405 | #clock-cells = <0>; | |
406 | compatible = "ti,divider-clock"; | |
407 | clocks = <&abe_clk>; | |
408 | ti,bit-shift = <24>; | |
409 | ti,max-div = <2>; | |
410 | reg = <0x0528>; | |
411 | }; | |
412 | ||
413 | dmic_sync_mux_ck: dmic_sync_mux_ck { | |
414 | #clock-cells = <0>; | |
415 | compatible = "ti,mux-clock"; | |
416 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
417 | ti,bit-shift = <26>; | |
418 | reg = <0x0538>; | |
419 | }; | |
420 | ||
421 | dmic_gfclk: dmic_gfclk { | |
422 | #clock-cells = <0>; | |
423 | compatible = "ti,mux-clock"; | |
424 | clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
425 | ti,bit-shift = <24>; | |
426 | reg = <0x0538>; | |
427 | }; | |
428 | ||
429 | mcasp_sync_mux_ck: mcasp_sync_mux_ck { | |
430 | #clock-cells = <0>; | |
431 | compatible = "ti,mux-clock"; | |
432 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
433 | ti,bit-shift = <26>; | |
434 | reg = <0x0540>; | |
435 | }; | |
436 | ||
437 | mcasp_gfclk: mcasp_gfclk { | |
438 | #clock-cells = <0>; | |
439 | compatible = "ti,mux-clock"; | |
440 | clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
441 | ti,bit-shift = <24>; | |
442 | reg = <0x0540>; | |
443 | }; | |
444 | ||
445 | mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { | |
446 | #clock-cells = <0>; | |
447 | compatible = "ti,mux-clock"; | |
448 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
449 | ti,bit-shift = <26>; | |
450 | reg = <0x0548>; | |
451 | }; | |
452 | ||
453 | mcbsp1_gfclk: mcbsp1_gfclk { | |
454 | #clock-cells = <0>; | |
455 | compatible = "ti,mux-clock"; | |
456 | clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
457 | ti,bit-shift = <24>; | |
458 | reg = <0x0548>; | |
459 | }; | |
460 | ||
461 | mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { | |
462 | #clock-cells = <0>; | |
463 | compatible = "ti,mux-clock"; | |
464 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
465 | ti,bit-shift = <26>; | |
466 | reg = <0x0550>; | |
467 | }; | |
468 | ||
469 | mcbsp2_gfclk: mcbsp2_gfclk { | |
470 | #clock-cells = <0>; | |
471 | compatible = "ti,mux-clock"; | |
472 | clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
473 | ti,bit-shift = <24>; | |
474 | reg = <0x0550>; | |
475 | }; | |
476 | ||
477 | mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { | |
478 | #clock-cells = <0>; | |
479 | compatible = "ti,mux-clock"; | |
480 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
481 | ti,bit-shift = <26>; | |
482 | reg = <0x0558>; | |
483 | }; | |
484 | ||
485 | mcbsp3_gfclk: mcbsp3_gfclk { | |
486 | #clock-cells = <0>; | |
487 | compatible = "ti,mux-clock"; | |
488 | clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
489 | ti,bit-shift = <24>; | |
490 | reg = <0x0558>; | |
491 | }; | |
492 | ||
493 | timer5_gfclk_mux: timer5_gfclk_mux { | |
494 | #clock-cells = <0>; | |
495 | compatible = "ti,mux-clock"; | |
496 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
497 | ti,bit-shift = <24>; | |
498 | reg = <0x0568>; | |
499 | }; | |
500 | ||
501 | timer6_gfclk_mux: timer6_gfclk_mux { | |
502 | #clock-cells = <0>; | |
503 | compatible = "ti,mux-clock"; | |
504 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
505 | ti,bit-shift = <24>; | |
506 | reg = <0x0570>; | |
507 | }; | |
508 | ||
509 | timer7_gfclk_mux: timer7_gfclk_mux { | |
510 | #clock-cells = <0>; | |
511 | compatible = "ti,mux-clock"; | |
512 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
513 | ti,bit-shift = <24>; | |
514 | reg = <0x0578>; | |
515 | }; | |
516 | ||
517 | timer8_gfclk_mux: timer8_gfclk_mux { | |
518 | #clock-cells = <0>; | |
519 | compatible = "ti,mux-clock"; | |
520 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
521 | ti,bit-shift = <24>; | |
522 | reg = <0x0580>; | |
523 | }; | |
524 | ||
525 | dummy_ck: dummy_ck { | |
526 | #clock-cells = <0>; | |
527 | compatible = "fixed-clock"; | |
528 | clock-frequency = <0>; | |
529 | }; | |
530 | }; | |
531 | &prm_clocks { | |
532 | sys_clkin: sys_clkin { | |
533 | #clock-cells = <0>; | |
534 | compatible = "ti,mux-clock"; | |
535 | clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
536 | reg = <0x0110>; | |
537 | ti,index-starts-at-one; | |
538 | }; | |
539 | ||
540 | abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { | |
541 | #clock-cells = <0>; | |
542 | compatible = "ti,mux-clock"; | |
543 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
544 | reg = <0x0108>; | |
545 | }; | |
546 | ||
547 | abe_dpll_clk_mux: abe_dpll_clk_mux { | |
548 | #clock-cells = <0>; | |
549 | compatible = "ti,mux-clock"; | |
550 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
551 | reg = <0x010c>; | |
552 | }; | |
553 | ||
554 | custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { | |
555 | #clock-cells = <0>; | |
556 | compatible = "fixed-factor-clock"; | |
557 | clocks = <&sys_clkin>; | |
558 | clock-mult = <1>; | |
559 | clock-div = <2>; | |
560 | }; | |
561 | ||
562 | dss_syc_gfclk_div: dss_syc_gfclk_div { | |
563 | #clock-cells = <0>; | |
564 | compatible = "fixed-factor-clock"; | |
565 | clocks = <&sys_clkin>; | |
566 | clock-mult = <1>; | |
567 | clock-div = <1>; | |
568 | }; | |
569 | ||
570 | wkupaon_iclk_mux: wkupaon_iclk_mux { | |
571 | #clock-cells = <0>; | |
572 | compatible = "ti,mux-clock"; | |
573 | clocks = <&sys_clkin>, <&abe_lp_clk_div>; | |
574 | reg = <0x0108>; | |
575 | }; | |
576 | ||
577 | l3instr_ts_gclk_div: l3instr_ts_gclk_div { | |
578 | #clock-cells = <0>; | |
579 | compatible = "fixed-factor-clock"; | |
580 | clocks = <&wkupaon_iclk_mux>; | |
581 | clock-mult = <1>; | |
582 | clock-div = <1>; | |
583 | }; | |
584 | ||
585 | gpio1_dbclk: gpio1_dbclk { | |
586 | #clock-cells = <0>; | |
587 | compatible = "ti,gate-clock"; | |
588 | clocks = <&sys_32k_ck>; | |
589 | ti,bit-shift = <8>; | |
590 | reg = <0x1938>; | |
591 | }; | |
592 | ||
593 | timer1_gfclk_mux: timer1_gfclk_mux { | |
594 | #clock-cells = <0>; | |
595 | compatible = "ti,mux-clock"; | |
596 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
597 | ti,bit-shift = <24>; | |
598 | reg = <0x1940>; | |
599 | }; | |
600 | }; | |
601 | &cm_core_clocks { | |
602 | dpll_per_ck: dpll_per_ck { | |
603 | #clock-cells = <0>; | |
604 | compatible = "ti,omap4-dpll-clock"; | |
605 | clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; | |
606 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; | |
607 | }; | |
608 | ||
609 | dpll_per_x2_ck: dpll_per_x2_ck { | |
610 | #clock-cells = <0>; | |
611 | compatible = "ti,omap4-dpll-x2-clock"; | |
612 | clocks = <&dpll_per_ck>; | |
613 | }; | |
614 | ||
615 | dpll_per_h11x2_ck: dpll_per_h11x2_ck { | |
616 | #clock-cells = <0>; | |
617 | compatible = "ti,divider-clock"; | |
618 | clocks = <&dpll_per_x2_ck>; | |
619 | ti,max-div = <63>; | |
85dc74e9 TK |
620 | reg = <0x0158>; |
621 | ti,index-starts-at-one; | |
85dc74e9 TK |
622 | }; |
623 | ||
624 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { | |
625 | #clock-cells = <0>; | |
626 | compatible = "ti,divider-clock"; | |
627 | clocks = <&dpll_per_x2_ck>; | |
628 | ti,max-div = <63>; | |
85dc74e9 TK |
629 | reg = <0x015c>; |
630 | ti,index-starts-at-one; | |
85dc74e9 TK |
631 | }; |
632 | ||
633 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { | |
634 | #clock-cells = <0>; | |
635 | compatible = "ti,divider-clock"; | |
636 | clocks = <&dpll_per_x2_ck>; | |
637 | ti,max-div = <63>; | |
85dc74e9 TK |
638 | reg = <0x0164>; |
639 | ti,index-starts-at-one; | |
85dc74e9 TK |
640 | }; |
641 | ||
642 | dpll_per_m2_ck: dpll_per_m2_ck { | |
643 | #clock-cells = <0>; | |
644 | compatible = "ti,divider-clock"; | |
645 | clocks = <&dpll_per_ck>; | |
646 | ti,max-div = <31>; | |
85dc74e9 TK |
647 | reg = <0x0150>; |
648 | ti,index-starts-at-one; | |
85dc74e9 TK |
649 | }; |
650 | ||
651 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { | |
652 | #clock-cells = <0>; | |
653 | compatible = "ti,divider-clock"; | |
654 | clocks = <&dpll_per_x2_ck>; | |
655 | ti,max-div = <31>; | |
85dc74e9 TK |
656 | reg = <0x0150>; |
657 | ti,index-starts-at-one; | |
85dc74e9 TK |
658 | }; |
659 | ||
660 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { | |
661 | #clock-cells = <0>; | |
662 | compatible = "ti,divider-clock"; | |
663 | clocks = <&dpll_per_x2_ck>; | |
664 | ti,max-div = <31>; | |
85dc74e9 TK |
665 | reg = <0x0154>; |
666 | ti,index-starts-at-one; | |
85dc74e9 TK |
667 | }; |
668 | ||
669 | dpll_unipro1_ck: dpll_unipro1_ck { | |
670 | #clock-cells = <0>; | |
671 | compatible = "ti,omap4-dpll-clock"; | |
672 | clocks = <&sys_clkin>, <&sys_clkin>; | |
673 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
674 | }; | |
675 | ||
676 | dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { | |
677 | #clock-cells = <0>; | |
678 | compatible = "fixed-factor-clock"; | |
679 | clocks = <&dpll_unipro1_ck>; | |
680 | clock-mult = <1>; | |
681 | clock-div = <1>; | |
682 | }; | |
683 | ||
684 | dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { | |
685 | #clock-cells = <0>; | |
686 | compatible = "ti,divider-clock"; | |
687 | clocks = <&dpll_unipro1_ck>; | |
688 | ti,max-div = <127>; | |
85dc74e9 TK |
689 | reg = <0x0210>; |
690 | ti,index-starts-at-one; | |
85dc74e9 TK |
691 | }; |
692 | ||
693 | dpll_unipro2_ck: dpll_unipro2_ck { | |
694 | #clock-cells = <0>; | |
695 | compatible = "ti,omap4-dpll-clock"; | |
696 | clocks = <&sys_clkin>, <&sys_clkin>; | |
697 | reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; | |
698 | }; | |
699 | ||
700 | dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { | |
701 | #clock-cells = <0>; | |
702 | compatible = "fixed-factor-clock"; | |
703 | clocks = <&dpll_unipro2_ck>; | |
704 | clock-mult = <1>; | |
705 | clock-div = <1>; | |
706 | }; | |
707 | ||
708 | dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { | |
709 | #clock-cells = <0>; | |
710 | compatible = "ti,divider-clock"; | |
711 | clocks = <&dpll_unipro2_ck>; | |
712 | ti,max-div = <127>; | |
85dc74e9 TK |
713 | reg = <0x01d0>; |
714 | ti,index-starts-at-one; | |
85dc74e9 TK |
715 | }; |
716 | ||
717 | dpll_usb_ck: dpll_usb_ck { | |
718 | #clock-cells = <0>; | |
719 | compatible = "ti,omap4-dpll-j-type-clock"; | |
720 | clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; | |
721 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; | |
722 | }; | |
723 | ||
724 | dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { | |
725 | #clock-cells = <0>; | |
726 | compatible = "fixed-factor-clock"; | |
727 | clocks = <&dpll_usb_ck>; | |
728 | clock-mult = <1>; | |
729 | clock-div = <1>; | |
730 | }; | |
731 | ||
732 | dpll_usb_m2_ck: dpll_usb_m2_ck { | |
733 | #clock-cells = <0>; | |
734 | compatible = "ti,divider-clock"; | |
735 | clocks = <&dpll_usb_ck>; | |
736 | ti,max-div = <127>; | |
85dc74e9 TK |
737 | reg = <0x0190>; |
738 | ti,index-starts-at-one; | |
85dc74e9 TK |
739 | }; |
740 | ||
741 | func_128m_clk: func_128m_clk { | |
742 | #clock-cells = <0>; | |
743 | compatible = "fixed-factor-clock"; | |
744 | clocks = <&dpll_per_h11x2_ck>; | |
745 | clock-mult = <1>; | |
746 | clock-div = <2>; | |
747 | }; | |
748 | ||
749 | func_12m_fclk: func_12m_fclk { | |
750 | #clock-cells = <0>; | |
751 | compatible = "fixed-factor-clock"; | |
752 | clocks = <&dpll_per_m2x2_ck>; | |
753 | clock-mult = <1>; | |
754 | clock-div = <16>; | |
755 | }; | |
756 | ||
757 | func_24m_clk: func_24m_clk { | |
758 | #clock-cells = <0>; | |
759 | compatible = "fixed-factor-clock"; | |
760 | clocks = <&dpll_per_m2_ck>; | |
761 | clock-mult = <1>; | |
762 | clock-div = <4>; | |
763 | }; | |
764 | ||
765 | func_48m_fclk: func_48m_fclk { | |
766 | #clock-cells = <0>; | |
767 | compatible = "fixed-factor-clock"; | |
768 | clocks = <&dpll_per_m2x2_ck>; | |
769 | clock-mult = <1>; | |
770 | clock-div = <4>; | |
771 | }; | |
772 | ||
773 | func_96m_fclk: func_96m_fclk { | |
774 | #clock-cells = <0>; | |
775 | compatible = "fixed-factor-clock"; | |
776 | clocks = <&dpll_per_m2x2_ck>; | |
777 | clock-mult = <1>; | |
778 | clock-div = <2>; | |
779 | }; | |
780 | ||
781 | l3init_60m_fclk: l3init_60m_fclk { | |
782 | #clock-cells = <0>; | |
783 | compatible = "ti,divider-clock"; | |
784 | clocks = <&dpll_usb_m2_ck>; | |
785 | reg = <0x0104>; | |
786 | ti,dividers = <1>, <8>; | |
787 | }; | |
788 | ||
789 | dss_32khz_clk: dss_32khz_clk { | |
790 | #clock-cells = <0>; | |
791 | compatible = "ti,gate-clock"; | |
792 | clocks = <&sys_32k_ck>; | |
793 | ti,bit-shift = <11>; | |
794 | reg = <0x1420>; | |
795 | }; | |
796 | ||
797 | dss_48mhz_clk: dss_48mhz_clk { | |
798 | #clock-cells = <0>; | |
799 | compatible = "ti,gate-clock"; | |
800 | clocks = <&func_48m_fclk>; | |
801 | ti,bit-shift = <9>; | |
802 | reg = <0x1420>; | |
803 | }; | |
804 | ||
805 | dss_dss_clk: dss_dss_clk { | |
806 | #clock-cells = <0>; | |
807 | compatible = "ti,gate-clock"; | |
808 | clocks = <&dpll_per_h12x2_ck>; | |
809 | ti,bit-shift = <8>; | |
810 | reg = <0x1420>; | |
1be7b88c | 811 | ti,set-rate-parent; |
85dc74e9 TK |
812 | }; |
813 | ||
814 | dss_sys_clk: dss_sys_clk { | |
815 | #clock-cells = <0>; | |
816 | compatible = "ti,gate-clock"; | |
817 | clocks = <&dss_syc_gfclk_div>; | |
818 | ti,bit-shift = <10>; | |
819 | reg = <0x1420>; | |
820 | }; | |
821 | ||
822 | gpio2_dbclk: gpio2_dbclk { | |
823 | #clock-cells = <0>; | |
824 | compatible = "ti,gate-clock"; | |
825 | clocks = <&sys_32k_ck>; | |
826 | ti,bit-shift = <8>; | |
827 | reg = <0x1060>; | |
828 | }; | |
829 | ||
830 | gpio3_dbclk: gpio3_dbclk { | |
831 | #clock-cells = <0>; | |
832 | compatible = "ti,gate-clock"; | |
833 | clocks = <&sys_32k_ck>; | |
834 | ti,bit-shift = <8>; | |
835 | reg = <0x1068>; | |
836 | }; | |
837 | ||
838 | gpio4_dbclk: gpio4_dbclk { | |
839 | #clock-cells = <0>; | |
840 | compatible = "ti,gate-clock"; | |
841 | clocks = <&sys_32k_ck>; | |
842 | ti,bit-shift = <8>; | |
843 | reg = <0x1070>; | |
844 | }; | |
845 | ||
846 | gpio5_dbclk: gpio5_dbclk { | |
847 | #clock-cells = <0>; | |
848 | compatible = "ti,gate-clock"; | |
849 | clocks = <&sys_32k_ck>; | |
850 | ti,bit-shift = <8>; | |
851 | reg = <0x1078>; | |
852 | }; | |
853 | ||
854 | gpio6_dbclk: gpio6_dbclk { | |
855 | #clock-cells = <0>; | |
856 | compatible = "ti,gate-clock"; | |
857 | clocks = <&sys_32k_ck>; | |
858 | ti,bit-shift = <8>; | |
859 | reg = <0x1080>; | |
860 | }; | |
861 | ||
862 | gpio7_dbclk: gpio7_dbclk { | |
863 | #clock-cells = <0>; | |
864 | compatible = "ti,gate-clock"; | |
865 | clocks = <&sys_32k_ck>; | |
866 | ti,bit-shift = <8>; | |
867 | reg = <0x1110>; | |
868 | }; | |
869 | ||
870 | gpio8_dbclk: gpio8_dbclk { | |
871 | #clock-cells = <0>; | |
872 | compatible = "ti,gate-clock"; | |
873 | clocks = <&sys_32k_ck>; | |
874 | ti,bit-shift = <8>; | |
875 | reg = <0x1118>; | |
876 | }; | |
877 | ||
878 | iss_ctrlclk: iss_ctrlclk { | |
879 | #clock-cells = <0>; | |
880 | compatible = "ti,gate-clock"; | |
881 | clocks = <&func_96m_fclk>; | |
882 | ti,bit-shift = <8>; | |
883 | reg = <0x1320>; | |
884 | }; | |
885 | ||
886 | lli_txphy_clk: lli_txphy_clk { | |
887 | #clock-cells = <0>; | |
888 | compatible = "ti,gate-clock"; | |
889 | clocks = <&dpll_unipro1_clkdcoldo>; | |
890 | ti,bit-shift = <8>; | |
891 | reg = <0x0f20>; | |
892 | }; | |
893 | ||
894 | lli_txphy_ls_clk: lli_txphy_ls_clk { | |
895 | #clock-cells = <0>; | |
896 | compatible = "ti,gate-clock"; | |
897 | clocks = <&dpll_unipro1_m2_ck>; | |
898 | ti,bit-shift = <9>; | |
899 | reg = <0x0f20>; | |
900 | }; | |
901 | ||
902 | mmc1_32khz_clk: mmc1_32khz_clk { | |
903 | #clock-cells = <0>; | |
904 | compatible = "ti,gate-clock"; | |
905 | clocks = <&sys_32k_ck>; | |
906 | ti,bit-shift = <8>; | |
907 | reg = <0x1628>; | |
908 | }; | |
909 | ||
910 | sata_ref_clk: sata_ref_clk { | |
911 | #clock-cells = <0>; | |
912 | compatible = "ti,gate-clock"; | |
913 | clocks = <&sys_clkin>; | |
914 | ti,bit-shift = <8>; | |
915 | reg = <0x1688>; | |
916 | }; | |
917 | ||
918 | usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { | |
919 | #clock-cells = <0>; | |
920 | compatible = "ti,gate-clock"; | |
921 | clocks = <&dpll_usb_m2_ck>; | |
922 | ti,bit-shift = <13>; | |
923 | reg = <0x1658>; | |
924 | }; | |
925 | ||
926 | usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { | |
927 | #clock-cells = <0>; | |
928 | compatible = "ti,gate-clock"; | |
929 | clocks = <&dpll_usb_m2_ck>; | |
930 | ti,bit-shift = <14>; | |
931 | reg = <0x1658>; | |
932 | }; | |
933 | ||
934 | usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { | |
935 | #clock-cells = <0>; | |
936 | compatible = "ti,gate-clock"; | |
937 | clocks = <&dpll_usb_m2_ck>; | |
938 | ti,bit-shift = <7>; | |
939 | reg = <0x1658>; | |
940 | }; | |
941 | ||
942 | usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { | |
943 | #clock-cells = <0>; | |
944 | compatible = "ti,gate-clock"; | |
945 | clocks = <&l3init_60m_fclk>; | |
946 | ti,bit-shift = <11>; | |
947 | reg = <0x1658>; | |
948 | }; | |
949 | ||
950 | usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { | |
951 | #clock-cells = <0>; | |
952 | compatible = "ti,gate-clock"; | |
953 | clocks = <&l3init_60m_fclk>; | |
954 | ti,bit-shift = <12>; | |
955 | reg = <0x1658>; | |
956 | }; | |
957 | ||
958 | usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { | |
959 | #clock-cells = <0>; | |
960 | compatible = "ti,gate-clock"; | |
961 | clocks = <&l3init_60m_fclk>; | |
962 | ti,bit-shift = <6>; | |
963 | reg = <0x1658>; | |
964 | }; | |
965 | ||
966 | utmi_p1_gfclk: utmi_p1_gfclk { | |
967 | #clock-cells = <0>; | |
968 | compatible = "ti,mux-clock"; | |
969 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; | |
970 | ti,bit-shift = <24>; | |
971 | reg = <0x1658>; | |
972 | }; | |
973 | ||
974 | usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { | |
975 | #clock-cells = <0>; | |
976 | compatible = "ti,gate-clock"; | |
977 | clocks = <&utmi_p1_gfclk>; | |
978 | ti,bit-shift = <8>; | |
979 | reg = <0x1658>; | |
980 | }; | |
981 | ||
982 | utmi_p2_gfclk: utmi_p2_gfclk { | |
983 | #clock-cells = <0>; | |
984 | compatible = "ti,mux-clock"; | |
985 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; | |
986 | ti,bit-shift = <25>; | |
987 | reg = <0x1658>; | |
988 | }; | |
989 | ||
990 | usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { | |
991 | #clock-cells = <0>; | |
992 | compatible = "ti,gate-clock"; | |
993 | clocks = <&utmi_p2_gfclk>; | |
994 | ti,bit-shift = <9>; | |
995 | reg = <0x1658>; | |
996 | }; | |
997 | ||
998 | usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { | |
999 | #clock-cells = <0>; | |
1000 | compatible = "ti,gate-clock"; | |
1001 | clocks = <&l3init_60m_fclk>; | |
1002 | ti,bit-shift = <10>; | |
1003 | reg = <0x1658>; | |
1004 | }; | |
1005 | ||
1006 | usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { | |
1007 | #clock-cells = <0>; | |
1008 | compatible = "ti,gate-clock"; | |
1009 | clocks = <&dpll_usb_clkdcoldo>; | |
1010 | ti,bit-shift = <8>; | |
1011 | reg = <0x16f0>; | |
1012 | }; | |
1013 | ||
1014 | usb_phy_cm_clk32k: usb_phy_cm_clk32k { | |
1015 | #clock-cells = <0>; | |
1016 | compatible = "ti,gate-clock"; | |
1017 | clocks = <&sys_32k_ck>; | |
1018 | ti,bit-shift = <8>; | |
1019 | reg = <0x0640>; | |
1020 | }; | |
1021 | ||
1022 | usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { | |
1023 | #clock-cells = <0>; | |
1024 | compatible = "ti,gate-clock"; | |
1025 | clocks = <&l3init_60m_fclk>; | |
1026 | ti,bit-shift = <8>; | |
1027 | reg = <0x1668>; | |
1028 | }; | |
1029 | ||
1030 | usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { | |
1031 | #clock-cells = <0>; | |
1032 | compatible = "ti,gate-clock"; | |
1033 | clocks = <&l3init_60m_fclk>; | |
1034 | ti,bit-shift = <9>; | |
1035 | reg = <0x1668>; | |
1036 | }; | |
1037 | ||
1038 | usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { | |
1039 | #clock-cells = <0>; | |
1040 | compatible = "ti,gate-clock"; | |
1041 | clocks = <&l3init_60m_fclk>; | |
1042 | ti,bit-shift = <10>; | |
1043 | reg = <0x1668>; | |
1044 | }; | |
1045 | ||
1046 | fdif_fclk: fdif_fclk { | |
1047 | #clock-cells = <0>; | |
1048 | compatible = "ti,divider-clock"; | |
1049 | clocks = <&dpll_per_h11x2_ck>; | |
1050 | ti,bit-shift = <24>; | |
1051 | ti,max-div = <2>; | |
1052 | reg = <0x1328>; | |
1053 | }; | |
1054 | ||
1055 | gpu_core_gclk_mux: gpu_core_gclk_mux { | |
1056 | #clock-cells = <0>; | |
1057 | compatible = "ti,mux-clock"; | |
1058 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
1059 | ti,bit-shift = <24>; | |
1060 | reg = <0x1520>; | |
1061 | }; | |
1062 | ||
1063 | gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { | |
1064 | #clock-cells = <0>; | |
1065 | compatible = "ti,mux-clock"; | |
1066 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
1067 | ti,bit-shift = <25>; | |
1068 | reg = <0x1520>; | |
1069 | }; | |
1070 | ||
1071 | hsi_fclk: hsi_fclk { | |
1072 | #clock-cells = <0>; | |
1073 | compatible = "ti,divider-clock"; | |
1074 | clocks = <&dpll_per_m2x2_ck>; | |
1075 | ti,bit-shift = <24>; | |
1076 | ti,max-div = <2>; | |
1077 | reg = <0x1638>; | |
1078 | }; | |
1079 | ||
1080 | mmc1_fclk_mux: mmc1_fclk_mux { | |
1081 | #clock-cells = <0>; | |
1082 | compatible = "ti,mux-clock"; | |
1083 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1084 | ti,bit-shift = <24>; | |
1085 | reg = <0x1628>; | |
1086 | }; | |
1087 | ||
1088 | mmc1_fclk: mmc1_fclk { | |
1089 | #clock-cells = <0>; | |
1090 | compatible = "ti,divider-clock"; | |
1091 | clocks = <&mmc1_fclk_mux>; | |
1092 | ti,bit-shift = <25>; | |
1093 | ti,max-div = <2>; | |
1094 | reg = <0x1628>; | |
1095 | }; | |
1096 | ||
1097 | mmc2_fclk_mux: mmc2_fclk_mux { | |
1098 | #clock-cells = <0>; | |
1099 | compatible = "ti,mux-clock"; | |
1100 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
1101 | ti,bit-shift = <24>; | |
1102 | reg = <0x1630>; | |
1103 | }; | |
1104 | ||
1105 | mmc2_fclk: mmc2_fclk { | |
1106 | #clock-cells = <0>; | |
1107 | compatible = "ti,divider-clock"; | |
1108 | clocks = <&mmc2_fclk_mux>; | |
1109 | ti,bit-shift = <25>; | |
1110 | ti,max-div = <2>; | |
1111 | reg = <0x1630>; | |
1112 | }; | |
1113 | ||
1114 | timer10_gfclk_mux: timer10_gfclk_mux { | |
1115 | #clock-cells = <0>; | |
1116 | compatible = "ti,mux-clock"; | |
1117 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1118 | ti,bit-shift = <24>; | |
1119 | reg = <0x1028>; | |
1120 | }; | |
1121 | ||
1122 | timer11_gfclk_mux: timer11_gfclk_mux { | |
1123 | #clock-cells = <0>; | |
1124 | compatible = "ti,mux-clock"; | |
1125 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1126 | ti,bit-shift = <24>; | |
1127 | reg = <0x1030>; | |
1128 | }; | |
1129 | ||
1130 | timer2_gfclk_mux: timer2_gfclk_mux { | |
1131 | #clock-cells = <0>; | |
1132 | compatible = "ti,mux-clock"; | |
1133 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1134 | ti,bit-shift = <24>; | |
1135 | reg = <0x1038>; | |
1136 | }; | |
1137 | ||
1138 | timer3_gfclk_mux: timer3_gfclk_mux { | |
1139 | #clock-cells = <0>; | |
1140 | compatible = "ti,mux-clock"; | |
1141 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1142 | ti,bit-shift = <24>; | |
1143 | reg = <0x1040>; | |
1144 | }; | |
1145 | ||
1146 | timer4_gfclk_mux: timer4_gfclk_mux { | |
1147 | #clock-cells = <0>; | |
1148 | compatible = "ti,mux-clock"; | |
1149 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1150 | ti,bit-shift = <24>; | |
1151 | reg = <0x1048>; | |
1152 | }; | |
1153 | ||
1154 | timer9_gfclk_mux: timer9_gfclk_mux { | |
1155 | #clock-cells = <0>; | |
1156 | compatible = "ti,mux-clock"; | |
1157 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
1158 | ti,bit-shift = <24>; | |
1159 | reg = <0x1050>; | |
1160 | }; | |
1161 | }; | |
1162 | ||
1163 | &cm_core_clockdomains { | |
1164 | l3init_clkdm: l3init_clkdm { | |
1165 | compatible = "ti,clockdomain"; | |
1166 | clocks = <&dpll_usb_ck>; | |
1167 | }; | |
1168 | }; | |
1169 | ||
1170 | &scrm_clocks { | |
1171 | auxclk0_src_gate_ck: auxclk0_src_gate_ck { | |
1172 | #clock-cells = <0>; | |
1173 | compatible = "ti,composite-no-wait-gate-clock"; | |
1174 | clocks = <&dpll_core_m3x2_ck>; | |
1175 | ti,bit-shift = <8>; | |
1176 | reg = <0x0310>; | |
1177 | }; | |
1178 | ||
1179 | auxclk0_src_mux_ck: auxclk0_src_mux_ck { | |
1180 | #clock-cells = <0>; | |
1181 | compatible = "ti,composite-mux-clock"; | |
1182 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1183 | ti,bit-shift = <1>; | |
1184 | reg = <0x0310>; | |
1185 | }; | |
1186 | ||
1187 | auxclk0_src_ck: auxclk0_src_ck { | |
1188 | #clock-cells = <0>; | |
1189 | compatible = "ti,composite-clock"; | |
1190 | clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; | |
1191 | }; | |
1192 | ||
1193 | auxclk0_ck: auxclk0_ck { | |
1194 | #clock-cells = <0>; | |
1195 | compatible = "ti,divider-clock"; | |
1196 | clocks = <&auxclk0_src_ck>; | |
1197 | ti,bit-shift = <16>; | |
1198 | ti,max-div = <16>; | |
1199 | reg = <0x0310>; | |
1200 | }; | |
1201 | ||
1202 | auxclk1_src_gate_ck: auxclk1_src_gate_ck { | |
1203 | #clock-cells = <0>; | |
1204 | compatible = "ti,composite-no-wait-gate-clock"; | |
1205 | clocks = <&dpll_core_m3x2_ck>; | |
1206 | ti,bit-shift = <8>; | |
1207 | reg = <0x0314>; | |
1208 | }; | |
1209 | ||
1210 | auxclk1_src_mux_ck: auxclk1_src_mux_ck { | |
1211 | #clock-cells = <0>; | |
1212 | compatible = "ti,composite-mux-clock"; | |
1213 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1214 | ti,bit-shift = <1>; | |
1215 | reg = <0x0314>; | |
1216 | }; | |
1217 | ||
1218 | auxclk1_src_ck: auxclk1_src_ck { | |
1219 | #clock-cells = <0>; | |
1220 | compatible = "ti,composite-clock"; | |
1221 | clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; | |
1222 | }; | |
1223 | ||
1224 | auxclk1_ck: auxclk1_ck { | |
1225 | #clock-cells = <0>; | |
1226 | compatible = "ti,divider-clock"; | |
1227 | clocks = <&auxclk1_src_ck>; | |
1228 | ti,bit-shift = <16>; | |
1229 | ti,max-div = <16>; | |
1230 | reg = <0x0314>; | |
1231 | }; | |
1232 | ||
1233 | auxclk2_src_gate_ck: auxclk2_src_gate_ck { | |
1234 | #clock-cells = <0>; | |
1235 | compatible = "ti,composite-no-wait-gate-clock"; | |
1236 | clocks = <&dpll_core_m3x2_ck>; | |
1237 | ti,bit-shift = <8>; | |
1238 | reg = <0x0318>; | |
1239 | }; | |
1240 | ||
1241 | auxclk2_src_mux_ck: auxclk2_src_mux_ck { | |
1242 | #clock-cells = <0>; | |
1243 | compatible = "ti,composite-mux-clock"; | |
1244 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1245 | ti,bit-shift = <1>; | |
1246 | reg = <0x0318>; | |
1247 | }; | |
1248 | ||
1249 | auxclk2_src_ck: auxclk2_src_ck { | |
1250 | #clock-cells = <0>; | |
1251 | compatible = "ti,composite-clock"; | |
1252 | clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; | |
1253 | }; | |
1254 | ||
1255 | auxclk2_ck: auxclk2_ck { | |
1256 | #clock-cells = <0>; | |
1257 | compatible = "ti,divider-clock"; | |
1258 | clocks = <&auxclk2_src_ck>; | |
1259 | ti,bit-shift = <16>; | |
1260 | ti,max-div = <16>; | |
1261 | reg = <0x0318>; | |
1262 | }; | |
1263 | ||
1264 | auxclk3_src_gate_ck: auxclk3_src_gate_ck { | |
1265 | #clock-cells = <0>; | |
1266 | compatible = "ti,composite-no-wait-gate-clock"; | |
1267 | clocks = <&dpll_core_m3x2_ck>; | |
1268 | ti,bit-shift = <8>; | |
1269 | reg = <0x031c>; | |
1270 | }; | |
1271 | ||
1272 | auxclk3_src_mux_ck: auxclk3_src_mux_ck { | |
1273 | #clock-cells = <0>; | |
1274 | compatible = "ti,composite-mux-clock"; | |
1275 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1276 | ti,bit-shift = <1>; | |
1277 | reg = <0x031c>; | |
1278 | }; | |
1279 | ||
1280 | auxclk3_src_ck: auxclk3_src_ck { | |
1281 | #clock-cells = <0>; | |
1282 | compatible = "ti,composite-clock"; | |
1283 | clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; | |
1284 | }; | |
1285 | ||
1286 | auxclk3_ck: auxclk3_ck { | |
1287 | #clock-cells = <0>; | |
1288 | compatible = "ti,divider-clock"; | |
1289 | clocks = <&auxclk3_src_ck>; | |
1290 | ti,bit-shift = <16>; | |
1291 | ti,max-div = <16>; | |
1292 | reg = <0x031c>; | |
1293 | }; | |
1294 | ||
1295 | auxclk4_src_gate_ck: auxclk4_src_gate_ck { | |
1296 | #clock-cells = <0>; | |
1297 | compatible = "ti,composite-no-wait-gate-clock"; | |
1298 | clocks = <&dpll_core_m3x2_ck>; | |
1299 | ti,bit-shift = <8>; | |
1300 | reg = <0x0320>; | |
1301 | }; | |
1302 | ||
1303 | auxclk4_src_mux_ck: auxclk4_src_mux_ck { | |
1304 | #clock-cells = <0>; | |
1305 | compatible = "ti,composite-mux-clock"; | |
1306 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
1307 | ti,bit-shift = <1>; | |
1308 | reg = <0x0320>; | |
1309 | }; | |
1310 | ||
1311 | auxclk4_src_ck: auxclk4_src_ck { | |
1312 | #clock-cells = <0>; | |
1313 | compatible = "ti,composite-clock"; | |
1314 | clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; | |
1315 | }; | |
1316 | ||
1317 | auxclk4_ck: auxclk4_ck { | |
1318 | #clock-cells = <0>; | |
1319 | compatible = "ti,divider-clock"; | |
1320 | clocks = <&auxclk4_src_ck>; | |
1321 | ti,bit-shift = <16>; | |
1322 | ti,max-div = <16>; | |
1323 | reg = <0x0320>; | |
1324 | }; | |
1325 | ||
1326 | auxclkreq0_ck: auxclkreq0_ck { | |
1327 | #clock-cells = <0>; | |
1328 | compatible = "ti,mux-clock"; | |
1329 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1330 | ti,bit-shift = <2>; | |
1331 | reg = <0x0210>; | |
1332 | }; | |
1333 | ||
1334 | auxclkreq1_ck: auxclkreq1_ck { | |
1335 | #clock-cells = <0>; | |
1336 | compatible = "ti,mux-clock"; | |
1337 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1338 | ti,bit-shift = <2>; | |
1339 | reg = <0x0214>; | |
1340 | }; | |
1341 | ||
1342 | auxclkreq2_ck: auxclkreq2_ck { | |
1343 | #clock-cells = <0>; | |
1344 | compatible = "ti,mux-clock"; | |
1345 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1346 | ti,bit-shift = <2>; | |
1347 | reg = <0x0218>; | |
1348 | }; | |
1349 | ||
1350 | auxclkreq3_ck: auxclkreq3_ck { | |
1351 | #clock-cells = <0>; | |
1352 | compatible = "ti,mux-clock"; | |
1353 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
1354 | ti,bit-shift = <2>; | |
1355 | reg = <0x021c>; | |
1356 | }; | |
1357 | }; |