projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 85dc74e9 TK |
1 | /* |
| 2 | * Device Tree Source for OMAP5 clock data | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | &cm_core_aon_clocks { | |
| 11 | pad_clks_src_ck: pad_clks_src_ck { | |
| 12 | #clock-cells = <0>; | |
| 13 | compatible = "fixed-clock"; | |
| 14 | clock-frequency = <12000000>; | |
| 15 | }; | |
| 16 | ||
| 17 | pad_clks_ck: pad_clks_ck { | |
| 18 | #clock-cells = <0>; | |
| 19 | compatible = "ti,gate-clock"; | |
| 20 | clocks = <&pad_clks_src_ck>; | |
| 21 | ti,bit-shift = <8>; | |
| 22 | reg = <0x0108>; | |
| 23 | }; | |
| 24 | ||
| 25 | secure_32k_clk_src_ck: secure_32k_clk_src_ck { | |
| 26 | #clock-cells = <0>; | |
| 27 | compatible = "fixed-clock"; | |
| 28 | clock-frequency = <32768>; | |
| 29 | }; | |
| 30 | ||
| 31 | slimbus_src_clk: slimbus_src_clk { | |
| 32 | #clock-cells = <0>; | |
| 33 | compatible = "fixed-clock"; | |
| 34 | clock-frequency = <12000000>; | |
| 35 | }; | |
| 36 | ||
| 37 | slimbus_clk: slimbus_clk { | |
| 38 | #clock-cells = <0>; | |
| 39 | compatible = "ti,gate-clock"; | |
| 40 | clocks = <&slimbus_src_clk>; | |
| 41 | ti,bit-shift = <10>; | |
| 42 | reg = <0x0108>; | |
| 43 | }; | |
| 44 | ||
| 45 | sys_32k_ck: sys_32k_ck { | |
| 46 | #clock-cells = <0>; | |
| 47 | compatible = "fixed-clock"; | |
| 48 | clock-frequency = <32768>; | |
| 49 | }; | |
| 50 | ||
| 51 | virt_12000000_ck: virt_12000000_ck { | |
| 52 | #clock-cells = <0>; | |
| 53 | compatible = "fixed-clock"; | |
| 54 | clock-frequency = <12000000>; | |
| 55 | }; | |
| 56 | ||
| 57 | virt_13000000_ck: virt_13000000_ck { | |
| 58 | #clock-cells = <0>; | |
| 59 | compatible = "fixed-clock"; | |
| 60 | clock-frequency = <13000000>; | |
| 61 | }; | |
| 62 | ||
| 63 | virt_16800000_ck: virt_16800000_ck { | |
| 64 | #clock-cells = <0>; | |
| 65 | compatible = "fixed-clock"; | |
| 66 | clock-frequency = <16800000>; | |
| 67 | }; | |
| 68 | ||
| 69 | virt_19200000_ck: virt_19200000_ck { | |
| 70 | #clock-cells = <0>; | |
| 71 | compatible = "fixed-clock"; | |
| 72 | clock-frequency = <19200000>; | |
| 73 | }; | |
| 74 | ||
| 75 | virt_26000000_ck: virt_26000000_ck { | |
| 76 | #clock-cells = <0>; | |
| 77 | compatible = "fixed-clock"; | |
| 78 | clock-frequency = <26000000>; | |
| 79 | }; | |
| 80 | ||
| 81 | virt_27000000_ck: virt_27000000_ck { | |
| 82 | #clock-cells = <0>; | |
| 83 | compatible = "fixed-clock"; | |
| 84 | clock-frequency = <27000000>; | |
| 85 | }; | |
| 86 | ||
| 87 | virt_38400000_ck: virt_38400000_ck { | |
| 88 | #clock-cells = <0>; | |
| 89 | compatible = "fixed-clock"; | |
| 90 | clock-frequency = <38400000>; | |
| 91 | }; | |
| 92 | ||
| 93 | xclk60mhsp1_ck: xclk60mhsp1_ck { | |
| 94 | #clock-cells = <0>; | |
| 95 | compatible = "fixed-clock"; | |
| 96 | clock-frequency = <60000000>; | |
| 97 | }; | |
| 98 | ||
| 99 | xclk60mhsp2_ck: xclk60mhsp2_ck { | |
| 100 | #clock-cells = <0>; | |
| 101 | compatible = "fixed-clock"; | |
| 102 | clock-frequency = <60000000>; | |
| 103 | }; | |
| 104 | ||
| 105 | dpll_abe_ck: dpll_abe_ck { | |
| 106 | #clock-cells = <0>; | |
| 107 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
| 108 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
| 109 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
| 110 | }; | |
| 111 | ||
| 112 | dpll_abe_x2_ck: dpll_abe_x2_ck { | |
| 113 | #clock-cells = <0>; | |
| 114 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 115 | clocks = <&dpll_abe_ck>; | |
| 116 | }; | |
| 117 | ||
| 118 | dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { | |
| 119 | #clock-cells = <0>; | |
| 120 | compatible = "ti,divider-clock"; | |
| 121 | clocks = <&dpll_abe_x2_ck>; | |
| 122 | ti,max-div = <31>; | |
| 85dc74e9 TK |
123 | reg = <0x01f0>; |
| 124 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
125 | }; |
| 126 | ||
| 127 | abe_24m_fclk: abe_24m_fclk { | |
| 128 | #clock-cells = <0>; | |
| 129 | compatible = "fixed-factor-clock"; | |
| 130 | clocks = <&dpll_abe_m2x2_ck>; | |
| 131 | clock-mult = <1>; | |
| 132 | clock-div = <8>; | |
| 133 | }; | |
| 134 | ||
| 135 | abe_clk: abe_clk { | |
| 136 | #clock-cells = <0>; | |
| 137 | compatible = "ti,divider-clock"; | |
| 138 | clocks = <&dpll_abe_m2x2_ck>; | |
| 139 | ti,max-div = <4>; | |
| 140 | reg = <0x0108>; | |
| 141 | ti,index-power-of-two; | |
| 142 | }; | |
| 143 | ||
| 144 | abe_iclk: abe_iclk { | |
| 145 | #clock-cells = <0>; | |
| 146 | compatible = "fixed-factor-clock"; | |
| 147 | clocks = <&abe_clk>; | |
| 148 | clock-mult = <1>; | |
| 149 | clock-div = <2>; | |
| 150 | }; | |
| 151 | ||
| 152 | abe_lp_clk_div: abe_lp_clk_div { | |
| 153 | #clock-cells = <0>; | |
| 154 | compatible = "fixed-factor-clock"; | |
| 155 | clocks = <&dpll_abe_m2x2_ck>; | |
| 156 | clock-mult = <1>; | |
| 157 | clock-div = <16>; | |
| 158 | }; | |
| 159 | ||
| 160 | dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { | |
| 161 | #clock-cells = <0>; | |
| 162 | compatible = "ti,divider-clock"; | |
| 163 | clocks = <&dpll_abe_x2_ck>; | |
| 164 | ti,max-div = <31>; | |
| 85dc74e9 TK |
165 | reg = <0x01f4>; |
| 166 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
167 | }; |
| 168 | ||
| 169 | dpll_core_ck: dpll_core_ck { | |
| 170 | #clock-cells = <0>; | |
| 171 | compatible = "ti,omap4-dpll-core-clock"; | |
| 172 | clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; | |
| 173 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; | |
| 174 | }; | |
| 175 | ||
| 176 | dpll_core_x2_ck: dpll_core_x2_ck { | |
| 177 | #clock-cells = <0>; | |
| 178 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 179 | clocks = <&dpll_core_ck>; | |
| 180 | }; | |
| 181 | ||
| 182 | dpll_core_h21x2_ck: dpll_core_h21x2_ck { | |
| 183 | #clock-cells = <0>; | |
| 184 | compatible = "ti,divider-clock"; | |
| 185 | clocks = <&dpll_core_x2_ck>; | |
| 186 | ti,max-div = <63>; | |
| 85dc74e9 TK |
187 | reg = <0x0150>; |
| 188 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
189 | }; |
| 190 | ||
| 191 | c2c_fclk: c2c_fclk { | |
| 192 | #clock-cells = <0>; | |
| 193 | compatible = "fixed-factor-clock"; | |
| 194 | clocks = <&dpll_core_h21x2_ck>; | |
| 195 | clock-mult = <1>; | |
| 196 | clock-div = <1>; | |
| 197 | }; | |
| 198 | ||
| 199 | c2c_iclk: c2c_iclk { | |
| 200 | #clock-cells = <0>; | |
| 201 | compatible = "fixed-factor-clock"; | |
| 202 | clocks = <&c2c_fclk>; | |
| 203 | clock-mult = <1>; | |
| 204 | clock-div = <2>; | |
| 205 | }; | |
| 206 | ||
| 207 | dpll_core_h11x2_ck: dpll_core_h11x2_ck { | |
| 208 | #clock-cells = <0>; | |
| 209 | compatible = "ti,divider-clock"; | |
| 210 | clocks = <&dpll_core_x2_ck>; | |
| 211 | ti,max-div = <63>; | |
| 85dc74e9 TK |
212 | reg = <0x0138>; |
| 213 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
214 | }; |
| 215 | ||
| 216 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { | |
| 217 | #clock-cells = <0>; | |
| 218 | compatible = "ti,divider-clock"; | |
| 219 | clocks = <&dpll_core_x2_ck>; | |
| 220 | ti,max-div = <63>; | |
| 85dc74e9 TK |
221 | reg = <0x013c>; |
| 222 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
223 | }; |
| 224 | ||
| 225 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { | |
| 226 | #clock-cells = <0>; | |
| 227 | compatible = "ti,divider-clock"; | |
| 228 | clocks = <&dpll_core_x2_ck>; | |
| 229 | ti,max-div = <63>; | |
| 85dc74e9 TK |
230 | reg = <0x0140>; |
| 231 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
232 | }; |
| 233 | ||
| 234 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { | |
| 235 | #clock-cells = <0>; | |
| 236 | compatible = "ti,divider-clock"; | |
| 237 | clocks = <&dpll_core_x2_ck>; | |
| 238 | ti,max-div = <63>; | |
| 85dc74e9 TK |
239 | reg = <0x0144>; |
| 240 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
241 | }; |
| 242 | ||
| 243 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { | |
| 244 | #clock-cells = <0>; | |
| 245 | compatible = "ti,divider-clock"; | |
| 246 | clocks = <&dpll_core_x2_ck>; | |
| 247 | ti,max-div = <63>; | |
| 85dc74e9 TK |
248 | reg = <0x0154>; |
| 249 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
250 | }; |
| 251 | ||
| 252 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { | |
| 253 | #clock-cells = <0>; | |
| 254 | compatible = "ti,divider-clock"; | |
| 255 | clocks = <&dpll_core_x2_ck>; | |
| 256 | ti,max-div = <63>; | |
| 85dc74e9 TK |
257 | reg = <0x0158>; |
| 258 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
259 | }; |
| 260 | ||
| 261 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { | |
| 262 | #clock-cells = <0>; | |
| 263 | compatible = "ti,divider-clock"; | |
| 264 | clocks = <&dpll_core_x2_ck>; | |
| 265 | ti,max-div = <63>; | |
| 85dc74e9 TK |
266 | reg = <0x015c>; |
| 267 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
268 | }; |
| 269 | ||
| 270 | dpll_core_m2_ck: dpll_core_m2_ck { | |
| 271 | #clock-cells = <0>; | |
| 272 | compatible = "ti,divider-clock"; | |
| 273 | clocks = <&dpll_core_ck>; | |
| 274 | ti,max-div = <31>; | |
| 85dc74e9 TK |
275 | reg = <0x0130>; |
| 276 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
277 | }; |
| 278 | ||
| 279 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { | |
| 280 | #clock-cells = <0>; | |
| 281 | compatible = "ti,divider-clock"; | |
| 282 | clocks = <&dpll_core_x2_ck>; | |
| 283 | ti,max-div = <31>; | |
| 85dc74e9 TK |
284 | reg = <0x0134>; |
| 285 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
286 | }; |
| 287 | ||
| 288 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | |
| 289 | #clock-cells = <0>; | |
| 290 | compatible = "fixed-factor-clock"; | |
| 291 | clocks = <&dpll_core_h12x2_ck>; | |
| 292 | clock-mult = <1>; | |
| 293 | clock-div = <1>; | |
| 294 | }; | |
| 295 | ||
| 296 | dpll_iva_ck: dpll_iva_ck { | |
| 297 | #clock-cells = <0>; | |
| 298 | compatible = "ti,omap4-dpll-clock"; | |
| 299 | clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; | |
| 300 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; | |
| 301 | }; | |
| 302 | ||
| 303 | dpll_iva_x2_ck: dpll_iva_x2_ck { | |
| 304 | #clock-cells = <0>; | |
| 305 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 306 | clocks = <&dpll_iva_ck>; | |
| 307 | }; | |
| 308 | ||
| 309 | dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { | |
| 310 | #clock-cells = <0>; | |
| 311 | compatible = "ti,divider-clock"; | |
| 312 | clocks = <&dpll_iva_x2_ck>; | |
| 313 | ti,max-div = <63>; | |
| 85dc74e9 TK |
314 | reg = <0x01b8>; |
| 315 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
316 | }; |
| 317 | ||
| 318 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { | |
| 319 | #clock-cells = <0>; | |
| 320 | compatible = "ti,divider-clock"; | |
| 321 | clocks = <&dpll_iva_x2_ck>; | |
| 322 | ti,max-div = <63>; | |
| 85dc74e9 TK |
323 | reg = <0x01bc>; |
| 324 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
325 | }; |
| 326 | ||
| 327 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | |
| 328 | #clock-cells = <0>; | |
| 329 | compatible = "fixed-factor-clock"; | |
| 330 | clocks = <&dpll_core_h12x2_ck>; | |
| 331 | clock-mult = <1>; | |
| 332 | clock-div = <1>; | |
| 333 | }; | |
| 334 | ||
| 335 | dpll_mpu_ck: dpll_mpu_ck { | |
| 336 | #clock-cells = <0>; | |
| 337 | compatible = "ti,omap4-dpll-clock"; | |
| 338 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; | |
| 339 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
| 340 | }; | |
| 341 | ||
| 342 | dpll_mpu_m2_ck: dpll_mpu_m2_ck { | |
| 343 | #clock-cells = <0>; | |
| 344 | compatible = "ti,divider-clock"; | |
| 345 | clocks = <&dpll_mpu_ck>; | |
| 346 | ti,max-div = <31>; | |
| 85dc74e9 TK |
347 | reg = <0x0170>; |
| 348 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
349 | }; |
| 350 | ||
| 351 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | |
| 352 | #clock-cells = <0>; | |
| 353 | compatible = "fixed-factor-clock"; | |
| 354 | clocks = <&dpll_abe_m3x2_ck>; | |
| 355 | clock-mult = <1>; | |
| 356 | clock-div = <2>; | |
| 357 | }; | |
| 358 | ||
| 359 | usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { | |
| 360 | #clock-cells = <0>; | |
| 361 | compatible = "fixed-factor-clock"; | |
| 362 | clocks = <&dpll_abe_m3x2_ck>; | |
| 363 | clock-mult = <1>; | |
| 364 | clock-div = <3>; | |
| 365 | }; | |
| 366 | ||
| 367 | l3_iclk_div: l3_iclk_div { | |
| 368 | #clock-cells = <0>; | |
| 369 | compatible = "fixed-factor-clock"; | |
| 370 | clocks = <&dpll_core_h12x2_ck>; | |
| 371 | clock-mult = <1>; | |
| 372 | clock-div = <1>; | |
| 373 | }; | |
| 374 | ||
| 375 | gpu_l3_iclk: gpu_l3_iclk { | |
| 376 | #clock-cells = <0>; | |
| 377 | compatible = "fixed-factor-clock"; | |
| 378 | clocks = <&l3_iclk_div>; | |
| 379 | clock-mult = <1>; | |
| 380 | clock-div = <1>; | |
| 381 | }; | |
| 382 | ||
| 383 | l4_root_clk_div: l4_root_clk_div { | |
| 384 | #clock-cells = <0>; | |
| 385 | compatible = "fixed-factor-clock"; | |
| 386 | clocks = <&l3_iclk_div>; | |
| 387 | clock-mult = <1>; | |
| 388 | clock-div = <1>; | |
| 389 | }; | |
| 390 | ||
| 391 | slimbus1_slimbus_clk: slimbus1_slimbus_clk { | |
| 392 | #clock-cells = <0>; | |
| 393 | compatible = "ti,gate-clock"; | |
| 394 | clocks = <&slimbus_clk>; | |
| 395 | ti,bit-shift = <11>; | |
| 396 | reg = <0x0560>; | |
| 397 | }; | |
| 398 | ||
| 399 | aess_fclk: aess_fclk { | |
| 400 | #clock-cells = <0>; | |
| 401 | compatible = "ti,divider-clock"; | |
| 402 | clocks = <&abe_clk>; | |
| 403 | ti,bit-shift = <24>; | |
| 404 | ti,max-div = <2>; | |
| 405 | reg = <0x0528>; | |
| 406 | }; | |
| 407 | ||
| 408 | dmic_sync_mux_ck: dmic_sync_mux_ck { | |
| 409 | #clock-cells = <0>; | |
| 410 | compatible = "ti,mux-clock"; | |
| 411 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 412 | ti,bit-shift = <26>; | |
| 413 | reg = <0x0538>; | |
| 414 | }; | |
| 415 | ||
| 416 | dmic_gfclk: dmic_gfclk { | |
| 417 | #clock-cells = <0>; | |
| 418 | compatible = "ti,mux-clock"; | |
| 419 | clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 420 | ti,bit-shift = <24>; | |
| 421 | reg = <0x0538>; | |
| 422 | }; | |
| 423 | ||
| 424 | mcasp_sync_mux_ck: mcasp_sync_mux_ck { | |
| 425 | #clock-cells = <0>; | |
| 426 | compatible = "ti,mux-clock"; | |
| 427 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 428 | ti,bit-shift = <26>; | |
| 429 | reg = <0x0540>; | |
| 430 | }; | |
| 431 | ||
| 432 | mcasp_gfclk: mcasp_gfclk { | |
| 433 | #clock-cells = <0>; | |
| 434 | compatible = "ti,mux-clock"; | |
| 435 | clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 436 | ti,bit-shift = <24>; | |
| 437 | reg = <0x0540>; | |
| 438 | }; | |
| 439 | ||
| 440 | mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { | |
| 441 | #clock-cells = <0>; | |
| 442 | compatible = "ti,mux-clock"; | |
| 443 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 444 | ti,bit-shift = <26>; | |
| 445 | reg = <0x0548>; | |
| 446 | }; | |
| 447 | ||
| 448 | mcbsp1_gfclk: mcbsp1_gfclk { | |
| 449 | #clock-cells = <0>; | |
| 450 | compatible = "ti,mux-clock"; | |
| 451 | clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 452 | ti,bit-shift = <24>; | |
| 453 | reg = <0x0548>; | |
| 454 | }; | |
| 455 | ||
| 456 | mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { | |
| 457 | #clock-cells = <0>; | |
| 458 | compatible = "ti,mux-clock"; | |
| 459 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 460 | ti,bit-shift = <26>; | |
| 461 | reg = <0x0550>; | |
| 462 | }; | |
| 463 | ||
| 464 | mcbsp2_gfclk: mcbsp2_gfclk { | |
| 465 | #clock-cells = <0>; | |
| 466 | compatible = "ti,mux-clock"; | |
| 467 | clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 468 | ti,bit-shift = <24>; | |
| 469 | reg = <0x0550>; | |
| 470 | }; | |
| 471 | ||
| 472 | mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { | |
| 473 | #clock-cells = <0>; | |
| 474 | compatible = "ti,mux-clock"; | |
| 475 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 476 | ti,bit-shift = <26>; | |
| 477 | reg = <0x0558>; | |
| 478 | }; | |
| 479 | ||
| 480 | mcbsp3_gfclk: mcbsp3_gfclk { | |
| 481 | #clock-cells = <0>; | |
| 482 | compatible = "ti,mux-clock"; | |
| 483 | clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 484 | ti,bit-shift = <24>; | |
| 485 | reg = <0x0558>; | |
| 486 | }; | |
| 487 | ||
| 488 | timer5_gfclk_mux: timer5_gfclk_mux { | |
| 489 | #clock-cells = <0>; | |
| 490 | compatible = "ti,mux-clock"; | |
| 491 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 492 | ti,bit-shift = <24>; | |
| 493 | reg = <0x0568>; | |
| 494 | }; | |
| 495 | ||
| 496 | timer6_gfclk_mux: timer6_gfclk_mux { | |
| 497 | #clock-cells = <0>; | |
| 498 | compatible = "ti,mux-clock"; | |
| 499 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 500 | ti,bit-shift = <24>; | |
| 501 | reg = <0x0570>; | |
| 502 | }; | |
| 503 | ||
| 504 | timer7_gfclk_mux: timer7_gfclk_mux { | |
| 505 | #clock-cells = <0>; | |
| 506 | compatible = "ti,mux-clock"; | |
| 507 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 508 | ti,bit-shift = <24>; | |
| 509 | reg = <0x0578>; | |
| 510 | }; | |
| 511 | ||
| 512 | timer8_gfclk_mux: timer8_gfclk_mux { | |
| 513 | #clock-cells = <0>; | |
| 514 | compatible = "ti,mux-clock"; | |
| 515 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 516 | ti,bit-shift = <24>; | |
| 517 | reg = <0x0580>; | |
| 518 | }; | |
| 519 | ||
| 520 | dummy_ck: dummy_ck { | |
| 521 | #clock-cells = <0>; | |
| 522 | compatible = "fixed-clock"; | |
| 523 | clock-frequency = <0>; | |
| 524 | }; | |
| 525 | }; | |
| 526 | &prm_clocks { | |
| 527 | sys_clkin: sys_clkin { | |
| 528 | #clock-cells = <0>; | |
| 529 | compatible = "ti,mux-clock"; | |
| 530 | clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
| 531 | reg = <0x0110>; | |
| 532 | ti,index-starts-at-one; | |
| 533 | }; | |
| 534 | ||
| 535 | abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { | |
| 536 | #clock-cells = <0>; | |
| 537 | compatible = "ti,mux-clock"; | |
| 538 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 539 | reg = <0x0108>; | |
| 540 | }; | |
| 541 | ||
| 542 | abe_dpll_clk_mux: abe_dpll_clk_mux { | |
| 543 | #clock-cells = <0>; | |
| 544 | compatible = "ti,mux-clock"; | |
| 545 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 546 | reg = <0x010c>; | |
| 547 | }; | |
| 548 | ||
| 549 | custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { | |
| 550 | #clock-cells = <0>; | |
| 551 | compatible = "fixed-factor-clock"; | |
| 552 | clocks = <&sys_clkin>; | |
| 553 | clock-mult = <1>; | |
| 554 | clock-div = <2>; | |
| 555 | }; | |
| 556 | ||
| 557 | dss_syc_gfclk_div: dss_syc_gfclk_div { | |
| 558 | #clock-cells = <0>; | |
| 559 | compatible = "fixed-factor-clock"; | |
| 560 | clocks = <&sys_clkin>; | |
| 561 | clock-mult = <1>; | |
| 562 | clock-div = <1>; | |
| 563 | }; | |
| 564 | ||
| 565 | wkupaon_iclk_mux: wkupaon_iclk_mux { | |
| 566 | #clock-cells = <0>; | |
| 567 | compatible = "ti,mux-clock"; | |
| 568 | clocks = <&sys_clkin>, <&abe_lp_clk_div>; | |
| 569 | reg = <0x0108>; | |
| 570 | }; | |
| 571 | ||
| 572 | l3instr_ts_gclk_div: l3instr_ts_gclk_div { | |
| 573 | #clock-cells = <0>; | |
| 574 | compatible = "fixed-factor-clock"; | |
| 575 | clocks = <&wkupaon_iclk_mux>; | |
| 576 | clock-mult = <1>; | |
| 577 | clock-div = <1>; | |
| 578 | }; | |
| 579 | ||
| 580 | gpio1_dbclk: gpio1_dbclk { | |
| 581 | #clock-cells = <0>; | |
| 582 | compatible = "ti,gate-clock"; | |
| 583 | clocks = <&sys_32k_ck>; | |
| 584 | ti,bit-shift = <8>; | |
| 585 | reg = <0x1938>; | |
| 586 | }; | |
| 587 | ||
| 588 | timer1_gfclk_mux: timer1_gfclk_mux { | |
| 589 | #clock-cells = <0>; | |
| 590 | compatible = "ti,mux-clock"; | |
| 591 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 592 | ti,bit-shift = <24>; | |
| 593 | reg = <0x1940>; | |
| 594 | }; | |
| 595 | }; | |
| 596 | &cm_core_clocks { | |
| 597 | dpll_per_ck: dpll_per_ck { | |
| 598 | #clock-cells = <0>; | |
| 599 | compatible = "ti,omap4-dpll-clock"; | |
| 600 | clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; | |
| 601 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; | |
| 602 | }; | |
| 603 | ||
| 604 | dpll_per_x2_ck: dpll_per_x2_ck { | |
| 605 | #clock-cells = <0>; | |
| 606 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 607 | clocks = <&dpll_per_ck>; | |
| 608 | }; | |
| 609 | ||
| 610 | dpll_per_h11x2_ck: dpll_per_h11x2_ck { | |
| 611 | #clock-cells = <0>; | |
| 612 | compatible = "ti,divider-clock"; | |
| 613 | clocks = <&dpll_per_x2_ck>; | |
| 614 | ti,max-div = <63>; | |
| 85dc74e9 TK |
615 | reg = <0x0158>; |
| 616 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
617 | }; |
| 618 | ||
| 619 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { | |
| 620 | #clock-cells = <0>; | |
| 621 | compatible = "ti,divider-clock"; | |
| 622 | clocks = <&dpll_per_x2_ck>; | |
| 623 | ti,max-div = <63>; | |
| 85dc74e9 TK |
624 | reg = <0x015c>; |
| 625 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
626 | }; |
| 627 | ||
| 628 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { | |
| 629 | #clock-cells = <0>; | |
| 630 | compatible = "ti,divider-clock"; | |
| 631 | clocks = <&dpll_per_x2_ck>; | |
| 632 | ti,max-div = <63>; | |
| 85dc74e9 TK |
633 | reg = <0x0164>; |
| 634 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
635 | }; |
| 636 | ||
| 637 | dpll_per_m2_ck: dpll_per_m2_ck { | |
| 638 | #clock-cells = <0>; | |
| 639 | compatible = "ti,divider-clock"; | |
| 640 | clocks = <&dpll_per_ck>; | |
| 641 | ti,max-div = <31>; | |
| 85dc74e9 TK |
642 | reg = <0x0150>; |
| 643 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
644 | }; |
| 645 | ||
| 646 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { | |
| 647 | #clock-cells = <0>; | |
| 648 | compatible = "ti,divider-clock"; | |
| 649 | clocks = <&dpll_per_x2_ck>; | |
| 650 | ti,max-div = <31>; | |
| 85dc74e9 TK |
651 | reg = <0x0150>; |
| 652 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
653 | }; |
| 654 | ||
| 655 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { | |
| 656 | #clock-cells = <0>; | |
| 657 | compatible = "ti,divider-clock"; | |
| 658 | clocks = <&dpll_per_x2_ck>; | |
| 659 | ti,max-div = <31>; | |
| 85dc74e9 TK |
660 | reg = <0x0154>; |
| 661 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
662 | }; |
| 663 | ||
| 664 | dpll_unipro1_ck: dpll_unipro1_ck { | |
| 665 | #clock-cells = <0>; | |
| 666 | compatible = "ti,omap4-dpll-clock"; | |
| 667 | clocks = <&sys_clkin>, <&sys_clkin>; | |
| 668 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
| 669 | }; | |
| 670 | ||
| 671 | dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { | |
| 672 | #clock-cells = <0>; | |
| 673 | compatible = "fixed-factor-clock"; | |
| 674 | clocks = <&dpll_unipro1_ck>; | |
| 675 | clock-mult = <1>; | |
| 676 | clock-div = <1>; | |
| 677 | }; | |
| 678 | ||
| 679 | dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { | |
| 680 | #clock-cells = <0>; | |
| 681 | compatible = "ti,divider-clock"; | |
| 682 | clocks = <&dpll_unipro1_ck>; | |
| 683 | ti,max-div = <127>; | |
| 85dc74e9 TK |
684 | reg = <0x0210>; |
| 685 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
686 | }; |
| 687 | ||
| 688 | dpll_unipro2_ck: dpll_unipro2_ck { | |
| 689 | #clock-cells = <0>; | |
| 690 | compatible = "ti,omap4-dpll-clock"; | |
| 691 | clocks = <&sys_clkin>, <&sys_clkin>; | |
| 692 | reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; | |
| 693 | }; | |
| 694 | ||
| 695 | dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { | |
| 696 | #clock-cells = <0>; | |
| 697 | compatible = "fixed-factor-clock"; | |
| 698 | clocks = <&dpll_unipro2_ck>; | |
| 699 | clock-mult = <1>; | |
| 700 | clock-div = <1>; | |
| 701 | }; | |
| 702 | ||
| 703 | dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { | |
| 704 | #clock-cells = <0>; | |
| 705 | compatible = "ti,divider-clock"; | |
| 706 | clocks = <&dpll_unipro2_ck>; | |
| 707 | ti,max-div = <127>; | |
| 85dc74e9 TK |
708 | reg = <0x01d0>; |
| 709 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
710 | }; |
| 711 | ||
| 712 | dpll_usb_ck: dpll_usb_ck { | |
| 713 | #clock-cells = <0>; | |
| 714 | compatible = "ti,omap4-dpll-j-type-clock"; | |
| 715 | clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; | |
| 716 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; | |
| 717 | }; | |
| 718 | ||
| 719 | dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { | |
| 720 | #clock-cells = <0>; | |
| 721 | compatible = "fixed-factor-clock"; | |
| 722 | clocks = <&dpll_usb_ck>; | |
| 723 | clock-mult = <1>; | |
| 724 | clock-div = <1>; | |
| 725 | }; | |
| 726 | ||
| 727 | dpll_usb_m2_ck: dpll_usb_m2_ck { | |
| 728 | #clock-cells = <0>; | |
| 729 | compatible = "ti,divider-clock"; | |
| 730 | clocks = <&dpll_usb_ck>; | |
| 731 | ti,max-div = <127>; | |
| 85dc74e9 TK |
732 | reg = <0x0190>; |
| 733 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
734 | }; |
| 735 | ||
| 736 | func_128m_clk: func_128m_clk { | |
| 737 | #clock-cells = <0>; | |
| 738 | compatible = "fixed-factor-clock"; | |
| 739 | clocks = <&dpll_per_h11x2_ck>; | |
| 740 | clock-mult = <1>; | |
| 741 | clock-div = <2>; | |
| 742 | }; | |
| 743 | ||
| 744 | func_12m_fclk: func_12m_fclk { | |
| 745 | #clock-cells = <0>; | |
| 746 | compatible = "fixed-factor-clock"; | |
| 747 | clocks = <&dpll_per_m2x2_ck>; | |
| 748 | clock-mult = <1>; | |
| 749 | clock-div = <16>; | |
| 750 | }; | |
| 751 | ||
| 752 | func_24m_clk: func_24m_clk { | |
| 753 | #clock-cells = <0>; | |
| 754 | compatible = "fixed-factor-clock"; | |
| 755 | clocks = <&dpll_per_m2_ck>; | |
| 756 | clock-mult = <1>; | |
| 757 | clock-div = <4>; | |
| 758 | }; | |
| 759 | ||
| 760 | func_48m_fclk: func_48m_fclk { | |
| 761 | #clock-cells = <0>; | |
| 762 | compatible = "fixed-factor-clock"; | |
| 763 | clocks = <&dpll_per_m2x2_ck>; | |
| 764 | clock-mult = <1>; | |
| 765 | clock-div = <4>; | |
| 766 | }; | |
| 767 | ||
| 768 | func_96m_fclk: func_96m_fclk { | |
| 769 | #clock-cells = <0>; | |
| 770 | compatible = "fixed-factor-clock"; | |
| 771 | clocks = <&dpll_per_m2x2_ck>; | |
| 772 | clock-mult = <1>; | |
| 773 | clock-div = <2>; | |
| 774 | }; | |
| 775 | ||
| 776 | l3init_60m_fclk: l3init_60m_fclk { | |
| 777 | #clock-cells = <0>; | |
| 778 | compatible = "ti,divider-clock"; | |
| 779 | clocks = <&dpll_usb_m2_ck>; | |
| 780 | reg = <0x0104>; | |
| 781 | ti,dividers = <1>, <8>; | |
| 782 | }; | |
| 783 | ||
| 784 | dss_32khz_clk: dss_32khz_clk { | |
| 785 | #clock-cells = <0>; | |
| 786 | compatible = "ti,gate-clock"; | |
| 787 | clocks = <&sys_32k_ck>; | |
| 788 | ti,bit-shift = <11>; | |
| 789 | reg = <0x1420>; | |
| 790 | }; | |
| 791 | ||
| 792 | dss_48mhz_clk: dss_48mhz_clk { | |
| 793 | #clock-cells = <0>; | |
| 794 | compatible = "ti,gate-clock"; | |
| 795 | clocks = <&func_48m_fclk>; | |
| 796 | ti,bit-shift = <9>; | |
| 797 | reg = <0x1420>; | |
| 798 | }; | |
| 799 | ||
| 800 | dss_dss_clk: dss_dss_clk { | |
| 801 | #clock-cells = <0>; | |
| 802 | compatible = "ti,gate-clock"; | |
| 803 | clocks = <&dpll_per_h12x2_ck>; | |
| 804 | ti,bit-shift = <8>; | |
| 805 | reg = <0x1420>; | |
| 806 | }; | |
| 807 | ||
| 808 | dss_sys_clk: dss_sys_clk { | |
| 809 | #clock-cells = <0>; | |
| 810 | compatible = "ti,gate-clock"; | |
| 811 | clocks = <&dss_syc_gfclk_div>; | |
| 812 | ti,bit-shift = <10>; | |
| 813 | reg = <0x1420>; | |
| 814 | }; | |
| 815 | ||
| 816 | gpio2_dbclk: gpio2_dbclk { | |
| 817 | #clock-cells = <0>; | |
| 818 | compatible = "ti,gate-clock"; | |
| 819 | clocks = <&sys_32k_ck>; | |
| 820 | ti,bit-shift = <8>; | |
| 821 | reg = <0x1060>; | |
| 822 | }; | |
| 823 | ||
| 824 | gpio3_dbclk: gpio3_dbclk { | |
| 825 | #clock-cells = <0>; | |
| 826 | compatible = "ti,gate-clock"; | |
| 827 | clocks = <&sys_32k_ck>; | |
| 828 | ti,bit-shift = <8>; | |
| 829 | reg = <0x1068>; | |
| 830 | }; | |
| 831 | ||
| 832 | gpio4_dbclk: gpio4_dbclk { | |
| 833 | #clock-cells = <0>; | |
| 834 | compatible = "ti,gate-clock"; | |
| 835 | clocks = <&sys_32k_ck>; | |
| 836 | ti,bit-shift = <8>; | |
| 837 | reg = <0x1070>; | |
| 838 | }; | |
| 839 | ||
| 840 | gpio5_dbclk: gpio5_dbclk { | |
| 841 | #clock-cells = <0>; | |
| 842 | compatible = "ti,gate-clock"; | |
| 843 | clocks = <&sys_32k_ck>; | |
| 844 | ti,bit-shift = <8>; | |
| 845 | reg = <0x1078>; | |
| 846 | }; | |
| 847 | ||
| 848 | gpio6_dbclk: gpio6_dbclk { | |
| 849 | #clock-cells = <0>; | |
| 850 | compatible = "ti,gate-clock"; | |
| 851 | clocks = <&sys_32k_ck>; | |
| 852 | ti,bit-shift = <8>; | |
| 853 | reg = <0x1080>; | |
| 854 | }; | |
| 855 | ||
| 856 | gpio7_dbclk: gpio7_dbclk { | |
| 857 | #clock-cells = <0>; | |
| 858 | compatible = "ti,gate-clock"; | |
| 859 | clocks = <&sys_32k_ck>; | |
| 860 | ti,bit-shift = <8>; | |
| 861 | reg = <0x1110>; | |
| 862 | }; | |
| 863 | ||
| 864 | gpio8_dbclk: gpio8_dbclk { | |
| 865 | #clock-cells = <0>; | |
| 866 | compatible = "ti,gate-clock"; | |
| 867 | clocks = <&sys_32k_ck>; | |
| 868 | ti,bit-shift = <8>; | |
| 869 | reg = <0x1118>; | |
| 870 | }; | |
| 871 | ||
| 872 | iss_ctrlclk: iss_ctrlclk { | |
| 873 | #clock-cells = <0>; | |
| 874 | compatible = "ti,gate-clock"; | |
| 875 | clocks = <&func_96m_fclk>; | |
| 876 | ti,bit-shift = <8>; | |
| 877 | reg = <0x1320>; | |
| 878 | }; | |
| 879 | ||
| 880 | lli_txphy_clk: lli_txphy_clk { | |
| 881 | #clock-cells = <0>; | |
| 882 | compatible = "ti,gate-clock"; | |
| 883 | clocks = <&dpll_unipro1_clkdcoldo>; | |
| 884 | ti,bit-shift = <8>; | |
| 885 | reg = <0x0f20>; | |
| 886 | }; | |
| 887 | ||
| 888 | lli_txphy_ls_clk: lli_txphy_ls_clk { | |
| 889 | #clock-cells = <0>; | |
| 890 | compatible = "ti,gate-clock"; | |
| 891 | clocks = <&dpll_unipro1_m2_ck>; | |
| 892 | ti,bit-shift = <9>; | |
| 893 | reg = <0x0f20>; | |
| 894 | }; | |
| 895 | ||
| 896 | mmc1_32khz_clk: mmc1_32khz_clk { | |
| 897 | #clock-cells = <0>; | |
| 898 | compatible = "ti,gate-clock"; | |
| 899 | clocks = <&sys_32k_ck>; | |
| 900 | ti,bit-shift = <8>; | |
| 901 | reg = <0x1628>; | |
| 902 | }; | |
| 903 | ||
| 904 | sata_ref_clk: sata_ref_clk { | |
| 905 | #clock-cells = <0>; | |
| 906 | compatible = "ti,gate-clock"; | |
| 907 | clocks = <&sys_clkin>; | |
| 908 | ti,bit-shift = <8>; | |
| 909 | reg = <0x1688>; | |
| 910 | }; | |
| 911 | ||
| 912 | usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { | |
| 913 | #clock-cells = <0>; | |
| 914 | compatible = "ti,gate-clock"; | |
| 915 | clocks = <&dpll_usb_m2_ck>; | |
| 916 | ti,bit-shift = <13>; | |
| 917 | reg = <0x1658>; | |
| 918 | }; | |
| 919 | ||
| 920 | usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { | |
| 921 | #clock-cells = <0>; | |
| 922 | compatible = "ti,gate-clock"; | |
| 923 | clocks = <&dpll_usb_m2_ck>; | |
| 924 | ti,bit-shift = <14>; | |
| 925 | reg = <0x1658>; | |
| 926 | }; | |
| 927 | ||
| 928 | usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { | |
| 929 | #clock-cells = <0>; | |
| 930 | compatible = "ti,gate-clock"; | |
| 931 | clocks = <&dpll_usb_m2_ck>; | |
| 932 | ti,bit-shift = <7>; | |
| 933 | reg = <0x1658>; | |
| 934 | }; | |
| 935 | ||
| 936 | usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { | |
| 937 | #clock-cells = <0>; | |
| 938 | compatible = "ti,gate-clock"; | |
| 939 | clocks = <&l3init_60m_fclk>; | |
| 940 | ti,bit-shift = <11>; | |
| 941 | reg = <0x1658>; | |
| 942 | }; | |
| 943 | ||
| 944 | usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { | |
| 945 | #clock-cells = <0>; | |
| 946 | compatible = "ti,gate-clock"; | |
| 947 | clocks = <&l3init_60m_fclk>; | |
| 948 | ti,bit-shift = <12>; | |
| 949 | reg = <0x1658>; | |
| 950 | }; | |
| 951 | ||
| 952 | usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { | |
| 953 | #clock-cells = <0>; | |
| 954 | compatible = "ti,gate-clock"; | |
| 955 | clocks = <&l3init_60m_fclk>; | |
| 956 | ti,bit-shift = <6>; | |
| 957 | reg = <0x1658>; | |
| 958 | }; | |
| 959 | ||
| 960 | utmi_p1_gfclk: utmi_p1_gfclk { | |
| 961 | #clock-cells = <0>; | |
| 962 | compatible = "ti,mux-clock"; | |
| 963 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; | |
| 964 | ti,bit-shift = <24>; | |
| 965 | reg = <0x1658>; | |
| 966 | }; | |
| 967 | ||
| 968 | usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { | |
| 969 | #clock-cells = <0>; | |
| 970 | compatible = "ti,gate-clock"; | |
| 971 | clocks = <&utmi_p1_gfclk>; | |
| 972 | ti,bit-shift = <8>; | |
| 973 | reg = <0x1658>; | |
| 974 | }; | |
| 975 | ||
| 976 | utmi_p2_gfclk: utmi_p2_gfclk { | |
| 977 | #clock-cells = <0>; | |
| 978 | compatible = "ti,mux-clock"; | |
| 979 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; | |
| 980 | ti,bit-shift = <25>; | |
| 981 | reg = <0x1658>; | |
| 982 | }; | |
| 983 | ||
| 984 | usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { | |
| 985 | #clock-cells = <0>; | |
| 986 | compatible = "ti,gate-clock"; | |
| 987 | clocks = <&utmi_p2_gfclk>; | |
| 988 | ti,bit-shift = <9>; | |
| 989 | reg = <0x1658>; | |
| 990 | }; | |
| 991 | ||
| 992 | usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { | |
| 993 | #clock-cells = <0>; | |
| 994 | compatible = "ti,gate-clock"; | |
| 995 | clocks = <&l3init_60m_fclk>; | |
| 996 | ti,bit-shift = <10>; | |
| 997 | reg = <0x1658>; | |
| 998 | }; | |
| 999 | ||
| 1000 | usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { | |
| 1001 | #clock-cells = <0>; | |
| 1002 | compatible = "ti,gate-clock"; | |
| 1003 | clocks = <&dpll_usb_clkdcoldo>; | |
| 1004 | ti,bit-shift = <8>; | |
| 1005 | reg = <0x16f0>; | |
| 1006 | }; | |
| 1007 | ||
| 1008 | usb_phy_cm_clk32k: usb_phy_cm_clk32k { | |
| 1009 | #clock-cells = <0>; | |
| 1010 | compatible = "ti,gate-clock"; | |
| 1011 | clocks = <&sys_32k_ck>; | |
| 1012 | ti,bit-shift = <8>; | |
| 1013 | reg = <0x0640>; | |
| 1014 | }; | |
| 1015 | ||
| 1016 | usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { | |
| 1017 | #clock-cells = <0>; | |
| 1018 | compatible = "ti,gate-clock"; | |
| 1019 | clocks = <&l3init_60m_fclk>; | |
| 1020 | ti,bit-shift = <8>; | |
| 1021 | reg = <0x1668>; | |
| 1022 | }; | |
| 1023 | ||
| 1024 | usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { | |
| 1025 | #clock-cells = <0>; | |
| 1026 | compatible = "ti,gate-clock"; | |
| 1027 | clocks = <&l3init_60m_fclk>; | |
| 1028 | ti,bit-shift = <9>; | |
| 1029 | reg = <0x1668>; | |
| 1030 | }; | |
| 1031 | ||
| 1032 | usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { | |
| 1033 | #clock-cells = <0>; | |
| 1034 | compatible = "ti,gate-clock"; | |
| 1035 | clocks = <&l3init_60m_fclk>; | |
| 1036 | ti,bit-shift = <10>; | |
| 1037 | reg = <0x1668>; | |
| 1038 | }; | |
| 1039 | ||
| 1040 | fdif_fclk: fdif_fclk { | |
| 1041 | #clock-cells = <0>; | |
| 1042 | compatible = "ti,divider-clock"; | |
| 1043 | clocks = <&dpll_per_h11x2_ck>; | |
| 1044 | ti,bit-shift = <24>; | |
| 1045 | ti,max-div = <2>; | |
| 1046 | reg = <0x1328>; | |
| 1047 | }; | |
| 1048 | ||
| 1049 | gpu_core_gclk_mux: gpu_core_gclk_mux { | |
| 1050 | #clock-cells = <0>; | |
| 1051 | compatible = "ti,mux-clock"; | |
| 1052 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
| 1053 | ti,bit-shift = <24>; | |
| 1054 | reg = <0x1520>; | |
| 1055 | }; | |
| 1056 | ||
| 1057 | gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { | |
| 1058 | #clock-cells = <0>; | |
| 1059 | compatible = "ti,mux-clock"; | |
| 1060 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
| 1061 | ti,bit-shift = <25>; | |
| 1062 | reg = <0x1520>; | |
| 1063 | }; | |
| 1064 | ||
| 1065 | hsi_fclk: hsi_fclk { | |
| 1066 | #clock-cells = <0>; | |
| 1067 | compatible = "ti,divider-clock"; | |
| 1068 | clocks = <&dpll_per_m2x2_ck>; | |
| 1069 | ti,bit-shift = <24>; | |
| 1070 | ti,max-div = <2>; | |
| 1071 | reg = <0x1638>; | |
| 1072 | }; | |
| 1073 | ||
| 1074 | mmc1_fclk_mux: mmc1_fclk_mux { | |
| 1075 | #clock-cells = <0>; | |
| 1076 | compatible = "ti,mux-clock"; | |
| 1077 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1078 | ti,bit-shift = <24>; | |
| 1079 | reg = <0x1628>; | |
| 1080 | }; | |
| 1081 | ||
| 1082 | mmc1_fclk: mmc1_fclk { | |
| 1083 | #clock-cells = <0>; | |
| 1084 | compatible = "ti,divider-clock"; | |
| 1085 | clocks = <&mmc1_fclk_mux>; | |
| 1086 | ti,bit-shift = <25>; | |
| 1087 | ti,max-div = <2>; | |
| 1088 | reg = <0x1628>; | |
| 1089 | }; | |
| 1090 | ||
| 1091 | mmc2_fclk_mux: mmc2_fclk_mux { | |
| 1092 | #clock-cells = <0>; | |
| 1093 | compatible = "ti,mux-clock"; | |
| 1094 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1095 | ti,bit-shift = <24>; | |
| 1096 | reg = <0x1630>; | |
| 1097 | }; | |
| 1098 | ||
| 1099 | mmc2_fclk: mmc2_fclk { | |
| 1100 | #clock-cells = <0>; | |
| 1101 | compatible = "ti,divider-clock"; | |
| 1102 | clocks = <&mmc2_fclk_mux>; | |
| 1103 | ti,bit-shift = <25>; | |
| 1104 | ti,max-div = <2>; | |
| 1105 | reg = <0x1630>; | |
| 1106 | }; | |
| 1107 | ||
| 1108 | timer10_gfclk_mux: timer10_gfclk_mux { | |
| 1109 | #clock-cells = <0>; | |
| 1110 | compatible = "ti,mux-clock"; | |
| 1111 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1112 | ti,bit-shift = <24>; | |
| 1113 | reg = <0x1028>; | |
| 1114 | }; | |
| 1115 | ||
| 1116 | timer11_gfclk_mux: timer11_gfclk_mux { | |
| 1117 | #clock-cells = <0>; | |
| 1118 | compatible = "ti,mux-clock"; | |
| 1119 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1120 | ti,bit-shift = <24>; | |
| 1121 | reg = <0x1030>; | |
| 1122 | }; | |
| 1123 | ||
| 1124 | timer2_gfclk_mux: timer2_gfclk_mux { | |
| 1125 | #clock-cells = <0>; | |
| 1126 | compatible = "ti,mux-clock"; | |
| 1127 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1128 | ti,bit-shift = <24>; | |
| 1129 | reg = <0x1038>; | |
| 1130 | }; | |
| 1131 | ||
| 1132 | timer3_gfclk_mux: timer3_gfclk_mux { | |
| 1133 | #clock-cells = <0>; | |
| 1134 | compatible = "ti,mux-clock"; | |
| 1135 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1136 | ti,bit-shift = <24>; | |
| 1137 | reg = <0x1040>; | |
| 1138 | }; | |
| 1139 | ||
| 1140 | timer4_gfclk_mux: timer4_gfclk_mux { | |
| 1141 | #clock-cells = <0>; | |
| 1142 | compatible = "ti,mux-clock"; | |
| 1143 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1144 | ti,bit-shift = <24>; | |
| 1145 | reg = <0x1048>; | |
| 1146 | }; | |
| 1147 | ||
| 1148 | timer9_gfclk_mux: timer9_gfclk_mux { | |
| 1149 | #clock-cells = <0>; | |
| 1150 | compatible = "ti,mux-clock"; | |
| 1151 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1152 | ti,bit-shift = <24>; | |
| 1153 | reg = <0x1050>; | |
| 1154 | }; | |
| 1155 | }; | |
| 1156 | ||
| 1157 | &cm_core_clockdomains { | |
| 1158 | l3init_clkdm: l3init_clkdm { | |
| 1159 | compatible = "ti,clockdomain"; | |
| 1160 | clocks = <&dpll_usb_ck>; | |
| 1161 | }; | |
| 1162 | }; | |
| 1163 | ||
| 1164 | &scrm_clocks { | |
| 1165 | auxclk0_src_gate_ck: auxclk0_src_gate_ck { | |
| 1166 | #clock-cells = <0>; | |
| 1167 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1168 | clocks = <&dpll_core_m3x2_ck>; | |
| 1169 | ti,bit-shift = <8>; | |
| 1170 | reg = <0x0310>; | |
| 1171 | }; | |
| 1172 | ||
| 1173 | auxclk0_src_mux_ck: auxclk0_src_mux_ck { | |
| 1174 | #clock-cells = <0>; | |
| 1175 | compatible = "ti,composite-mux-clock"; | |
| 1176 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1177 | ti,bit-shift = <1>; | |
| 1178 | reg = <0x0310>; | |
| 1179 | }; | |
| 1180 | ||
| 1181 | auxclk0_src_ck: auxclk0_src_ck { | |
| 1182 | #clock-cells = <0>; | |
| 1183 | compatible = "ti,composite-clock"; | |
| 1184 | clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; | |
| 1185 | }; | |
| 1186 | ||
| 1187 | auxclk0_ck: auxclk0_ck { | |
| 1188 | #clock-cells = <0>; | |
| 1189 | compatible = "ti,divider-clock"; | |
| 1190 | clocks = <&auxclk0_src_ck>; | |
| 1191 | ti,bit-shift = <16>; | |
| 1192 | ti,max-div = <16>; | |
| 1193 | reg = <0x0310>; | |
| 1194 | }; | |
| 1195 | ||
| 1196 | auxclk1_src_gate_ck: auxclk1_src_gate_ck { | |
| 1197 | #clock-cells = <0>; | |
| 1198 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1199 | clocks = <&dpll_core_m3x2_ck>; | |
| 1200 | ti,bit-shift = <8>; | |
| 1201 | reg = <0x0314>; | |
| 1202 | }; | |
| 1203 | ||
| 1204 | auxclk1_src_mux_ck: auxclk1_src_mux_ck { | |
| 1205 | #clock-cells = <0>; | |
| 1206 | compatible = "ti,composite-mux-clock"; | |
| 1207 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1208 | ti,bit-shift = <1>; | |
| 1209 | reg = <0x0314>; | |
| 1210 | }; | |
| 1211 | ||
| 1212 | auxclk1_src_ck: auxclk1_src_ck { | |
| 1213 | #clock-cells = <0>; | |
| 1214 | compatible = "ti,composite-clock"; | |
| 1215 | clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; | |
| 1216 | }; | |
| 1217 | ||
| 1218 | auxclk1_ck: auxclk1_ck { | |
| 1219 | #clock-cells = <0>; | |
| 1220 | compatible = "ti,divider-clock"; | |
| 1221 | clocks = <&auxclk1_src_ck>; | |
| 1222 | ti,bit-shift = <16>; | |
| 1223 | ti,max-div = <16>; | |
| 1224 | reg = <0x0314>; | |
| 1225 | }; | |
| 1226 | ||
| 1227 | auxclk2_src_gate_ck: auxclk2_src_gate_ck { | |
| 1228 | #clock-cells = <0>; | |
| 1229 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1230 | clocks = <&dpll_core_m3x2_ck>; | |
| 1231 | ti,bit-shift = <8>; | |
| 1232 | reg = <0x0318>; | |
| 1233 | }; | |
| 1234 | ||
| 1235 | auxclk2_src_mux_ck: auxclk2_src_mux_ck { | |
| 1236 | #clock-cells = <0>; | |
| 1237 | compatible = "ti,composite-mux-clock"; | |
| 1238 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1239 | ti,bit-shift = <1>; | |
| 1240 | reg = <0x0318>; | |
| 1241 | }; | |
| 1242 | ||
| 1243 | auxclk2_src_ck: auxclk2_src_ck { | |
| 1244 | #clock-cells = <0>; | |
| 1245 | compatible = "ti,composite-clock"; | |
| 1246 | clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; | |
| 1247 | }; | |
| 1248 | ||
| 1249 | auxclk2_ck: auxclk2_ck { | |
| 1250 | #clock-cells = <0>; | |
| 1251 | compatible = "ti,divider-clock"; | |
| 1252 | clocks = <&auxclk2_src_ck>; | |
| 1253 | ti,bit-shift = <16>; | |
| 1254 | ti,max-div = <16>; | |
| 1255 | reg = <0x0318>; | |
| 1256 | }; | |
| 1257 | ||
| 1258 | auxclk3_src_gate_ck: auxclk3_src_gate_ck { | |
| 1259 | #clock-cells = <0>; | |
| 1260 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1261 | clocks = <&dpll_core_m3x2_ck>; | |
| 1262 | ti,bit-shift = <8>; | |
| 1263 | reg = <0x031c>; | |
| 1264 | }; | |
| 1265 | ||
| 1266 | auxclk3_src_mux_ck: auxclk3_src_mux_ck { | |
| 1267 | #clock-cells = <0>; | |
| 1268 | compatible = "ti,composite-mux-clock"; | |
| 1269 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1270 | ti,bit-shift = <1>; | |
| 1271 | reg = <0x031c>; | |
| 1272 | }; | |
| 1273 | ||
| 1274 | auxclk3_src_ck: auxclk3_src_ck { | |
| 1275 | #clock-cells = <0>; | |
| 1276 | compatible = "ti,composite-clock"; | |
| 1277 | clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; | |
| 1278 | }; | |
| 1279 | ||
| 1280 | auxclk3_ck: auxclk3_ck { | |
| 1281 | #clock-cells = <0>; | |
| 1282 | compatible = "ti,divider-clock"; | |
| 1283 | clocks = <&auxclk3_src_ck>; | |
| 1284 | ti,bit-shift = <16>; | |
| 1285 | ti,max-div = <16>; | |
| 1286 | reg = <0x031c>; | |
| 1287 | }; | |
| 1288 | ||
| 1289 | auxclk4_src_gate_ck: auxclk4_src_gate_ck { | |
| 1290 | #clock-cells = <0>; | |
| 1291 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1292 | clocks = <&dpll_core_m3x2_ck>; | |
| 1293 | ti,bit-shift = <8>; | |
| 1294 | reg = <0x0320>; | |
| 1295 | }; | |
| 1296 | ||
| 1297 | auxclk4_src_mux_ck: auxclk4_src_mux_ck { | |
| 1298 | #clock-cells = <0>; | |
| 1299 | compatible = "ti,composite-mux-clock"; | |
| 1300 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1301 | ti,bit-shift = <1>; | |
| 1302 | reg = <0x0320>; | |
| 1303 | }; | |
| 1304 | ||
| 1305 | auxclk4_src_ck: auxclk4_src_ck { | |
| 1306 | #clock-cells = <0>; | |
| 1307 | compatible = "ti,composite-clock"; | |
| 1308 | clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; | |
| 1309 | }; | |
| 1310 | ||
| 1311 | auxclk4_ck: auxclk4_ck { | |
| 1312 | #clock-cells = <0>; | |
| 1313 | compatible = "ti,divider-clock"; | |
| 1314 | clocks = <&auxclk4_src_ck>; | |
| 1315 | ti,bit-shift = <16>; | |
| 1316 | ti,max-div = <16>; | |
| 1317 | reg = <0x0320>; | |
| 1318 | }; | |
| 1319 | ||
| 1320 | auxclkreq0_ck: auxclkreq0_ck { | |
| 1321 | #clock-cells = <0>; | |
| 1322 | compatible = "ti,mux-clock"; | |
| 1323 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1324 | ti,bit-shift = <2>; | |
| 1325 | reg = <0x0210>; | |
| 1326 | }; | |
| 1327 | ||
| 1328 | auxclkreq1_ck: auxclkreq1_ck { | |
| 1329 | #clock-cells = <0>; | |
| 1330 | compatible = "ti,mux-clock"; | |
| 1331 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1332 | ti,bit-shift = <2>; | |
| 1333 | reg = <0x0214>; | |
| 1334 | }; | |
| 1335 | ||
| 1336 | auxclkreq2_ck: auxclkreq2_ck { | |
| 1337 | #clock-cells = <0>; | |
| 1338 | compatible = "ti,mux-clock"; | |
| 1339 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1340 | ti,bit-shift = <2>; | |
| 1341 | reg = <0x0218>; | |
| 1342 | }; | |
| 1343 | ||
| 1344 | auxclkreq3_ck: auxclkreq3_ck { | |
| 1345 | #clock-cells = <0>; | |
| 1346 | compatible = "ti,mux-clock"; | |
| 1347 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1348 | ti,bit-shift = <2>; | |
| 1349 | reg = <0x021c>; | |
| 1350 | }; | |
| 1351 | }; |