projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 85dc74e9 TK |
1 | /* |
| 2 | * Device Tree Source for OMAP5 clock data | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | &cm_core_aon_clocks { | |
| 11 | pad_clks_src_ck: pad_clks_src_ck { | |
| 12 | #clock-cells = <0>; | |
| 13 | compatible = "fixed-clock"; | |
| 14 | clock-frequency = <12000000>; | |
| 15 | }; | |
| 16 | ||
| 17 | pad_clks_ck: pad_clks_ck { | |
| 18 | #clock-cells = <0>; | |
| 19 | compatible = "ti,gate-clock"; | |
| 20 | clocks = <&pad_clks_src_ck>; | |
| 21 | ti,bit-shift = <8>; | |
| 22 | reg = <0x0108>; | |
| 23 | }; | |
| 24 | ||
| 25 | secure_32k_clk_src_ck: secure_32k_clk_src_ck { | |
| 26 | #clock-cells = <0>; | |
| 27 | compatible = "fixed-clock"; | |
| 28 | clock-frequency = <32768>; | |
| 29 | }; | |
| 30 | ||
| 31 | slimbus_src_clk: slimbus_src_clk { | |
| 32 | #clock-cells = <0>; | |
| 33 | compatible = "fixed-clock"; | |
| 34 | clock-frequency = <12000000>; | |
| 35 | }; | |
| 36 | ||
| 37 | slimbus_clk: slimbus_clk { | |
| 38 | #clock-cells = <0>; | |
| 39 | compatible = "ti,gate-clock"; | |
| 40 | clocks = <&slimbus_src_clk>; | |
| 41 | ti,bit-shift = <10>; | |
| 42 | reg = <0x0108>; | |
| 43 | }; | |
| 44 | ||
| 45 | sys_32k_ck: sys_32k_ck { | |
| 46 | #clock-cells = <0>; | |
| 47 | compatible = "fixed-clock"; | |
| 48 | clock-frequency = <32768>; | |
| 49 | }; | |
| 50 | ||
| 51 | virt_12000000_ck: virt_12000000_ck { | |
| 52 | #clock-cells = <0>; | |
| 53 | compatible = "fixed-clock"; | |
| 54 | clock-frequency = <12000000>; | |
| 55 | }; | |
| 56 | ||
| 57 | virt_13000000_ck: virt_13000000_ck { | |
| 58 | #clock-cells = <0>; | |
| 59 | compatible = "fixed-clock"; | |
| 60 | clock-frequency = <13000000>; | |
| 61 | }; | |
| 62 | ||
| 63 | virt_16800000_ck: virt_16800000_ck { | |
| 64 | #clock-cells = <0>; | |
| 65 | compatible = "fixed-clock"; | |
| 66 | clock-frequency = <16800000>; | |
| 67 | }; | |
| 68 | ||
| 69 | virt_19200000_ck: virt_19200000_ck { | |
| 70 | #clock-cells = <0>; | |
| 71 | compatible = "fixed-clock"; | |
| 72 | clock-frequency = <19200000>; | |
| 73 | }; | |
| 74 | ||
| 75 | virt_26000000_ck: virt_26000000_ck { | |
| 76 | #clock-cells = <0>; | |
| 77 | compatible = "fixed-clock"; | |
| 78 | clock-frequency = <26000000>; | |
| 79 | }; | |
| 80 | ||
| 81 | virt_27000000_ck: virt_27000000_ck { | |
| 82 | #clock-cells = <0>; | |
| 83 | compatible = "fixed-clock"; | |
| 84 | clock-frequency = <27000000>; | |
| 85 | }; | |
| 86 | ||
| 87 | virt_38400000_ck: virt_38400000_ck { | |
| 88 | #clock-cells = <0>; | |
| 89 | compatible = "fixed-clock"; | |
| 90 | clock-frequency = <38400000>; | |
| 91 | }; | |
| 92 | ||
| 93 | xclk60mhsp1_ck: xclk60mhsp1_ck { | |
| 94 | #clock-cells = <0>; | |
| 95 | compatible = "fixed-clock"; | |
| 96 | clock-frequency = <60000000>; | |
| 97 | }; | |
| 98 | ||
| 99 | xclk60mhsp2_ck: xclk60mhsp2_ck { | |
| 100 | #clock-cells = <0>; | |
| 101 | compatible = "fixed-clock"; | |
| 102 | clock-frequency = <60000000>; | |
| 103 | }; | |
| 104 | ||
| 105 | dpll_abe_ck: dpll_abe_ck { | |
| 106 | #clock-cells = <0>; | |
| 107 | compatible = "ti,omap4-dpll-m4xen-clock"; | |
| 108 | clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; | |
| 109 | reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; | |
| 110 | }; | |
| 111 | ||
| 112 | dpll_abe_x2_ck: dpll_abe_x2_ck { | |
| 113 | #clock-cells = <0>; | |
| 114 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 115 | clocks = <&dpll_abe_ck>; | |
| 116 | }; | |
| 117 | ||
| 118 | dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { | |
| 119 | #clock-cells = <0>; | |
| 120 | compatible = "ti,divider-clock"; | |
| 121 | clocks = <&dpll_abe_x2_ck>; | |
| 122 | ti,max-div = <31>; | |
| 85dc74e9 TK |
123 | reg = <0x01f0>; |
| 124 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
125 | }; |
| 126 | ||
| 127 | abe_24m_fclk: abe_24m_fclk { | |
| 128 | #clock-cells = <0>; | |
| 129 | compatible = "fixed-factor-clock"; | |
| 130 | clocks = <&dpll_abe_m2x2_ck>; | |
| 131 | clock-mult = <1>; | |
| 132 | clock-div = <8>; | |
| 133 | }; | |
| 134 | ||
| 135 | abe_clk: abe_clk { | |
| 136 | #clock-cells = <0>; | |
| 137 | compatible = "ti,divider-clock"; | |
| 138 | clocks = <&dpll_abe_m2x2_ck>; | |
| 139 | ti,max-div = <4>; | |
| 140 | reg = <0x0108>; | |
| 141 | ti,index-power-of-two; | |
| 142 | }; | |
| 143 | ||
| 144 | abe_iclk: abe_iclk { | |
| 145 | #clock-cells = <0>; | |
| 0922b339 PU |
146 | compatible = "ti,divider-clock"; |
| 147 | clocks = <&aess_fclk>; | |
| 148 | ti,bit-shift = <24>; | |
| 149 | reg = <0x0528>; | |
| 150 | ti,dividers = <2>, <1>; | |
| 85dc74e9 TK |
151 | }; |
| 152 | ||
| 153 | abe_lp_clk_div: abe_lp_clk_div { | |
| 154 | #clock-cells = <0>; | |
| 155 | compatible = "fixed-factor-clock"; | |
| 156 | clocks = <&dpll_abe_m2x2_ck>; | |
| 157 | clock-mult = <1>; | |
| 158 | clock-div = <16>; | |
| 159 | }; | |
| 160 | ||
| 161 | dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { | |
| 162 | #clock-cells = <0>; | |
| 163 | compatible = "ti,divider-clock"; | |
| 164 | clocks = <&dpll_abe_x2_ck>; | |
| 165 | ti,max-div = <31>; | |
| 85dc74e9 TK |
166 | reg = <0x01f4>; |
| 167 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
168 | }; |
| 169 | ||
| 170 | dpll_core_ck: dpll_core_ck { | |
| 171 | #clock-cells = <0>; | |
| 172 | compatible = "ti,omap4-dpll-core-clock"; | |
| 173 | clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; | |
| 174 | reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; | |
| 175 | }; | |
| 176 | ||
| 177 | dpll_core_x2_ck: dpll_core_x2_ck { | |
| 178 | #clock-cells = <0>; | |
| 179 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 180 | clocks = <&dpll_core_ck>; | |
| 181 | }; | |
| 182 | ||
| 183 | dpll_core_h21x2_ck: dpll_core_h21x2_ck { | |
| 184 | #clock-cells = <0>; | |
| 185 | compatible = "ti,divider-clock"; | |
| 186 | clocks = <&dpll_core_x2_ck>; | |
| 187 | ti,max-div = <63>; | |
| 85dc74e9 TK |
188 | reg = <0x0150>; |
| 189 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
190 | }; |
| 191 | ||
| 192 | c2c_fclk: c2c_fclk { | |
| 193 | #clock-cells = <0>; | |
| 194 | compatible = "fixed-factor-clock"; | |
| 195 | clocks = <&dpll_core_h21x2_ck>; | |
| 196 | clock-mult = <1>; | |
| 197 | clock-div = <1>; | |
| 198 | }; | |
| 199 | ||
| 200 | c2c_iclk: c2c_iclk { | |
| 201 | #clock-cells = <0>; | |
| 202 | compatible = "fixed-factor-clock"; | |
| 203 | clocks = <&c2c_fclk>; | |
| 204 | clock-mult = <1>; | |
| 205 | clock-div = <2>; | |
| 206 | }; | |
| 207 | ||
| 208 | dpll_core_h11x2_ck: dpll_core_h11x2_ck { | |
| 209 | #clock-cells = <0>; | |
| 210 | compatible = "ti,divider-clock"; | |
| 211 | clocks = <&dpll_core_x2_ck>; | |
| 212 | ti,max-div = <63>; | |
| 85dc74e9 TK |
213 | reg = <0x0138>; |
| 214 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
215 | }; |
| 216 | ||
| 217 | dpll_core_h12x2_ck: dpll_core_h12x2_ck { | |
| 218 | #clock-cells = <0>; | |
| 219 | compatible = "ti,divider-clock"; | |
| 220 | clocks = <&dpll_core_x2_ck>; | |
| 221 | ti,max-div = <63>; | |
| 85dc74e9 TK |
222 | reg = <0x013c>; |
| 223 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
224 | }; |
| 225 | ||
| 226 | dpll_core_h13x2_ck: dpll_core_h13x2_ck { | |
| 227 | #clock-cells = <0>; | |
| 228 | compatible = "ti,divider-clock"; | |
| 229 | clocks = <&dpll_core_x2_ck>; | |
| 230 | ti,max-div = <63>; | |
| 85dc74e9 TK |
231 | reg = <0x0140>; |
| 232 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
233 | }; |
| 234 | ||
| 235 | dpll_core_h14x2_ck: dpll_core_h14x2_ck { | |
| 236 | #clock-cells = <0>; | |
| 237 | compatible = "ti,divider-clock"; | |
| 238 | clocks = <&dpll_core_x2_ck>; | |
| 239 | ti,max-div = <63>; | |
| 85dc74e9 TK |
240 | reg = <0x0144>; |
| 241 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
242 | }; |
| 243 | ||
| 244 | dpll_core_h22x2_ck: dpll_core_h22x2_ck { | |
| 245 | #clock-cells = <0>; | |
| 246 | compatible = "ti,divider-clock"; | |
| 247 | clocks = <&dpll_core_x2_ck>; | |
| 248 | ti,max-div = <63>; | |
| 85dc74e9 TK |
249 | reg = <0x0154>; |
| 250 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
251 | }; |
| 252 | ||
| 253 | dpll_core_h23x2_ck: dpll_core_h23x2_ck { | |
| 254 | #clock-cells = <0>; | |
| 255 | compatible = "ti,divider-clock"; | |
| 256 | clocks = <&dpll_core_x2_ck>; | |
| 257 | ti,max-div = <63>; | |
| 85dc74e9 TK |
258 | reg = <0x0158>; |
| 259 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
260 | }; |
| 261 | ||
| 262 | dpll_core_h24x2_ck: dpll_core_h24x2_ck { | |
| 263 | #clock-cells = <0>; | |
| 264 | compatible = "ti,divider-clock"; | |
| 265 | clocks = <&dpll_core_x2_ck>; | |
| 266 | ti,max-div = <63>; | |
| 85dc74e9 TK |
267 | reg = <0x015c>; |
| 268 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
269 | }; |
| 270 | ||
| 271 | dpll_core_m2_ck: dpll_core_m2_ck { | |
| 272 | #clock-cells = <0>; | |
| 273 | compatible = "ti,divider-clock"; | |
| 274 | clocks = <&dpll_core_ck>; | |
| 275 | ti,max-div = <31>; | |
| 85dc74e9 TK |
276 | reg = <0x0130>; |
| 277 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
278 | }; |
| 279 | ||
| 280 | dpll_core_m3x2_ck: dpll_core_m3x2_ck { | |
| 281 | #clock-cells = <0>; | |
| 282 | compatible = "ti,divider-clock"; | |
| 283 | clocks = <&dpll_core_x2_ck>; | |
| 284 | ti,max-div = <31>; | |
| 85dc74e9 TK |
285 | reg = <0x0134>; |
| 286 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
287 | }; |
| 288 | ||
| 289 | iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { | |
| 290 | #clock-cells = <0>; | |
| 291 | compatible = "fixed-factor-clock"; | |
| 292 | clocks = <&dpll_core_h12x2_ck>; | |
| 293 | clock-mult = <1>; | |
| 294 | clock-div = <1>; | |
| 295 | }; | |
| 296 | ||
| 297 | dpll_iva_ck: dpll_iva_ck { | |
| 298 | #clock-cells = <0>; | |
| 299 | compatible = "ti,omap4-dpll-clock"; | |
| 300 | clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; | |
| 301 | reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; | |
| 302 | }; | |
| 303 | ||
| 304 | dpll_iva_x2_ck: dpll_iva_x2_ck { | |
| 305 | #clock-cells = <0>; | |
| 306 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 307 | clocks = <&dpll_iva_ck>; | |
| 308 | }; | |
| 309 | ||
| 310 | dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { | |
| 311 | #clock-cells = <0>; | |
| 312 | compatible = "ti,divider-clock"; | |
| 313 | clocks = <&dpll_iva_x2_ck>; | |
| 314 | ti,max-div = <63>; | |
| 85dc74e9 TK |
315 | reg = <0x01b8>; |
| 316 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
317 | }; |
| 318 | ||
| 319 | dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { | |
| 320 | #clock-cells = <0>; | |
| 321 | compatible = "ti,divider-clock"; | |
| 322 | clocks = <&dpll_iva_x2_ck>; | |
| 323 | ti,max-div = <63>; | |
| 85dc74e9 TK |
324 | reg = <0x01bc>; |
| 325 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
326 | }; |
| 327 | ||
| 328 | mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { | |
| 329 | #clock-cells = <0>; | |
| 330 | compatible = "fixed-factor-clock"; | |
| 331 | clocks = <&dpll_core_h12x2_ck>; | |
| 332 | clock-mult = <1>; | |
| 333 | clock-div = <1>; | |
| 334 | }; | |
| 335 | ||
| 336 | dpll_mpu_ck: dpll_mpu_ck { | |
| 337 | #clock-cells = <0>; | |
| 7e148070 | 338 | compatible = "ti,omap5-mpu-dpll-clock"; |
| 85dc74e9 TK |
339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; |
| 340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | |
| 341 | }; | |
| 342 | ||
| 343 | dpll_mpu_m2_ck: dpll_mpu_m2_ck { | |
| 344 | #clock-cells = <0>; | |
| 345 | compatible = "ti,divider-clock"; | |
| 346 | clocks = <&dpll_mpu_ck>; | |
| 347 | ti,max-div = <31>; | |
| 85dc74e9 TK |
348 | reg = <0x0170>; |
| 349 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
350 | }; |
| 351 | ||
| 352 | per_dpll_hs_clk_div: per_dpll_hs_clk_div { | |
| 353 | #clock-cells = <0>; | |
| 354 | compatible = "fixed-factor-clock"; | |
| 355 | clocks = <&dpll_abe_m3x2_ck>; | |
| 356 | clock-mult = <1>; | |
| 357 | clock-div = <2>; | |
| 358 | }; | |
| 359 | ||
| 360 | usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { | |
| 361 | #clock-cells = <0>; | |
| 362 | compatible = "fixed-factor-clock"; | |
| 363 | clocks = <&dpll_abe_m3x2_ck>; | |
| 364 | clock-mult = <1>; | |
| 365 | clock-div = <3>; | |
| 366 | }; | |
| 367 | ||
| 368 | l3_iclk_div: l3_iclk_div { | |
| 369 | #clock-cells = <0>; | |
| 370 | compatible = "fixed-factor-clock"; | |
| 371 | clocks = <&dpll_core_h12x2_ck>; | |
| 372 | clock-mult = <1>; | |
| 373 | clock-div = <1>; | |
| 374 | }; | |
| 375 | ||
| 376 | gpu_l3_iclk: gpu_l3_iclk { | |
| 377 | #clock-cells = <0>; | |
| 378 | compatible = "fixed-factor-clock"; | |
| 379 | clocks = <&l3_iclk_div>; | |
| 380 | clock-mult = <1>; | |
| 381 | clock-div = <1>; | |
| 382 | }; | |
| 383 | ||
| 384 | l4_root_clk_div: l4_root_clk_div { | |
| 385 | #clock-cells = <0>; | |
| 386 | compatible = "fixed-factor-clock"; | |
| 387 | clocks = <&l3_iclk_div>; | |
| 388 | clock-mult = <1>; | |
| 389 | clock-div = <1>; | |
| 390 | }; | |
| 391 | ||
| 392 | slimbus1_slimbus_clk: slimbus1_slimbus_clk { | |
| 393 | #clock-cells = <0>; | |
| 394 | compatible = "ti,gate-clock"; | |
| 395 | clocks = <&slimbus_clk>; | |
| 396 | ti,bit-shift = <11>; | |
| 397 | reg = <0x0560>; | |
| 398 | }; | |
| 399 | ||
| 400 | aess_fclk: aess_fclk { | |
| 401 | #clock-cells = <0>; | |
| 402 | compatible = "ti,divider-clock"; | |
| 403 | clocks = <&abe_clk>; | |
| 404 | ti,bit-shift = <24>; | |
| 405 | ti,max-div = <2>; | |
| 406 | reg = <0x0528>; | |
| 407 | }; | |
| 408 | ||
| 409 | dmic_sync_mux_ck: dmic_sync_mux_ck { | |
| 410 | #clock-cells = <0>; | |
| 411 | compatible = "ti,mux-clock"; | |
| 412 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 413 | ti,bit-shift = <26>; | |
| 414 | reg = <0x0538>; | |
| 415 | }; | |
| 416 | ||
| 417 | dmic_gfclk: dmic_gfclk { | |
| 418 | #clock-cells = <0>; | |
| 419 | compatible = "ti,mux-clock"; | |
| 420 | clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 421 | ti,bit-shift = <24>; | |
| 422 | reg = <0x0538>; | |
| 423 | }; | |
| 424 | ||
| 425 | mcasp_sync_mux_ck: mcasp_sync_mux_ck { | |
| 426 | #clock-cells = <0>; | |
| 427 | compatible = "ti,mux-clock"; | |
| 428 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 429 | ti,bit-shift = <26>; | |
| 430 | reg = <0x0540>; | |
| 431 | }; | |
| 432 | ||
| 433 | mcasp_gfclk: mcasp_gfclk { | |
| 434 | #clock-cells = <0>; | |
| 435 | compatible = "ti,mux-clock"; | |
| 436 | clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 437 | ti,bit-shift = <24>; | |
| 438 | reg = <0x0540>; | |
| 439 | }; | |
| 440 | ||
| 441 | mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { | |
| 442 | #clock-cells = <0>; | |
| 443 | compatible = "ti,mux-clock"; | |
| 444 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 445 | ti,bit-shift = <26>; | |
| 446 | reg = <0x0548>; | |
| 447 | }; | |
| 448 | ||
| 449 | mcbsp1_gfclk: mcbsp1_gfclk { | |
| 450 | #clock-cells = <0>; | |
| 451 | compatible = "ti,mux-clock"; | |
| 452 | clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 453 | ti,bit-shift = <24>; | |
| 454 | reg = <0x0548>; | |
| 455 | }; | |
| 456 | ||
| 457 | mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { | |
| 458 | #clock-cells = <0>; | |
| 459 | compatible = "ti,mux-clock"; | |
| 460 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 461 | ti,bit-shift = <26>; | |
| 462 | reg = <0x0550>; | |
| 463 | }; | |
| 464 | ||
| 465 | mcbsp2_gfclk: mcbsp2_gfclk { | |
| 466 | #clock-cells = <0>; | |
| 467 | compatible = "ti,mux-clock"; | |
| 468 | clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 469 | ti,bit-shift = <24>; | |
| 470 | reg = <0x0550>; | |
| 471 | }; | |
| 472 | ||
| 473 | mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { | |
| 474 | #clock-cells = <0>; | |
| 475 | compatible = "ti,mux-clock"; | |
| 476 | clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; | |
| 477 | ti,bit-shift = <26>; | |
| 478 | reg = <0x0558>; | |
| 479 | }; | |
| 480 | ||
| 481 | mcbsp3_gfclk: mcbsp3_gfclk { | |
| 482 | #clock-cells = <0>; | |
| 483 | compatible = "ti,mux-clock"; | |
| 484 | clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; | |
| 485 | ti,bit-shift = <24>; | |
| 486 | reg = <0x0558>; | |
| 487 | }; | |
| 488 | ||
| 489 | timer5_gfclk_mux: timer5_gfclk_mux { | |
| 490 | #clock-cells = <0>; | |
| 491 | compatible = "ti,mux-clock"; | |
| 492 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 493 | ti,bit-shift = <24>; | |
| 494 | reg = <0x0568>; | |
| 495 | }; | |
| 496 | ||
| 497 | timer6_gfclk_mux: timer6_gfclk_mux { | |
| 498 | #clock-cells = <0>; | |
| 499 | compatible = "ti,mux-clock"; | |
| 500 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 501 | ti,bit-shift = <24>; | |
| 502 | reg = <0x0570>; | |
| 503 | }; | |
| 504 | ||
| 505 | timer7_gfclk_mux: timer7_gfclk_mux { | |
| 506 | #clock-cells = <0>; | |
| 507 | compatible = "ti,mux-clock"; | |
| 508 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 509 | ti,bit-shift = <24>; | |
| 510 | reg = <0x0578>; | |
| 511 | }; | |
| 512 | ||
| 513 | timer8_gfclk_mux: timer8_gfclk_mux { | |
| 514 | #clock-cells = <0>; | |
| 515 | compatible = "ti,mux-clock"; | |
| 516 | clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; | |
| 517 | ti,bit-shift = <24>; | |
| 518 | reg = <0x0580>; | |
| 519 | }; | |
| 520 | ||
| 521 | dummy_ck: dummy_ck { | |
| 522 | #clock-cells = <0>; | |
| 523 | compatible = "fixed-clock"; | |
| 524 | clock-frequency = <0>; | |
| 525 | }; | |
| 526 | }; | |
| 527 | &prm_clocks { | |
| 528 | sys_clkin: sys_clkin { | |
| 529 | #clock-cells = <0>; | |
| 530 | compatible = "ti,mux-clock"; | |
| 531 | clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; | |
| 532 | reg = <0x0110>; | |
| 533 | ti,index-starts-at-one; | |
| 534 | }; | |
| 535 | ||
| 536 | abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { | |
| 537 | #clock-cells = <0>; | |
| 538 | compatible = "ti,mux-clock"; | |
| 539 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 540 | reg = <0x0108>; | |
| 541 | }; | |
| 542 | ||
| 543 | abe_dpll_clk_mux: abe_dpll_clk_mux { | |
| 544 | #clock-cells = <0>; | |
| 545 | compatible = "ti,mux-clock"; | |
| 546 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 547 | reg = <0x010c>; | |
| 548 | }; | |
| 549 | ||
| 550 | custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { | |
| 551 | #clock-cells = <0>; | |
| 552 | compatible = "fixed-factor-clock"; | |
| 553 | clocks = <&sys_clkin>; | |
| 554 | clock-mult = <1>; | |
| 555 | clock-div = <2>; | |
| 556 | }; | |
| 557 | ||
| 558 | dss_syc_gfclk_div: dss_syc_gfclk_div { | |
| 559 | #clock-cells = <0>; | |
| 560 | compatible = "fixed-factor-clock"; | |
| 561 | clocks = <&sys_clkin>; | |
| 562 | clock-mult = <1>; | |
| 563 | clock-div = <1>; | |
| 564 | }; | |
| 565 | ||
| 566 | wkupaon_iclk_mux: wkupaon_iclk_mux { | |
| 567 | #clock-cells = <0>; | |
| 568 | compatible = "ti,mux-clock"; | |
| 569 | clocks = <&sys_clkin>, <&abe_lp_clk_div>; | |
| 570 | reg = <0x0108>; | |
| 571 | }; | |
| 572 | ||
| 573 | l3instr_ts_gclk_div: l3instr_ts_gclk_div { | |
| 574 | #clock-cells = <0>; | |
| 575 | compatible = "fixed-factor-clock"; | |
| 576 | clocks = <&wkupaon_iclk_mux>; | |
| 577 | clock-mult = <1>; | |
| 578 | clock-div = <1>; | |
| 579 | }; | |
| 580 | ||
| 581 | gpio1_dbclk: gpio1_dbclk { | |
| 582 | #clock-cells = <0>; | |
| 583 | compatible = "ti,gate-clock"; | |
| 584 | clocks = <&sys_32k_ck>; | |
| 585 | ti,bit-shift = <8>; | |
| 586 | reg = <0x1938>; | |
| 587 | }; | |
| 588 | ||
| 589 | timer1_gfclk_mux: timer1_gfclk_mux { | |
| 590 | #clock-cells = <0>; | |
| 591 | compatible = "ti,mux-clock"; | |
| 592 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 593 | ti,bit-shift = <24>; | |
| 594 | reg = <0x1940>; | |
| 595 | }; | |
| 596 | }; | |
| 597 | &cm_core_clocks { | |
| 598 | dpll_per_ck: dpll_per_ck { | |
| 599 | #clock-cells = <0>; | |
| 600 | compatible = "ti,omap4-dpll-clock"; | |
| 601 | clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; | |
| 602 | reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; | |
| 603 | }; | |
| 604 | ||
| 605 | dpll_per_x2_ck: dpll_per_x2_ck { | |
| 606 | #clock-cells = <0>; | |
| 607 | compatible = "ti,omap4-dpll-x2-clock"; | |
| 608 | clocks = <&dpll_per_ck>; | |
| 609 | }; | |
| 610 | ||
| 611 | dpll_per_h11x2_ck: dpll_per_h11x2_ck { | |
| 612 | #clock-cells = <0>; | |
| 613 | compatible = "ti,divider-clock"; | |
| 614 | clocks = <&dpll_per_x2_ck>; | |
| 615 | ti,max-div = <63>; | |
| 85dc74e9 TK |
616 | reg = <0x0158>; |
| 617 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
618 | }; |
| 619 | ||
| 620 | dpll_per_h12x2_ck: dpll_per_h12x2_ck { | |
| 621 | #clock-cells = <0>; | |
| 622 | compatible = "ti,divider-clock"; | |
| 623 | clocks = <&dpll_per_x2_ck>; | |
| 624 | ti,max-div = <63>; | |
| 85dc74e9 TK |
625 | reg = <0x015c>; |
| 626 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
627 | }; |
| 628 | ||
| 629 | dpll_per_h14x2_ck: dpll_per_h14x2_ck { | |
| 630 | #clock-cells = <0>; | |
| 631 | compatible = "ti,divider-clock"; | |
| 632 | clocks = <&dpll_per_x2_ck>; | |
| 633 | ti,max-div = <63>; | |
| 85dc74e9 TK |
634 | reg = <0x0164>; |
| 635 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
636 | }; |
| 637 | ||
| 638 | dpll_per_m2_ck: dpll_per_m2_ck { | |
| 639 | #clock-cells = <0>; | |
| 640 | compatible = "ti,divider-clock"; | |
| 641 | clocks = <&dpll_per_ck>; | |
| 642 | ti,max-div = <31>; | |
| 85dc74e9 TK |
643 | reg = <0x0150>; |
| 644 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
645 | }; |
| 646 | ||
| 647 | dpll_per_m2x2_ck: dpll_per_m2x2_ck { | |
| 648 | #clock-cells = <0>; | |
| 649 | compatible = "ti,divider-clock"; | |
| 650 | clocks = <&dpll_per_x2_ck>; | |
| 651 | ti,max-div = <31>; | |
| 85dc74e9 TK |
652 | reg = <0x0150>; |
| 653 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
654 | }; |
| 655 | ||
| 656 | dpll_per_m3x2_ck: dpll_per_m3x2_ck { | |
| 657 | #clock-cells = <0>; | |
| 658 | compatible = "ti,divider-clock"; | |
| 659 | clocks = <&dpll_per_x2_ck>; | |
| 660 | ti,max-div = <31>; | |
| 85dc74e9 TK |
661 | reg = <0x0154>; |
| 662 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
663 | }; |
| 664 | ||
| 665 | dpll_unipro1_ck: dpll_unipro1_ck { | |
| 666 | #clock-cells = <0>; | |
| 667 | compatible = "ti,omap4-dpll-clock"; | |
| 668 | clocks = <&sys_clkin>, <&sys_clkin>; | |
| 669 | reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; | |
| 670 | }; | |
| 671 | ||
| 672 | dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { | |
| 673 | #clock-cells = <0>; | |
| 674 | compatible = "fixed-factor-clock"; | |
| 675 | clocks = <&dpll_unipro1_ck>; | |
| 676 | clock-mult = <1>; | |
| 677 | clock-div = <1>; | |
| 678 | }; | |
| 679 | ||
| 680 | dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { | |
| 681 | #clock-cells = <0>; | |
| 682 | compatible = "ti,divider-clock"; | |
| 683 | clocks = <&dpll_unipro1_ck>; | |
| 684 | ti,max-div = <127>; | |
| 85dc74e9 TK |
685 | reg = <0x0210>; |
| 686 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
687 | }; |
| 688 | ||
| 689 | dpll_unipro2_ck: dpll_unipro2_ck { | |
| 690 | #clock-cells = <0>; | |
| 691 | compatible = "ti,omap4-dpll-clock"; | |
| 692 | clocks = <&sys_clkin>, <&sys_clkin>; | |
| 693 | reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; | |
| 694 | }; | |
| 695 | ||
| 696 | dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { | |
| 697 | #clock-cells = <0>; | |
| 698 | compatible = "fixed-factor-clock"; | |
| 699 | clocks = <&dpll_unipro2_ck>; | |
| 700 | clock-mult = <1>; | |
| 701 | clock-div = <1>; | |
| 702 | }; | |
| 703 | ||
| 704 | dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { | |
| 705 | #clock-cells = <0>; | |
| 706 | compatible = "ti,divider-clock"; | |
| 707 | clocks = <&dpll_unipro2_ck>; | |
| 708 | ti,max-div = <127>; | |
| 85dc74e9 TK |
709 | reg = <0x01d0>; |
| 710 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
711 | }; |
| 712 | ||
| 713 | dpll_usb_ck: dpll_usb_ck { | |
| 714 | #clock-cells = <0>; | |
| 715 | compatible = "ti,omap4-dpll-j-type-clock"; | |
| 716 | clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; | |
| 717 | reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; | |
| 718 | }; | |
| 719 | ||
| 720 | dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { | |
| 721 | #clock-cells = <0>; | |
| 722 | compatible = "fixed-factor-clock"; | |
| 723 | clocks = <&dpll_usb_ck>; | |
| 724 | clock-mult = <1>; | |
| 725 | clock-div = <1>; | |
| 726 | }; | |
| 727 | ||
| 728 | dpll_usb_m2_ck: dpll_usb_m2_ck { | |
| 729 | #clock-cells = <0>; | |
| 730 | compatible = "ti,divider-clock"; | |
| 731 | clocks = <&dpll_usb_ck>; | |
| 732 | ti,max-div = <127>; | |
| 85dc74e9 TK |
733 | reg = <0x0190>; |
| 734 | ti,index-starts-at-one; | |
| 85dc74e9 TK |
735 | }; |
| 736 | ||
| 737 | func_128m_clk: func_128m_clk { | |
| 738 | #clock-cells = <0>; | |
| 739 | compatible = "fixed-factor-clock"; | |
| 740 | clocks = <&dpll_per_h11x2_ck>; | |
| 741 | clock-mult = <1>; | |
| 742 | clock-div = <2>; | |
| 743 | }; | |
| 744 | ||
| 745 | func_12m_fclk: func_12m_fclk { | |
| 746 | #clock-cells = <0>; | |
| 747 | compatible = "fixed-factor-clock"; | |
| 748 | clocks = <&dpll_per_m2x2_ck>; | |
| 749 | clock-mult = <1>; | |
| 750 | clock-div = <16>; | |
| 751 | }; | |
| 752 | ||
| 753 | func_24m_clk: func_24m_clk { | |
| 754 | #clock-cells = <0>; | |
| 755 | compatible = "fixed-factor-clock"; | |
| 756 | clocks = <&dpll_per_m2_ck>; | |
| 757 | clock-mult = <1>; | |
| 758 | clock-div = <4>; | |
| 759 | }; | |
| 760 | ||
| 761 | func_48m_fclk: func_48m_fclk { | |
| 762 | #clock-cells = <0>; | |
| 763 | compatible = "fixed-factor-clock"; | |
| 764 | clocks = <&dpll_per_m2x2_ck>; | |
| 765 | clock-mult = <1>; | |
| 766 | clock-div = <4>; | |
| 767 | }; | |
| 768 | ||
| 769 | func_96m_fclk: func_96m_fclk { | |
| 770 | #clock-cells = <0>; | |
| 771 | compatible = "fixed-factor-clock"; | |
| 772 | clocks = <&dpll_per_m2x2_ck>; | |
| 773 | clock-mult = <1>; | |
| 774 | clock-div = <2>; | |
| 775 | }; | |
| 776 | ||
| 777 | l3init_60m_fclk: l3init_60m_fclk { | |
| 778 | #clock-cells = <0>; | |
| 779 | compatible = "ti,divider-clock"; | |
| 780 | clocks = <&dpll_usb_m2_ck>; | |
| 781 | reg = <0x0104>; | |
| 782 | ti,dividers = <1>, <8>; | |
| 783 | }; | |
| 784 | ||
| 785 | dss_32khz_clk: dss_32khz_clk { | |
| 786 | #clock-cells = <0>; | |
| 787 | compatible = "ti,gate-clock"; | |
| 788 | clocks = <&sys_32k_ck>; | |
| 789 | ti,bit-shift = <11>; | |
| 790 | reg = <0x1420>; | |
| 791 | }; | |
| 792 | ||
| 793 | dss_48mhz_clk: dss_48mhz_clk { | |
| 794 | #clock-cells = <0>; | |
| 795 | compatible = "ti,gate-clock"; | |
| 796 | clocks = <&func_48m_fclk>; | |
| 797 | ti,bit-shift = <9>; | |
| 798 | reg = <0x1420>; | |
| 799 | }; | |
| 800 | ||
| 801 | dss_dss_clk: dss_dss_clk { | |
| 802 | #clock-cells = <0>; | |
| 803 | compatible = "ti,gate-clock"; | |
| 804 | clocks = <&dpll_per_h12x2_ck>; | |
| 805 | ti,bit-shift = <8>; | |
| 806 | reg = <0x1420>; | |
| 1be7b88c | 807 | ti,set-rate-parent; |
| 85dc74e9 TK |
808 | }; |
| 809 | ||
| 810 | dss_sys_clk: dss_sys_clk { | |
| 811 | #clock-cells = <0>; | |
| 812 | compatible = "ti,gate-clock"; | |
| 813 | clocks = <&dss_syc_gfclk_div>; | |
| 814 | ti,bit-shift = <10>; | |
| 815 | reg = <0x1420>; | |
| 816 | }; | |
| 817 | ||
| 818 | gpio2_dbclk: gpio2_dbclk { | |
| 819 | #clock-cells = <0>; | |
| 820 | compatible = "ti,gate-clock"; | |
| 821 | clocks = <&sys_32k_ck>; | |
| 822 | ti,bit-shift = <8>; | |
| 823 | reg = <0x1060>; | |
| 824 | }; | |
| 825 | ||
| 826 | gpio3_dbclk: gpio3_dbclk { | |
| 827 | #clock-cells = <0>; | |
| 828 | compatible = "ti,gate-clock"; | |
| 829 | clocks = <&sys_32k_ck>; | |
| 830 | ti,bit-shift = <8>; | |
| 831 | reg = <0x1068>; | |
| 832 | }; | |
| 833 | ||
| 834 | gpio4_dbclk: gpio4_dbclk { | |
| 835 | #clock-cells = <0>; | |
| 836 | compatible = "ti,gate-clock"; | |
| 837 | clocks = <&sys_32k_ck>; | |
| 838 | ti,bit-shift = <8>; | |
| 839 | reg = <0x1070>; | |
| 840 | }; | |
| 841 | ||
| 842 | gpio5_dbclk: gpio5_dbclk { | |
| 843 | #clock-cells = <0>; | |
| 844 | compatible = "ti,gate-clock"; | |
| 845 | clocks = <&sys_32k_ck>; | |
| 846 | ti,bit-shift = <8>; | |
| 847 | reg = <0x1078>; | |
| 848 | }; | |
| 849 | ||
| 850 | gpio6_dbclk: gpio6_dbclk { | |
| 851 | #clock-cells = <0>; | |
| 852 | compatible = "ti,gate-clock"; | |
| 853 | clocks = <&sys_32k_ck>; | |
| 854 | ti,bit-shift = <8>; | |
| 855 | reg = <0x1080>; | |
| 856 | }; | |
| 857 | ||
| 858 | gpio7_dbclk: gpio7_dbclk { | |
| 859 | #clock-cells = <0>; | |
| 860 | compatible = "ti,gate-clock"; | |
| 861 | clocks = <&sys_32k_ck>; | |
| 862 | ti,bit-shift = <8>; | |
| 863 | reg = <0x1110>; | |
| 864 | }; | |
| 865 | ||
| 866 | gpio8_dbclk: gpio8_dbclk { | |
| 867 | #clock-cells = <0>; | |
| 868 | compatible = "ti,gate-clock"; | |
| 869 | clocks = <&sys_32k_ck>; | |
| 870 | ti,bit-shift = <8>; | |
| 871 | reg = <0x1118>; | |
| 872 | }; | |
| 873 | ||
| 874 | iss_ctrlclk: iss_ctrlclk { | |
| 875 | #clock-cells = <0>; | |
| 876 | compatible = "ti,gate-clock"; | |
| 877 | clocks = <&func_96m_fclk>; | |
| 878 | ti,bit-shift = <8>; | |
| 879 | reg = <0x1320>; | |
| 880 | }; | |
| 881 | ||
| 882 | lli_txphy_clk: lli_txphy_clk { | |
| 883 | #clock-cells = <0>; | |
| 884 | compatible = "ti,gate-clock"; | |
| 885 | clocks = <&dpll_unipro1_clkdcoldo>; | |
| 886 | ti,bit-shift = <8>; | |
| 887 | reg = <0x0f20>; | |
| 888 | }; | |
| 889 | ||
| 890 | lli_txphy_ls_clk: lli_txphy_ls_clk { | |
| 891 | #clock-cells = <0>; | |
| 892 | compatible = "ti,gate-clock"; | |
| 893 | clocks = <&dpll_unipro1_m2_ck>; | |
| 894 | ti,bit-shift = <9>; | |
| 895 | reg = <0x0f20>; | |
| 896 | }; | |
| 897 | ||
| 898 | mmc1_32khz_clk: mmc1_32khz_clk { | |
| 899 | #clock-cells = <0>; | |
| 900 | compatible = "ti,gate-clock"; | |
| 901 | clocks = <&sys_32k_ck>; | |
| 902 | ti,bit-shift = <8>; | |
| 903 | reg = <0x1628>; | |
| 904 | }; | |
| 905 | ||
| 906 | sata_ref_clk: sata_ref_clk { | |
| 907 | #clock-cells = <0>; | |
| 908 | compatible = "ti,gate-clock"; | |
| 909 | clocks = <&sys_clkin>; | |
| 910 | ti,bit-shift = <8>; | |
| 911 | reg = <0x1688>; | |
| 912 | }; | |
| 913 | ||
| 914 | usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { | |
| 915 | #clock-cells = <0>; | |
| 916 | compatible = "ti,gate-clock"; | |
| 917 | clocks = <&dpll_usb_m2_ck>; | |
| 918 | ti,bit-shift = <13>; | |
| 919 | reg = <0x1658>; | |
| 920 | }; | |
| 921 | ||
| 922 | usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { | |
| 923 | #clock-cells = <0>; | |
| 924 | compatible = "ti,gate-clock"; | |
| 925 | clocks = <&dpll_usb_m2_ck>; | |
| 926 | ti,bit-shift = <14>; | |
| 927 | reg = <0x1658>; | |
| 928 | }; | |
| 929 | ||
| 930 | usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { | |
| 931 | #clock-cells = <0>; | |
| 932 | compatible = "ti,gate-clock"; | |
| 933 | clocks = <&dpll_usb_m2_ck>; | |
| 934 | ti,bit-shift = <7>; | |
| 935 | reg = <0x1658>; | |
| 936 | }; | |
| 937 | ||
| 938 | usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { | |
| 939 | #clock-cells = <0>; | |
| 940 | compatible = "ti,gate-clock"; | |
| 941 | clocks = <&l3init_60m_fclk>; | |
| 942 | ti,bit-shift = <11>; | |
| 943 | reg = <0x1658>; | |
| 944 | }; | |
| 945 | ||
| 946 | usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { | |
| 947 | #clock-cells = <0>; | |
| 948 | compatible = "ti,gate-clock"; | |
| 949 | clocks = <&l3init_60m_fclk>; | |
| 950 | ti,bit-shift = <12>; | |
| 951 | reg = <0x1658>; | |
| 952 | }; | |
| 953 | ||
| 954 | usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { | |
| 955 | #clock-cells = <0>; | |
| 956 | compatible = "ti,gate-clock"; | |
| 957 | clocks = <&l3init_60m_fclk>; | |
| 958 | ti,bit-shift = <6>; | |
| 959 | reg = <0x1658>; | |
| 960 | }; | |
| 961 | ||
| 962 | utmi_p1_gfclk: utmi_p1_gfclk { | |
| 963 | #clock-cells = <0>; | |
| 964 | compatible = "ti,mux-clock"; | |
| 965 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; | |
| 966 | ti,bit-shift = <24>; | |
| 967 | reg = <0x1658>; | |
| 968 | }; | |
| 969 | ||
| 970 | usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { | |
| 971 | #clock-cells = <0>; | |
| 972 | compatible = "ti,gate-clock"; | |
| 973 | clocks = <&utmi_p1_gfclk>; | |
| 974 | ti,bit-shift = <8>; | |
| 975 | reg = <0x1658>; | |
| 976 | }; | |
| 977 | ||
| 978 | utmi_p2_gfclk: utmi_p2_gfclk { | |
| 979 | #clock-cells = <0>; | |
| 980 | compatible = "ti,mux-clock"; | |
| 981 | clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; | |
| 982 | ti,bit-shift = <25>; | |
| 983 | reg = <0x1658>; | |
| 984 | }; | |
| 985 | ||
| 986 | usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { | |
| 987 | #clock-cells = <0>; | |
| 988 | compatible = "ti,gate-clock"; | |
| 989 | clocks = <&utmi_p2_gfclk>; | |
| 990 | ti,bit-shift = <9>; | |
| 991 | reg = <0x1658>; | |
| 992 | }; | |
| 993 | ||
| 994 | usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { | |
| 995 | #clock-cells = <0>; | |
| 996 | compatible = "ti,gate-clock"; | |
| 997 | clocks = <&l3init_60m_fclk>; | |
| 998 | ti,bit-shift = <10>; | |
| 999 | reg = <0x1658>; | |
| 1000 | }; | |
| 1001 | ||
| 1002 | usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { | |
| 1003 | #clock-cells = <0>; | |
| 1004 | compatible = "ti,gate-clock"; | |
| 1005 | clocks = <&dpll_usb_clkdcoldo>; | |
| 1006 | ti,bit-shift = <8>; | |
| 1007 | reg = <0x16f0>; | |
| 1008 | }; | |
| 1009 | ||
| 1010 | usb_phy_cm_clk32k: usb_phy_cm_clk32k { | |
| 1011 | #clock-cells = <0>; | |
| 1012 | compatible = "ti,gate-clock"; | |
| 1013 | clocks = <&sys_32k_ck>; | |
| 1014 | ti,bit-shift = <8>; | |
| 1015 | reg = <0x0640>; | |
| 1016 | }; | |
| 1017 | ||
| 1018 | usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { | |
| 1019 | #clock-cells = <0>; | |
| 1020 | compatible = "ti,gate-clock"; | |
| 1021 | clocks = <&l3init_60m_fclk>; | |
| 1022 | ti,bit-shift = <8>; | |
| 1023 | reg = <0x1668>; | |
| 1024 | }; | |
| 1025 | ||
| 1026 | usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { | |
| 1027 | #clock-cells = <0>; | |
| 1028 | compatible = "ti,gate-clock"; | |
| 1029 | clocks = <&l3init_60m_fclk>; | |
| 1030 | ti,bit-shift = <9>; | |
| 1031 | reg = <0x1668>; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { | |
| 1035 | #clock-cells = <0>; | |
| 1036 | compatible = "ti,gate-clock"; | |
| 1037 | clocks = <&l3init_60m_fclk>; | |
| 1038 | ti,bit-shift = <10>; | |
| 1039 | reg = <0x1668>; | |
| 1040 | }; | |
| 1041 | ||
| 1042 | fdif_fclk: fdif_fclk { | |
| 1043 | #clock-cells = <0>; | |
| 1044 | compatible = "ti,divider-clock"; | |
| 1045 | clocks = <&dpll_per_h11x2_ck>; | |
| 1046 | ti,bit-shift = <24>; | |
| 1047 | ti,max-div = <2>; | |
| 1048 | reg = <0x1328>; | |
| 1049 | }; | |
| 1050 | ||
| 1051 | gpu_core_gclk_mux: gpu_core_gclk_mux { | |
| 1052 | #clock-cells = <0>; | |
| 1053 | compatible = "ti,mux-clock"; | |
| 1054 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
| 1055 | ti,bit-shift = <24>; | |
| 1056 | reg = <0x1520>; | |
| 1057 | }; | |
| 1058 | ||
| 1059 | gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { | |
| 1060 | #clock-cells = <0>; | |
| 1061 | compatible = "ti,mux-clock"; | |
| 1062 | clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; | |
| 1063 | ti,bit-shift = <25>; | |
| 1064 | reg = <0x1520>; | |
| 1065 | }; | |
| 1066 | ||
| 1067 | hsi_fclk: hsi_fclk { | |
| 1068 | #clock-cells = <0>; | |
| 1069 | compatible = "ti,divider-clock"; | |
| 1070 | clocks = <&dpll_per_m2x2_ck>; | |
| 1071 | ti,bit-shift = <24>; | |
| 1072 | ti,max-div = <2>; | |
| 1073 | reg = <0x1638>; | |
| 1074 | }; | |
| 1075 | ||
| 1076 | mmc1_fclk_mux: mmc1_fclk_mux { | |
| 1077 | #clock-cells = <0>; | |
| 1078 | compatible = "ti,mux-clock"; | |
| 1079 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1080 | ti,bit-shift = <24>; | |
| 1081 | reg = <0x1628>; | |
| 1082 | }; | |
| 1083 | ||
| 1084 | mmc1_fclk: mmc1_fclk { | |
| 1085 | #clock-cells = <0>; | |
| 1086 | compatible = "ti,divider-clock"; | |
| 1087 | clocks = <&mmc1_fclk_mux>; | |
| 1088 | ti,bit-shift = <25>; | |
| 1089 | ti,max-div = <2>; | |
| 1090 | reg = <0x1628>; | |
| 1091 | }; | |
| 1092 | ||
| 1093 | mmc2_fclk_mux: mmc2_fclk_mux { | |
| 1094 | #clock-cells = <0>; | |
| 1095 | compatible = "ti,mux-clock"; | |
| 1096 | clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; | |
| 1097 | ti,bit-shift = <24>; | |
| 1098 | reg = <0x1630>; | |
| 1099 | }; | |
| 1100 | ||
| 1101 | mmc2_fclk: mmc2_fclk { | |
| 1102 | #clock-cells = <0>; | |
| 1103 | compatible = "ti,divider-clock"; | |
| 1104 | clocks = <&mmc2_fclk_mux>; | |
| 1105 | ti,bit-shift = <25>; | |
| 1106 | ti,max-div = <2>; | |
| 1107 | reg = <0x1630>; | |
| 1108 | }; | |
| 1109 | ||
| 1110 | timer10_gfclk_mux: timer10_gfclk_mux { | |
| 1111 | #clock-cells = <0>; | |
| 1112 | compatible = "ti,mux-clock"; | |
| 1113 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1114 | ti,bit-shift = <24>; | |
| 1115 | reg = <0x1028>; | |
| 1116 | }; | |
| 1117 | ||
| 1118 | timer11_gfclk_mux: timer11_gfclk_mux { | |
| 1119 | #clock-cells = <0>; | |
| 1120 | compatible = "ti,mux-clock"; | |
| 1121 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1122 | ti,bit-shift = <24>; | |
| 1123 | reg = <0x1030>; | |
| 1124 | }; | |
| 1125 | ||
| 1126 | timer2_gfclk_mux: timer2_gfclk_mux { | |
| 1127 | #clock-cells = <0>; | |
| 1128 | compatible = "ti,mux-clock"; | |
| 1129 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1130 | ti,bit-shift = <24>; | |
| 1131 | reg = <0x1038>; | |
| 1132 | }; | |
| 1133 | ||
| 1134 | timer3_gfclk_mux: timer3_gfclk_mux { | |
| 1135 | #clock-cells = <0>; | |
| 1136 | compatible = "ti,mux-clock"; | |
| 1137 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1138 | ti,bit-shift = <24>; | |
| 1139 | reg = <0x1040>; | |
| 1140 | }; | |
| 1141 | ||
| 1142 | timer4_gfclk_mux: timer4_gfclk_mux { | |
| 1143 | #clock-cells = <0>; | |
| 1144 | compatible = "ti,mux-clock"; | |
| 1145 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1146 | ti,bit-shift = <24>; | |
| 1147 | reg = <0x1048>; | |
| 1148 | }; | |
| 1149 | ||
| 1150 | timer9_gfclk_mux: timer9_gfclk_mux { | |
| 1151 | #clock-cells = <0>; | |
| 1152 | compatible = "ti,mux-clock"; | |
| 1153 | clocks = <&sys_clkin>, <&sys_32k_ck>; | |
| 1154 | ti,bit-shift = <24>; | |
| 1155 | reg = <0x1050>; | |
| 1156 | }; | |
| 1157 | }; | |
| 1158 | ||
| 1159 | &cm_core_clockdomains { | |
| 1160 | l3init_clkdm: l3init_clkdm { | |
| 1161 | compatible = "ti,clockdomain"; | |
| 1162 | clocks = <&dpll_usb_ck>; | |
| 1163 | }; | |
| 1164 | }; | |
| 1165 | ||
| 1166 | &scrm_clocks { | |
| 1167 | auxclk0_src_gate_ck: auxclk0_src_gate_ck { | |
| 1168 | #clock-cells = <0>; | |
| 1169 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1170 | clocks = <&dpll_core_m3x2_ck>; | |
| 1171 | ti,bit-shift = <8>; | |
| 1172 | reg = <0x0310>; | |
| 1173 | }; | |
| 1174 | ||
| 1175 | auxclk0_src_mux_ck: auxclk0_src_mux_ck { | |
| 1176 | #clock-cells = <0>; | |
| 1177 | compatible = "ti,composite-mux-clock"; | |
| 1178 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1179 | ti,bit-shift = <1>; | |
| 1180 | reg = <0x0310>; | |
| 1181 | }; | |
| 1182 | ||
| 1183 | auxclk0_src_ck: auxclk0_src_ck { | |
| 1184 | #clock-cells = <0>; | |
| 1185 | compatible = "ti,composite-clock"; | |
| 1186 | clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; | |
| 1187 | }; | |
| 1188 | ||
| 1189 | auxclk0_ck: auxclk0_ck { | |
| 1190 | #clock-cells = <0>; | |
| 1191 | compatible = "ti,divider-clock"; | |
| 1192 | clocks = <&auxclk0_src_ck>; | |
| 1193 | ti,bit-shift = <16>; | |
| 1194 | ti,max-div = <16>; | |
| 1195 | reg = <0x0310>; | |
| 1196 | }; | |
| 1197 | ||
| 1198 | auxclk1_src_gate_ck: auxclk1_src_gate_ck { | |
| 1199 | #clock-cells = <0>; | |
| 1200 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1201 | clocks = <&dpll_core_m3x2_ck>; | |
| 1202 | ti,bit-shift = <8>; | |
| 1203 | reg = <0x0314>; | |
| 1204 | }; | |
| 1205 | ||
| 1206 | auxclk1_src_mux_ck: auxclk1_src_mux_ck { | |
| 1207 | #clock-cells = <0>; | |
| 1208 | compatible = "ti,composite-mux-clock"; | |
| 1209 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1210 | ti,bit-shift = <1>; | |
| 1211 | reg = <0x0314>; | |
| 1212 | }; | |
| 1213 | ||
| 1214 | auxclk1_src_ck: auxclk1_src_ck { | |
| 1215 | #clock-cells = <0>; | |
| 1216 | compatible = "ti,composite-clock"; | |
| 1217 | clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; | |
| 1218 | }; | |
| 1219 | ||
| 1220 | auxclk1_ck: auxclk1_ck { | |
| 1221 | #clock-cells = <0>; | |
| 1222 | compatible = "ti,divider-clock"; | |
| 1223 | clocks = <&auxclk1_src_ck>; | |
| 1224 | ti,bit-shift = <16>; | |
| 1225 | ti,max-div = <16>; | |
| 1226 | reg = <0x0314>; | |
| 1227 | }; | |
| 1228 | ||
| 1229 | auxclk2_src_gate_ck: auxclk2_src_gate_ck { | |
| 1230 | #clock-cells = <0>; | |
| 1231 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1232 | clocks = <&dpll_core_m3x2_ck>; | |
| 1233 | ti,bit-shift = <8>; | |
| 1234 | reg = <0x0318>; | |
| 1235 | }; | |
| 1236 | ||
| 1237 | auxclk2_src_mux_ck: auxclk2_src_mux_ck { | |
| 1238 | #clock-cells = <0>; | |
| 1239 | compatible = "ti,composite-mux-clock"; | |
| 1240 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1241 | ti,bit-shift = <1>; | |
| 1242 | reg = <0x0318>; | |
| 1243 | }; | |
| 1244 | ||
| 1245 | auxclk2_src_ck: auxclk2_src_ck { | |
| 1246 | #clock-cells = <0>; | |
| 1247 | compatible = "ti,composite-clock"; | |
| 1248 | clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; | |
| 1249 | }; | |
| 1250 | ||
| 1251 | auxclk2_ck: auxclk2_ck { | |
| 1252 | #clock-cells = <0>; | |
| 1253 | compatible = "ti,divider-clock"; | |
| 1254 | clocks = <&auxclk2_src_ck>; | |
| 1255 | ti,bit-shift = <16>; | |
| 1256 | ti,max-div = <16>; | |
| 1257 | reg = <0x0318>; | |
| 1258 | }; | |
| 1259 | ||
| 1260 | auxclk3_src_gate_ck: auxclk3_src_gate_ck { | |
| 1261 | #clock-cells = <0>; | |
| 1262 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1263 | clocks = <&dpll_core_m3x2_ck>; | |
| 1264 | ti,bit-shift = <8>; | |
| 1265 | reg = <0x031c>; | |
| 1266 | }; | |
| 1267 | ||
| 1268 | auxclk3_src_mux_ck: auxclk3_src_mux_ck { | |
| 1269 | #clock-cells = <0>; | |
| 1270 | compatible = "ti,composite-mux-clock"; | |
| 1271 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1272 | ti,bit-shift = <1>; | |
| 1273 | reg = <0x031c>; | |
| 1274 | }; | |
| 1275 | ||
| 1276 | auxclk3_src_ck: auxclk3_src_ck { | |
| 1277 | #clock-cells = <0>; | |
| 1278 | compatible = "ti,composite-clock"; | |
| 1279 | clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; | |
| 1280 | }; | |
| 1281 | ||
| 1282 | auxclk3_ck: auxclk3_ck { | |
| 1283 | #clock-cells = <0>; | |
| 1284 | compatible = "ti,divider-clock"; | |
| 1285 | clocks = <&auxclk3_src_ck>; | |
| 1286 | ti,bit-shift = <16>; | |
| 1287 | ti,max-div = <16>; | |
| 1288 | reg = <0x031c>; | |
| 1289 | }; | |
| 1290 | ||
| 1291 | auxclk4_src_gate_ck: auxclk4_src_gate_ck { | |
| 1292 | #clock-cells = <0>; | |
| 1293 | compatible = "ti,composite-no-wait-gate-clock"; | |
| 1294 | clocks = <&dpll_core_m3x2_ck>; | |
| 1295 | ti,bit-shift = <8>; | |
| 1296 | reg = <0x0320>; | |
| 1297 | }; | |
| 1298 | ||
| 1299 | auxclk4_src_mux_ck: auxclk4_src_mux_ck { | |
| 1300 | #clock-cells = <0>; | |
| 1301 | compatible = "ti,composite-mux-clock"; | |
| 1302 | clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; | |
| 1303 | ti,bit-shift = <1>; | |
| 1304 | reg = <0x0320>; | |
| 1305 | }; | |
| 1306 | ||
| 1307 | auxclk4_src_ck: auxclk4_src_ck { | |
| 1308 | #clock-cells = <0>; | |
| 1309 | compatible = "ti,composite-clock"; | |
| 1310 | clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; | |
| 1311 | }; | |
| 1312 | ||
| 1313 | auxclk4_ck: auxclk4_ck { | |
| 1314 | #clock-cells = <0>; | |
| 1315 | compatible = "ti,divider-clock"; | |
| 1316 | clocks = <&auxclk4_src_ck>; | |
| 1317 | ti,bit-shift = <16>; | |
| 1318 | ti,max-div = <16>; | |
| 1319 | reg = <0x0320>; | |
| 1320 | }; | |
| 1321 | ||
| 1322 | auxclkreq0_ck: auxclkreq0_ck { | |
| 1323 | #clock-cells = <0>; | |
| 1324 | compatible = "ti,mux-clock"; | |
| 1325 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1326 | ti,bit-shift = <2>; | |
| 1327 | reg = <0x0210>; | |
| 1328 | }; | |
| 1329 | ||
| 1330 | auxclkreq1_ck: auxclkreq1_ck { | |
| 1331 | #clock-cells = <0>; | |
| 1332 | compatible = "ti,mux-clock"; | |
| 1333 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1334 | ti,bit-shift = <2>; | |
| 1335 | reg = <0x0214>; | |
| 1336 | }; | |
| 1337 | ||
| 1338 | auxclkreq2_ck: auxclkreq2_ck { | |
| 1339 | #clock-cells = <0>; | |
| 1340 | compatible = "ti,mux-clock"; | |
| 1341 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1342 | ti,bit-shift = <2>; | |
| 1343 | reg = <0x0218>; | |
| 1344 | }; | |
| 1345 | ||
| 1346 | auxclkreq3_ck: auxclkreq3_ck { | |
| 1347 | #clock-cells = <0>; | |
| 1348 | compatible = "ti,mux-clock"; | |
| 1349 | clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; | |
| 1350 | ti,bit-shift = <2>; | |
| 1351 | reg = <0x021c>; | |
| 1352 | }; | |
| 1353 | }; |