ARM: orion5x: enable pinctrl driver at SoC level
[deliverable/linux.git] / arch / arm / boot / dts / orion5x.dtsi
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1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
48be9707 9#include "skeleton.dtsi"
1bffb4a8 10
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11#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
12
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13/ {
14 model = "Marvell Orion5x SoC";
15 compatible = "marvell,orion5x";
16 interrupt-parent = <&intc>;
17
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18 aliases {
19 gpio0 = &gpio0;
20 };
cabbd6bd 21
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22 soc {
23 #address-cells = <2>;
1bffb4a8 24 #size-cells = <1>;
5c697664 25 controller = <&mbusc>;
1bffb4a8 26
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27 internal-regs {
28 compatible = "simple-bus";
6226cf18 29 #address-cells = <1>;
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30 #size-cells = <1>;
31 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
32
33 gpio0: gpio@10100 {
34 compatible = "marvell,orion-gpio";
35 #gpio-cells = <2>;
36 gpio-controller;
37 reg = <0x10100 0x40>;
38 ngpios = <32>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
41 interrupts = <6>, <7>, <8>, <9>;
42 };
6226cf18 43
2958316d 44 spi: spi@10600 {
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45 compatible = "marvell,orion-spi";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cell-index = <0>;
49 reg = <0x10600 0x28>;
50 status = "disabled";
51 };
1bffb4a8 52
2958316d 53 i2c: i2c@11000 {
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54 compatible = "marvell,mv64xxx-i2c";
55 reg = <0x11000 0x20>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 interrupts = <5>;
59 clock-frequency = <100000>;
60 status = "disabled";
61 };
1bffb4a8 62
2958316d 63 uart0: serial@12000 {
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64 compatible = "ns16550a";
65 reg = <0x12000 0x100>;
66 reg-shift = <2>;
67 interrupts = <3>;
0180ed45 68 clocks = <&core_clk 0>;
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69 status = "disabled";
70 };
0fb28811 71
2958316d 72 uart1: serial@12100 {
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73 compatible = "ns16550a";
74 reg = <0x12100 0x100>;
75 reg-shift = <2>;
76 interrupts = <4>;
0180ed45 77 clocks = <&core_clk 0>;
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78 status = "disabled";
79 };
1bffb4a8 80
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81 bridge_intc: bridge-interrupt-ctrl@20110 {
82 compatible = "marvell,orion-bridge-intc";
83 interrupt-controller;
84 #interrupt-cells = <1>;
85 reg = <0x20110 0x8>;
86 interrupts = <0>;
87 marvell,#interrupts = <4>;
88 };
89
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90 intc: interrupt-controller@20200 {
91 compatible = "marvell,orion-intc";
92 interrupt-controller;
93 #interrupt-cells = <1>;
94 reg = <0x20200 0x08>;
95 };
48e86997 96
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97 timer: timer@20300 {
98 compatible = "marvell,orion-timer";
99 reg = <0x20300 0x20>;
100 interrupt-parent = <&bridge_intc>;
101 interrupts = <1>, <2>;
102 clocks = <&core_clk 0>;
103 };
104
2958316d 105 wdt: wdt@20300 {
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106 compatible = "marvell,orion-wdt";
107 reg = <0x20300 0x28>;
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108 interrupt-parent = <&bridge_intc>;
109 interrupts = <3>;
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110 status = "okay";
111 };
4504607f 112
2958316d 113 ehci0: ehci@50000 {
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114 compatible = "marvell,orion-ehci";
115 reg = <0x50000 0x1000>;
116 interrupts = <17>;
117 status = "disabled";
4504607f 118 };
5c697664 119
984d37c4 120 xor: dma-controller@60900 {
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121 compatible = "marvell,orion-xor";
122 reg = <0x60900 0x100
123 0x60b00 0x100>;
124 status = "okay";
125
126 xor00 {
127 interrupts = <30>;
128 dmacap,memcpy;
129 dmacap,xor;
130 };
131 xor01 {
132 interrupts = <31>;
133 dmacap,memcpy;
134 dmacap,xor;
135 dmacap,memset;
136 };
4504607f 137 };
4504607f 138
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139 eth: ethernet-controller@72000 {
140 compatible = "marvell,orion-eth";
141 #address-cells = <1>;
142 #size-cells = <0>;
143 reg = <0x72000 0x4000>;
144 marvell,tx-checksum-limit = <1600>;
145 status = "disabled";
146
2958316d 147 ethport: ethernet-port@0 {
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148 compatible = "marvell,orion-eth-port";
149 reg = <0>;
2864ed64 150 interrupts = <21>;
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151 /* overwrite MAC address in bootloader */
152 local-mac-address = [00 00 00 00 00 00];
153 /* set phy-handle property in board file */
154 };
99d6455b 155 };
6226cf18 156
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157 mdio: mdio-bus@72004 {
158 compatible = "marvell,orion-mdio";
159 #address-cells = <1>;
160 #size-cells = <0>;
161 reg = <0x72004 0x84>;
162 interrupts = <22>;
163 status = "disabled";
6226cf18 164
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165 /* add phy nodes in board file */
166 };
167
2958316d 168 sata: sata@80000 {
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169 compatible = "marvell,orion-sata";
170 reg = <0x80000 0x5000>;
171 interrupts = <29>;
172 status = "disabled";
173 };
6226cf18 174
2958316d 175 ehci1: ehci@a0000 {
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176 compatible = "marvell,orion-ehci";
177 reg = <0xa0000 0x1000>;
178 interrupts = <12>;
179 status = "disabled";
180 };
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181 };
182
2958316d 183 cesa: crypto@90000 {
6226cf18 184 compatible = "marvell,orion-crypto";
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185 reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
186 <MBUS_ID(0x09, 0x00) 0x0 0x800>;
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187 reg-names = "regs", "sram";
188 interrupts = <28>;
189 status = "okay";
190 };
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191 };
192};
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