Commit | Line | Data |
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434e1c57 BS |
1 | /* |
2 | * DTS file for CSR SiRFprimaII SoC | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
02c981c0 | 10 | / { |
434e1c57 | 11 | compatible = "sirf,prima2"; |
02c981c0 BD |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
02c981c0 BD |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
cc73f875 LP |
21 | compatible = "arm,cortex-a9"; |
22 | device_type = "cpu"; | |
02c981c0 BD |
23 | reg = <0x0>; |
24 | d-cache-line-size = <32>; | |
25 | i-cache-line-size = <32>; | |
26 | d-cache-size = <32768>; | |
27 | i-cache-size = <32768>; | |
28 | /* from bootloader */ | |
29 | timebase-frequency = <0>; | |
30 | bus-frequency = <0>; | |
31 | clock-frequency = <0>; | |
683659f3 RY |
32 | clocks = <&clks 12>; |
33 | operating-points = < | |
34 | /* kHz uV */ | |
35 | 200000 1025000 | |
36 | 400000 1025000 | |
37 | 664000 1050000 | |
38 | 800000 1100000 | |
39 | >; | |
40 | clock-latency = <150000>; | |
02c981c0 BD |
41 | }; |
42 | }; | |
43 | ||
44 | axi { | |
45 | compatible = "simple-bus"; | |
46 | #address-cells = <1>; | |
47 | #size-cells = <1>; | |
48 | ranges = <0x40000000 0x40000000 0x80000000>; | |
49 | ||
50 | l2-cache-controller@80040000 { | |
918197be | 51 | compatible = "arm,pl310-cache"; |
02c981c0 BD |
52 | reg = <0x80040000 0x1000>; |
53 | interrupts = <59>; | |
917d8535 BS |
54 | arm,tag-latency = <1 1 1>; |
55 | arm,data-latency = <1 1 1>; | |
56 | arm,filter-ranges = <0 0x40000000>; | |
02c981c0 BD |
57 | }; |
58 | ||
59 | intc: interrupt-controller@80020000 { | |
60 | #interrupt-cells = <1>; | |
61 | interrupt-controller; | |
62 | compatible = "sirf,prima2-intc"; | |
63 | reg = <0x80020000 0x1000>; | |
64 | }; | |
65 | ||
66 | sys-iobg { | |
67 | compatible = "simple-bus"; | |
68 | #address-cells = <1>; | |
69 | #size-cells = <1>; | |
70 | ranges = <0x88000000 0x88000000 0x40000>; | |
71 | ||
eb8b8f2e | 72 | clks: clock-controller@88000000 { |
02c981c0 BD |
73 | compatible = "sirf,prima2-clkc"; |
74 | reg = <0x88000000 0x1000>; | |
75 | interrupts = <3>; | |
eb8b8f2e | 76 | #clock-cells = <1>; |
02c981c0 BD |
77 | }; |
78 | ||
e7eda91f | 79 | rstc: reset-controller@88010000 { |
02c981c0 BD |
80 | compatible = "sirf,prima2-rstc"; |
81 | reg = <0x88010000 0x1000>; | |
e7eda91f | 82 | #reset-cells = <1>; |
02c981c0 | 83 | }; |
073adf4f BS |
84 | |
85 | rsc-controller@88020000 { | |
86 | compatible = "sirf,prima2-rsc"; | |
87 | reg = <0x88020000 0x1000>; | |
88 | }; | |
0671840c BS |
89 | |
90 | cphifbg@88030000 { | |
91 | compatible = "sirf,prima2-cphifbg"; | |
92 | reg = <0x88030000 0x1000>; | |
794f8b21 | 93 | clocks = <&clks 42>; |
0671840c | 94 | }; |
02c981c0 BD |
95 | }; |
96 | ||
97 | mem-iobg { | |
98 | compatible = "simple-bus"; | |
99 | #address-cells = <1>; | |
100 | #size-cells = <1>; | |
101 | ranges = <0x90000000 0x90000000 0x10000>; | |
102 | ||
103 | memory-controller@90000000 { | |
104 | compatible = "sirf,prima2-memc"; | |
5fadea22 | 105 | reg = <0x90000000 0x2000>; |
02c981c0 | 106 | interrupts = <27>; |
eb8b8f2e | 107 | clocks = <&clks 5>; |
02c981c0 | 108 | }; |
5fadea22 YH |
109 | |
110 | memc-monitor { | |
111 | compatible = "sirf,prima2-memcmon"; | |
112 | reg = <0x90002000 0x200>; | |
113 | interrupts = <4>; | |
114 | clocks = <&clks 32>; | |
115 | }; | |
02c981c0 BD |
116 | }; |
117 | ||
118 | disp-iobg { | |
119 | compatible = "simple-bus"; | |
120 | #address-cells = <1>; | |
121 | #size-cells = <1>; | |
122 | ranges = <0x90010000 0x90010000 0x30000>; | |
123 | ||
124 | display@90010000 { | |
125 | compatible = "sirf,prima2-lcd"; | |
126 | reg = <0x90010000 0x20000>; | |
127 | interrupts = <30>; | |
128 | }; | |
129 | ||
130 | vpp@90020000 { | |
131 | compatible = "sirf,prima2-vpp"; | |
132 | reg = <0x90020000 0x10000>; | |
133 | interrupts = <31>; | |
eb8b8f2e | 134 | clocks = <&clks 35>; |
02c981c0 BD |
135 | }; |
136 | }; | |
137 | ||
138 | graphics-iobg { | |
139 | compatible = "simple-bus"; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <1>; | |
142 | ranges = <0x98000000 0x98000000 0x8000000>; | |
143 | ||
144 | graphics@98000000 { | |
145 | compatible = "powervr,sgx531"; | |
146 | reg = <0x98000000 0x8000000>; | |
147 | interrupts = <6>; | |
eb8b8f2e | 148 | clocks = <&clks 32>; |
02c981c0 BD |
149 | }; |
150 | }; | |
151 | ||
152 | multimedia-iobg { | |
153 | compatible = "simple-bus"; | |
154 | #address-cells = <1>; | |
155 | #size-cells = <1>; | |
156 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
157 | ||
158 | multimedia@a0000000 { | |
159 | compatible = "sirf,prima2-video-codec"; | |
160 | reg = <0xa0000000 0x8000000>; | |
161 | interrupts = <5>; | |
eb8b8f2e | 162 | clocks = <&clks 33>; |
02c981c0 BD |
163 | }; |
164 | }; | |
165 | ||
166 | dsp-iobg { | |
167 | compatible = "simple-bus"; | |
168 | #address-cells = <1>; | |
169 | #size-cells = <1>; | |
170 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
171 | ||
172 | dspif@a8000000 { | |
173 | compatible = "sirf,prima2-dspif"; | |
174 | reg = <0xa8000000 0x10000>; | |
175 | interrupts = <9>; | |
176 | }; | |
177 | ||
178 | gps@a8010000 { | |
179 | compatible = "sirf,prima2-gps"; | |
180 | reg = <0xa8010000 0x10000>; | |
181 | interrupts = <7>; | |
eb8b8f2e | 182 | clocks = <&clks 9>; |
02c981c0 BD |
183 | }; |
184 | ||
185 | dsp@a9000000 { | |
186 | compatible = "sirf,prima2-dsp"; | |
187 | reg = <0xa9000000 0x1000000>; | |
188 | interrupts = <8>; | |
eb8b8f2e | 189 | clocks = <&clks 8>; |
02c981c0 BD |
190 | }; |
191 | }; | |
192 | ||
193 | peri-iobg { | |
194 | compatible = "simple-bus"; | |
195 | #address-cells = <1>; | |
196 | #size-cells = <1>; | |
9e85b9d1 BS |
197 | ranges = <0xb0000000 0xb0000000 0x180000>, |
198 | <0x56000000 0x56000000 0x1b00000>; | |
02c981c0 BD |
199 | |
200 | timer@b0020000 { | |
201 | compatible = "sirf,prima2-tick"; | |
202 | reg = <0xb0020000 0x1000>; | |
203 | interrupts = <0>; | |
c7cff54d | 204 | clocks = <&clks 11>; |
02c981c0 BD |
205 | }; |
206 | ||
207 | nand@b0030000 { | |
208 | compatible = "sirf,prima2-nand"; | |
209 | reg = <0xb0030000 0x10000>; | |
210 | interrupts = <41>; | |
eb8b8f2e | 211 | clocks = <&clks 26>; |
02c981c0 BD |
212 | }; |
213 | ||
214 | audio@b0040000 { | |
215 | compatible = "sirf,prima2-audio"; | |
216 | reg = <0xb0040000 0x10000>; | |
217 | interrupts = <35>; | |
eb8b8f2e | 218 | clocks = <&clks 27>; |
02c981c0 BD |
219 | }; |
220 | ||
221 | uart0: uart@b0050000 { | |
222 | cell-index = <0>; | |
223 | compatible = "sirf,prima2-uart"; | |
a1369978 | 224 | reg = <0xb0050000 0x1000>; |
02c981c0 | 225 | interrupts = <17>; |
a1369978 | 226 | fifosize = <128>; |
eb8b8f2e | 227 | clocks = <&clks 13>; |
9be16b38 QL |
228 | dmas = <&dmac1 5>, <&dmac0 2>; |
229 | dma-names = "rx", "tx"; | |
02c981c0 BD |
230 | }; |
231 | ||
232 | uart1: uart@b0060000 { | |
233 | cell-index = <1>; | |
234 | compatible = "sirf,prima2-uart"; | |
a1369978 | 235 | reg = <0xb0060000 0x1000>; |
02c981c0 | 236 | interrupts = <18>; |
a1369978 | 237 | fifosize = <32>; |
eb8b8f2e | 238 | clocks = <&clks 14>; |
02c981c0 BD |
239 | }; |
240 | ||
241 | uart2: uart@b0070000 { | |
242 | cell-index = <2>; | |
243 | compatible = "sirf,prima2-uart"; | |
a1369978 | 244 | reg = <0xb0070000 0x1000>; |
02c981c0 | 245 | interrupts = <19>; |
a1369978 | 246 | fifosize = <128>; |
eb8b8f2e | 247 | clocks = <&clks 15>; |
9be16b38 QL |
248 | dmas = <&dmac0 6>, <&dmac0 7>; |
249 | dma-names = "rx", "tx"; | |
02c981c0 BD |
250 | }; |
251 | ||
252 | usp0: usp@b0080000 { | |
253 | cell-index = <0>; | |
254 | compatible = "sirf,prima2-usp"; | |
255 | reg = <0xb0080000 0x10000>; | |
256 | interrupts = <20>; | |
a1369978 | 257 | fifosize = <128>; |
eb8b8f2e | 258 | clocks = <&clks 28>; |
9be16b38 QL |
259 | dmas = <&dmac1 1>, <&dmac1 2>; |
260 | dma-names = "rx", "tx"; | |
02c981c0 BD |
261 | }; |
262 | ||
263 | usp1: usp@b0090000 { | |
264 | cell-index = <1>; | |
265 | compatible = "sirf,prima2-usp"; | |
266 | reg = <0xb0090000 0x10000>; | |
267 | interrupts = <21>; | |
a1369978 | 268 | fifosize = <128>; |
eb8b8f2e | 269 | clocks = <&clks 29>; |
9be16b38 QL |
270 | dmas = <&dmac0 14>, <&dmac0 15>; |
271 | dma-names = "rx", "tx"; | |
02c981c0 BD |
272 | }; |
273 | ||
274 | usp2: usp@b00a0000 { | |
275 | cell-index = <2>; | |
276 | compatible = "sirf,prima2-usp"; | |
277 | reg = <0xb00a0000 0x10000>; | |
278 | interrupts = <22>; | |
a1369978 | 279 | fifosize = <128>; |
eb8b8f2e | 280 | clocks = <&clks 30>; |
9be16b38 QL |
281 | dmas = <&dmac0 10>, <&dmac0 11>; |
282 | dma-names = "rx", "tx"; | |
02c981c0 BD |
283 | }; |
284 | ||
285 | dmac0: dma-controller@b00b0000 { | |
286 | cell-index = <0>; | |
287 | compatible = "sirf,prima2-dmac"; | |
288 | reg = <0xb00b0000 0x10000>; | |
289 | interrupts = <12>; | |
eb8b8f2e | 290 | clocks = <&clks 24>; |
2e041c94 | 291 | #dma-cells = <1>; |
02c981c0 BD |
292 | }; |
293 | ||
294 | dmac1: dma-controller@b0160000 { | |
295 | cell-index = <1>; | |
296 | compatible = "sirf,prima2-dmac"; | |
297 | reg = <0xb0160000 0x10000>; | |
298 | interrupts = <13>; | |
eb8b8f2e | 299 | clocks = <&clks 25>; |
2e041c94 | 300 | #dma-cells = <1>; |
02c981c0 BD |
301 | }; |
302 | ||
303 | vip@b00C0000 { | |
304 | compatible = "sirf,prima2-vip"; | |
305 | reg = <0xb00C0000 0x10000>; | |
eb8b8f2e | 306 | clocks = <&clks 31>; |
262bcc1d RW |
307 | interrupts = <14>; |
308 | sirf,vip-dma-rx-channel = <16>; | |
02c981c0 BD |
309 | }; |
310 | ||
311 | spi0: spi@b00d0000 { | |
312 | cell-index = <0>; | |
313 | compatible = "sirf,prima2-spi"; | |
314 | reg = <0xb00d0000 0x10000>; | |
315 | interrupts = <15>; | |
6f425115 | 316 | sirf,spi-num-chipselects = <1>; |
e47a118b BS |
317 | dmas = <&dmac1 9>, |
318 | <&dmac1 4>; | |
319 | dma-names = "rx", "tx"; | |
6f425115 BS |
320 | #address-cells = <1>; |
321 | #size-cells = <0>; | |
eb8b8f2e | 322 | clocks = <&clks 19>; |
6f425115 | 323 | status = "disabled"; |
02c981c0 BD |
324 | }; |
325 | ||
326 | spi1: spi@b0170000 { | |
327 | cell-index = <1>; | |
328 | compatible = "sirf,prima2-spi"; | |
329 | reg = <0xb0170000 0x10000>; | |
330 | interrupts = <16>; | |
6f425115 | 331 | sirf,spi-num-chipselects = <1>; |
e47a118b BS |
332 | dmas = <&dmac0 12>, |
333 | <&dmac0 13>; | |
334 | dma-names = "rx", "tx"; | |
6f425115 BS |
335 | #address-cells = <1>; |
336 | #size-cells = <0>; | |
eb8b8f2e | 337 | clocks = <&clks 20>; |
6f425115 | 338 | status = "disabled"; |
02c981c0 BD |
339 | }; |
340 | ||
341 | i2c0: i2c@b00e0000 { | |
342 | cell-index = <0>; | |
343 | compatible = "sirf,prima2-i2c"; | |
344 | reg = <0xb00e0000 0x10000>; | |
345 | interrupts = <24>; | |
eb8b8f2e | 346 | clocks = <&clks 17>; |
7a54a4ba RW |
347 | #address-cells = <1>; |
348 | #size-cells = <0>; | |
02c981c0 BD |
349 | }; |
350 | ||
351 | i2c1: i2c@b00f0000 { | |
352 | cell-index = <1>; | |
353 | compatible = "sirf,prima2-i2c"; | |
354 | reg = <0xb00f0000 0x10000>; | |
355 | interrupts = <25>; | |
eb8b8f2e | 356 | clocks = <&clks 18>; |
7a54a4ba RW |
357 | #address-cells = <1>; |
358 | #size-cells = <0>; | |
02c981c0 BD |
359 | }; |
360 | ||
361 | tsc@b0110000 { | |
362 | compatible = "sirf,prima2-tsc"; | |
363 | reg = <0xb0110000 0x10000>; | |
364 | interrupts = <33>; | |
eb8b8f2e | 365 | clocks = <&clks 16>; |
02c981c0 BD |
366 | }; |
367 | ||
056876f6 | 368 | gpio: pinctrl@b0120000 { |
02c981c0 BD |
369 | #gpio-cells = <2>; |
370 | #interrupt-cells = <2>; | |
056876f6 | 371 | compatible = "sirf,prima2-pinctrl"; |
02c981c0 | 372 | reg = <0xb0120000 0x10000>; |
500b6ae3 | 373 | interrupts = <43 44 45 46 47>; |
02c981c0 BD |
374 | gpio-controller; |
375 | interrupt-controller; | |
056876f6 BS |
376 | |
377 | lcd_16pins_a: lcd0@0 { | |
378 | lcd { | |
379 | sirf,pins = "lcd_16bitsgrp"; | |
380 | sirf,function = "lcd_16bits"; | |
381 | }; | |
382 | }; | |
383 | lcd_18pins_a: lcd0@1 { | |
384 | lcd { | |
385 | sirf,pins = "lcd_18bitsgrp"; | |
386 | sirf,function = "lcd_18bits"; | |
387 | }; | |
388 | }; | |
389 | lcd_24pins_a: lcd0@2 { | |
390 | lcd { | |
391 | sirf,pins = "lcd_24bitsgrp"; | |
392 | sirf,function = "lcd_24bits"; | |
393 | }; | |
394 | }; | |
395 | lcdrom_pins_a: lcdrom0@0 { | |
396 | lcd { | |
397 | sirf,pins = "lcdromgrp"; | |
398 | sirf,function = "lcdrom"; | |
399 | }; | |
400 | }; | |
401 | uart0_pins_a: uart0@0 { | |
402 | uart { | |
403 | sirf,pins = "uart0grp"; | |
404 | sirf,function = "uart0"; | |
405 | }; | |
406 | }; | |
fb85f429 QL |
407 | uart0_noflow_pins_a: uart0@1 { |
408 | uart { | |
409 | sirf,pins = "uart0_nostreamctrlgrp"; | |
410 | sirf,function = "uart0_nostreamctrl"; | |
411 | }; | |
412 | }; | |
056876f6 BS |
413 | uart1_pins_a: uart1@0 { |
414 | uart { | |
415 | sirf,pins = "uart1grp"; | |
416 | sirf,function = "uart1"; | |
417 | }; | |
418 | }; | |
419 | uart2_pins_a: uart2@0 { | |
420 | uart { | |
421 | sirf,pins = "uart2grp"; | |
422 | sirf,function = "uart2"; | |
423 | }; | |
424 | }; | |
425 | uart2_noflow_pins_a: uart2@1 { | |
426 | uart { | |
427 | sirf,pins = "uart2_nostreamctrlgrp"; | |
428 | sirf,function = "uart2_nostreamctrl"; | |
429 | }; | |
430 | }; | |
431 | spi0_pins_a: spi0@0 { | |
432 | spi { | |
433 | sirf,pins = "spi0grp"; | |
434 | sirf,function = "spi0"; | |
435 | }; | |
436 | }; | |
437 | spi1_pins_a: spi1@0 { | |
438 | spi { | |
439 | sirf,pins = "spi1grp"; | |
440 | sirf,function = "spi1"; | |
441 | }; | |
442 | }; | |
443 | i2c0_pins_a: i2c0@0 { | |
444 | i2c { | |
445 | sirf,pins = "i2c0grp"; | |
446 | sirf,function = "i2c0"; | |
447 | }; | |
448 | }; | |
449 | i2c1_pins_a: i2c1@0 { | |
450 | i2c { | |
451 | sirf,pins = "i2c1grp"; | |
452 | sirf,function = "i2c1"; | |
453 | }; | |
454 | }; | |
455 | pwm0_pins_a: pwm0@0 { | |
456 | pwm { | |
457 | sirf,pins = "pwm0grp"; | |
458 | sirf,function = "pwm0"; | |
459 | }; | |
460 | }; | |
461 | pwm1_pins_a: pwm1@0 { | |
462 | pwm { | |
463 | sirf,pins = "pwm1grp"; | |
464 | sirf,function = "pwm1"; | |
465 | }; | |
466 | }; | |
467 | pwm2_pins_a: pwm2@0 { | |
468 | pwm { | |
469 | sirf,pins = "pwm2grp"; | |
470 | sirf,function = "pwm2"; | |
471 | }; | |
472 | }; | |
473 | pwm3_pins_a: pwm3@0 { | |
474 | pwm { | |
475 | sirf,pins = "pwm3grp"; | |
476 | sirf,function = "pwm3"; | |
477 | }; | |
478 | }; | |
479 | gps_pins_a: gps@0 { | |
480 | gps { | |
481 | sirf,pins = "gpsgrp"; | |
482 | sirf,function = "gps"; | |
483 | }; | |
484 | }; | |
485 | vip_pins_a: vip@0 { | |
486 | vip { | |
487 | sirf,pins = "vipgrp"; | |
488 | sirf,function = "vip"; | |
489 | }; | |
490 | }; | |
491 | sdmmc0_pins_a: sdmmc0@0 { | |
492 | sdmmc0 { | |
493 | sirf,pins = "sdmmc0grp"; | |
494 | sirf,function = "sdmmc0"; | |
495 | }; | |
496 | }; | |
497 | sdmmc1_pins_a: sdmmc1@0 { | |
498 | sdmmc1 { | |
499 | sirf,pins = "sdmmc1grp"; | |
500 | sirf,function = "sdmmc1"; | |
501 | }; | |
502 | }; | |
503 | sdmmc2_pins_a: sdmmc2@0 { | |
504 | sdmmc2 { | |
505 | sirf,pins = "sdmmc2grp"; | |
506 | sirf,function = "sdmmc2"; | |
507 | }; | |
508 | }; | |
509 | sdmmc3_pins_a: sdmmc3@0 { | |
510 | sdmmc3 { | |
511 | sirf,pins = "sdmmc3grp"; | |
512 | sirf,function = "sdmmc3"; | |
513 | }; | |
514 | }; | |
515 | sdmmc4_pins_a: sdmmc4@0 { | |
516 | sdmmc4 { | |
517 | sirf,pins = "sdmmc4grp"; | |
518 | sirf,function = "sdmmc4"; | |
519 | }; | |
520 | }; | |
521 | sdmmc5_pins_a: sdmmc5@0 { | |
522 | sdmmc5 { | |
523 | sirf,pins = "sdmmc5grp"; | |
524 | sirf,function = "sdmmc5"; | |
525 | }; | |
526 | }; | |
e6067f29 RY |
527 | i2s_mclk_pins_a: i2s_mclk@0 { |
528 | i2s_mclk { | |
529 | sirf,pins = "i2smclkgrp"; | |
530 | sirf,function = "i2s_mclk"; | |
531 | }; | |
532 | }; | |
533 | i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { | |
534 | i2s_ext_clk_input { | |
535 | sirf,pins = "i2s_ext_clk_inputgrp"; | |
536 | sirf,function = "i2s_ext_clk_input"; | |
537 | }; | |
538 | }; | |
056876f6 BS |
539 | i2s_pins_a: i2s@0 { |
540 | i2s { | |
541 | sirf,pins = "i2sgrp"; | |
542 | sirf,function = "i2s"; | |
543 | }; | |
544 | }; | |
e6067f29 RY |
545 | i2s_no_din_pins_a: i2s_no_din@0 { |
546 | i2s_no_din { | |
547 | sirf,pins = "i2s_no_dingrp"; | |
548 | sirf,function = "i2s_no_din"; | |
549 | }; | |
550 | }; | |
551 | i2s_6chn_pins_a: i2s_6chn@0 { | |
552 | i2s_6chn { | |
553 | sirf,pins = "i2s_6chngrp"; | |
554 | sirf,function = "i2s_6chn"; | |
555 | }; | |
556 | }; | |
056876f6 BS |
557 | ac97_pins_a: ac97@0 { |
558 | ac97 { | |
559 | sirf,pins = "ac97grp"; | |
560 | sirf,function = "ac97"; | |
561 | }; | |
562 | }; | |
563 | nand_pins_a: nand@0 { | |
564 | nand { | |
565 | sirf,pins = "nandgrp"; | |
566 | sirf,function = "nand"; | |
567 | }; | |
568 | }; | |
569 | usp0_pins_a: usp0@0 { | |
570 | usp0 { | |
571 | sirf,pins = "usp0grp"; | |
572 | sirf,function = "usp0"; | |
573 | }; | |
574 | }; | |
af614b23 QL |
575 | usp0_uart_nostreamctrl_pins_a: usp0@1 { |
576 | usp0 { | |
577 | sirf,pins = | |
578 | "usp0_uart_nostreamctrl_grp"; | |
579 | sirf,function = | |
580 | "usp0_uart_nostreamctrl"; | |
581 | }; | |
582 | }; | |
73f68c01 RY |
583 | usp0_only_utfs_pins_a: usp0@2 { |
584 | usp0 { | |
585 | sirf,pins = "usp0_only_utfs_grp"; | |
586 | sirf,function = "usp0_only_utfs"; | |
587 | }; | |
588 | }; | |
589 | usp0_only_urfs_pins_a: usp0@3 { | |
590 | usp0 { | |
591 | sirf,pins = "usp0_only_urfs_grp"; | |
592 | sirf,function = "usp0_only_urfs"; | |
593 | }; | |
594 | }; | |
056876f6 BS |
595 | usp1_pins_a: usp1@0 { |
596 | usp1 { | |
597 | sirf,pins = "usp1grp"; | |
598 | sirf,function = "usp1"; | |
599 | }; | |
600 | }; | |
af614b23 QL |
601 | usp1_uart_nostreamctrl_pins_a: usp1@1 { |
602 | usp1 { | |
603 | sirf,pins = | |
604 | "usp1_uart_nostreamctrl_grp"; | |
605 | sirf,function = | |
606 | "usp1_uart_nostreamctrl"; | |
607 | }; | |
608 | }; | |
056876f6 BS |
609 | usp2_pins_a: usp2@0 { |
610 | usp2 { | |
611 | sirf,pins = "usp2grp"; | |
612 | sirf,function = "usp2"; | |
613 | }; | |
614 | }; | |
af614b23 QL |
615 | usp2_uart_nostreamctrl_pins_a: usp2@1 { |
616 | usp2 { | |
617 | sirf,pins = | |
618 | "usp2_uart_nostreamctrl_grp"; | |
619 | sirf,function = | |
620 | "usp2_uart_nostreamctrl"; | |
621 | }; | |
622 | }; | |
056876f6 BS |
623 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { |
624 | usb0_utmi_drvbus { | |
625 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
626 | sirf,function = "usb0_utmi_drvbus"; | |
627 | }; | |
628 | }; | |
629 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
630 | usb1_utmi_drvbus { | |
631 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
632 | sirf,function = "usb1_utmi_drvbus"; | |
633 | }; | |
634 | }; | |
6a08a92e RW |
635 | usb1_dp_dn_pins_a: usb1_dp_dn@0 { |
636 | usb1_dp_dn { | |
637 | sirf,pins = "usb1_dp_dngrp"; | |
638 | sirf,function = "usb1_dp_dn"; | |
639 | }; | |
640 | }; | |
641 | uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 { | |
642 | uart1_route_io_usb1 { | |
643 | sirf,pins = "uart1_route_io_usb1grp"; | |
644 | sirf,function = "uart1_route_io_usb1"; | |
645 | }; | |
646 | }; | |
056876f6 BS |
647 | warm_rst_pins_a: warm_rst@0 { |
648 | warm_rst { | |
649 | sirf,pins = "warm_rstgrp"; | |
650 | sirf,function = "warm_rst"; | |
651 | }; | |
652 | }; | |
653 | pulse_count_pins_a: pulse_count@0 { | |
654 | pulse_count { | |
655 | sirf,pins = "pulse_countgrp"; | |
656 | sirf,function = "pulse_count"; | |
657 | }; | |
658 | }; | |
c8078de8 BS |
659 | cko0_pins_a: cko0@0 { |
660 | cko0 { | |
661 | sirf,pins = "cko0grp"; | |
662 | sirf,function = "cko0"; | |
056876f6 BS |
663 | }; |
664 | }; | |
c8078de8 BS |
665 | cko1_pins_a: cko1@0 { |
666 | cko1 { | |
667 | sirf,pins = "cko1grp"; | |
668 | sirf,function = "cko1"; | |
056876f6 BS |
669 | }; |
670 | }; | |
02c981c0 BD |
671 | }; |
672 | ||
673 | pwm@b0130000 { | |
674 | compatible = "sirf,prima2-pwm"; | |
675 | reg = <0xb0130000 0x10000>; | |
eb8b8f2e | 676 | clocks = <&clks 21>; |
02c981c0 BD |
677 | }; |
678 | ||
679 | efusesys@b0140000 { | |
680 | compatible = "sirf,prima2-efuse"; | |
681 | reg = <0xb0140000 0x10000>; | |
eb8b8f2e | 682 | clocks = <&clks 22>; |
02c981c0 BD |
683 | }; |
684 | ||
685 | pulsec@b0150000 { | |
686 | compatible = "sirf,prima2-pulsec"; | |
687 | reg = <0xb0150000 0x10000>; | |
688 | interrupts = <48>; | |
eb8b8f2e | 689 | clocks = <&clks 23>; |
02c981c0 BD |
690 | }; |
691 | ||
692 | pci-iobg { | |
693 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
694 | #address-cells = <1>; | |
695 | #size-cells = <1>; | |
696 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
697 | ||
698 | sd0: sdhci@56000000 { | |
699 | cell-index = <0>; | |
700 | compatible = "sirf,prima2-sdhc"; | |
701 | reg = <0x56000000 0x100000>; | |
702 | interrupts = <38>; | |
7f97c303 BS |
703 | status = "disabled"; |
704 | bus-width = <8>; | |
705 | clocks = <&clks 36>; | |
02c981c0 BD |
706 | }; |
707 | ||
708 | sd1: sdhci@56100000 { | |
709 | cell-index = <1>; | |
710 | compatible = "sirf,prima2-sdhc"; | |
711 | reg = <0x56100000 0x100000>; | |
712 | interrupts = <38>; | |
7f97c303 BS |
713 | status = "disabled"; |
714 | bus-width = <4>; | |
715 | clocks = <&clks 36>; | |
02c981c0 BD |
716 | }; |
717 | ||
718 | sd2: sdhci@56200000 { | |
719 | cell-index = <2>; | |
720 | compatible = "sirf,prima2-sdhc"; | |
721 | reg = <0x56200000 0x100000>; | |
722 | interrupts = <23>; | |
7f97c303 BS |
723 | status = "disabled"; |
724 | clocks = <&clks 37>; | |
02c981c0 BD |
725 | }; |
726 | ||
727 | sd3: sdhci@56300000 { | |
728 | cell-index = <3>; | |
729 | compatible = "sirf,prima2-sdhc"; | |
730 | reg = <0x56300000 0x100000>; | |
731 | interrupts = <23>; | |
7f97c303 BS |
732 | status = "disabled"; |
733 | clocks = <&clks 37>; | |
02c981c0 BD |
734 | }; |
735 | ||
736 | sd4: sdhci@56400000 { | |
737 | cell-index = <4>; | |
738 | compatible = "sirf,prima2-sdhc"; | |
739 | reg = <0x56400000 0x100000>; | |
740 | interrupts = <39>; | |
7f97c303 BS |
741 | status = "disabled"; |
742 | clocks = <&clks 38>; | |
02c981c0 BD |
743 | }; |
744 | ||
745 | sd5: sdhci@56500000 { | |
746 | cell-index = <5>; | |
747 | compatible = "sirf,prima2-sdhc"; | |
748 | reg = <0x56500000 0x100000>; | |
749 | interrupts = <39>; | |
7f97c303 | 750 | clocks = <&clks 38>; |
02c981c0 BD |
751 | }; |
752 | ||
753 | pci-copy@57900000 { | |
754 | compatible = "sirf,prima2-pcicp"; | |
755 | reg = <0x57900000 0x100000>; | |
756 | interrupts = <40>; | |
757 | }; | |
758 | ||
759 | rom-interface@57a00000 { | |
760 | compatible = "sirf,prima2-romif"; | |
761 | reg = <0x57a00000 0x100000>; | |
762 | }; | |
763 | }; | |
764 | }; | |
765 | ||
766 | rtc-iobg { | |
e88b815e | 767 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
02c981c0 BD |
768 | #address-cells = <1>; |
769 | #size-cells = <1>; | |
770 | reg = <0x80030000 0x10000>; | |
771 | ||
772 | gpsrtc@1000 { | |
773 | compatible = "sirf,prima2-gpsrtc"; | |
774 | reg = <0x1000 0x1000>; | |
775 | interrupts = <55 56 57>; | |
776 | }; | |
777 | ||
778 | sysrtc@2000 { | |
779 | compatible = "sirf,prima2-sysrtc"; | |
780 | reg = <0x2000 0x1000>; | |
781 | interrupts = <52 53 54>; | |
782 | }; | |
783 | ||
423ef791 XD |
784 | minigpsrtc@2000 { |
785 | compatible = "sirf,prima2-minigpsrtc"; | |
786 | reg = <0x2000 0x1000>; | |
787 | interrupts = <54>; | |
788 | }; | |
789 | ||
02c981c0 BD |
790 | pwrc@3000 { |
791 | compatible = "sirf,prima2-pwrc"; | |
792 | reg = <0x3000 0x1000>; | |
793 | interrupts = <32>; | |
794 | }; | |
795 | }; | |
796 | ||
797 | uus-iobg { | |
798 | compatible = "simple-bus"; | |
799 | #address-cells = <1>; | |
800 | #size-cells = <1>; | |
801 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
802 | ||
803 | usb0: usb@b00e0000 { | |
804 | compatible = "chipidea,ci13611a-prima2"; | |
805 | reg = <0xb8000000 0x10000>; | |
806 | interrupts = <10>; | |
eb8b8f2e | 807 | clocks = <&clks 40>; |
02c981c0 BD |
808 | }; |
809 | ||
810 | usb1: usb@b00f0000 { | |
811 | compatible = "chipidea,ci13611a-prima2"; | |
812 | reg = <0xb8010000 0x10000>; | |
813 | interrupts = <11>; | |
eb8b8f2e | 814 | clocks = <&clks 41>; |
02c981c0 BD |
815 | }; |
816 | ||
817 | sata@b00f0000 { | |
818 | compatible = "synopsys,dwc-ahsata"; | |
819 | reg = <0xb8020000 0x10000>; | |
820 | interrupts = <37>; | |
821 | }; | |
822 | ||
823 | security@b00f0000 { | |
824 | compatible = "sirf,prima2-security"; | |
825 | reg = <0xb8030000 0x10000>; | |
826 | interrupts = <42>; | |
eb8b8f2e | 827 | clocks = <&clks 7>; |
02c981c0 BD |
828 | }; |
829 | }; | |
830 | }; | |
831 | }; |