Commit | Line | Data |
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434e1c57 BS |
1 | /* |
2 | * DTS file for CSR SiRFprimaII SoC | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
02c981c0 | 10 | / { |
434e1c57 | 11 | compatible = "sirf,prima2"; |
02c981c0 BD |
12 | #address-cells = <1>; |
13 | #size-cells = <1>; | |
14 | interrupt-parent = <&intc>; | |
15 | ||
02c981c0 BD |
16 | cpus { |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
20 | cpu@0 { | |
cc73f875 LP |
21 | compatible = "arm,cortex-a9"; |
22 | device_type = "cpu"; | |
02c981c0 BD |
23 | reg = <0x0>; |
24 | d-cache-line-size = <32>; | |
25 | i-cache-line-size = <32>; | |
26 | d-cache-size = <32768>; | |
27 | i-cache-size = <32768>; | |
28 | /* from bootloader */ | |
29 | timebase-frequency = <0>; | |
30 | bus-frequency = <0>; | |
31 | clock-frequency = <0>; | |
32 | }; | |
33 | }; | |
34 | ||
35 | axi { | |
36 | compatible = "simple-bus"; | |
37 | #address-cells = <1>; | |
38 | #size-cells = <1>; | |
39 | ranges = <0x40000000 0x40000000 0x80000000>; | |
40 | ||
41 | l2-cache-controller@80040000 { | |
917d8535 | 42 | compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache"; |
02c981c0 BD |
43 | reg = <0x80040000 0x1000>; |
44 | interrupts = <59>; | |
917d8535 BS |
45 | arm,tag-latency = <1 1 1>; |
46 | arm,data-latency = <1 1 1>; | |
47 | arm,filter-ranges = <0 0x40000000>; | |
02c981c0 BD |
48 | }; |
49 | ||
50 | intc: interrupt-controller@80020000 { | |
51 | #interrupt-cells = <1>; | |
52 | interrupt-controller; | |
53 | compatible = "sirf,prima2-intc"; | |
54 | reg = <0x80020000 0x1000>; | |
55 | }; | |
56 | ||
57 | sys-iobg { | |
58 | compatible = "simple-bus"; | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges = <0x88000000 0x88000000 0x40000>; | |
62 | ||
eb8b8f2e | 63 | clks: clock-controller@88000000 { |
02c981c0 BD |
64 | compatible = "sirf,prima2-clkc"; |
65 | reg = <0x88000000 0x1000>; | |
66 | interrupts = <3>; | |
eb8b8f2e | 67 | #clock-cells = <1>; |
02c981c0 BD |
68 | }; |
69 | ||
70 | reset-controller@88010000 { | |
71 | compatible = "sirf,prima2-rstc"; | |
72 | reg = <0x88010000 0x1000>; | |
73 | }; | |
073adf4f BS |
74 | |
75 | rsc-controller@88020000 { | |
76 | compatible = "sirf,prima2-rsc"; | |
77 | reg = <0x88020000 0x1000>; | |
78 | }; | |
02c981c0 BD |
79 | }; |
80 | ||
81 | mem-iobg { | |
82 | compatible = "simple-bus"; | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | ranges = <0x90000000 0x90000000 0x10000>; | |
86 | ||
87 | memory-controller@90000000 { | |
88 | compatible = "sirf,prima2-memc"; | |
89 | reg = <0x90000000 0x10000>; | |
90 | interrupts = <27>; | |
eb8b8f2e | 91 | clocks = <&clks 5>; |
02c981c0 BD |
92 | }; |
93 | }; | |
94 | ||
95 | disp-iobg { | |
96 | compatible = "simple-bus"; | |
97 | #address-cells = <1>; | |
98 | #size-cells = <1>; | |
99 | ranges = <0x90010000 0x90010000 0x30000>; | |
100 | ||
101 | display@90010000 { | |
102 | compatible = "sirf,prima2-lcd"; | |
103 | reg = <0x90010000 0x20000>; | |
104 | interrupts = <30>; | |
105 | }; | |
106 | ||
107 | vpp@90020000 { | |
108 | compatible = "sirf,prima2-vpp"; | |
109 | reg = <0x90020000 0x10000>; | |
110 | interrupts = <31>; | |
eb8b8f2e | 111 | clocks = <&clks 35>; |
02c981c0 BD |
112 | }; |
113 | }; | |
114 | ||
115 | graphics-iobg { | |
116 | compatible = "simple-bus"; | |
117 | #address-cells = <1>; | |
118 | #size-cells = <1>; | |
119 | ranges = <0x98000000 0x98000000 0x8000000>; | |
120 | ||
121 | graphics@98000000 { | |
122 | compatible = "powervr,sgx531"; | |
123 | reg = <0x98000000 0x8000000>; | |
124 | interrupts = <6>; | |
eb8b8f2e | 125 | clocks = <&clks 32>; |
02c981c0 BD |
126 | }; |
127 | }; | |
128 | ||
129 | multimedia-iobg { | |
130 | compatible = "simple-bus"; | |
131 | #address-cells = <1>; | |
132 | #size-cells = <1>; | |
133 | ranges = <0xa0000000 0xa0000000 0x8000000>; | |
134 | ||
135 | multimedia@a0000000 { | |
136 | compatible = "sirf,prima2-video-codec"; | |
137 | reg = <0xa0000000 0x8000000>; | |
138 | interrupts = <5>; | |
eb8b8f2e | 139 | clocks = <&clks 33>; |
02c981c0 BD |
140 | }; |
141 | }; | |
142 | ||
143 | dsp-iobg { | |
144 | compatible = "simple-bus"; | |
145 | #address-cells = <1>; | |
146 | #size-cells = <1>; | |
147 | ranges = <0xa8000000 0xa8000000 0x2000000>; | |
148 | ||
149 | dspif@a8000000 { | |
150 | compatible = "sirf,prima2-dspif"; | |
151 | reg = <0xa8000000 0x10000>; | |
152 | interrupts = <9>; | |
153 | }; | |
154 | ||
155 | gps@a8010000 { | |
156 | compatible = "sirf,prima2-gps"; | |
157 | reg = <0xa8010000 0x10000>; | |
158 | interrupts = <7>; | |
eb8b8f2e | 159 | clocks = <&clks 9>; |
02c981c0 BD |
160 | }; |
161 | ||
162 | dsp@a9000000 { | |
163 | compatible = "sirf,prima2-dsp"; | |
164 | reg = <0xa9000000 0x1000000>; | |
165 | interrupts = <8>; | |
eb8b8f2e | 166 | clocks = <&clks 8>; |
02c981c0 BD |
167 | }; |
168 | }; | |
169 | ||
170 | peri-iobg { | |
171 | compatible = "simple-bus"; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <1>; | |
9e85b9d1 BS |
174 | ranges = <0xb0000000 0xb0000000 0x180000>, |
175 | <0x56000000 0x56000000 0x1b00000>; | |
02c981c0 BD |
176 | |
177 | timer@b0020000 { | |
178 | compatible = "sirf,prima2-tick"; | |
179 | reg = <0xb0020000 0x1000>; | |
180 | interrupts = <0>; | |
181 | }; | |
182 | ||
183 | nand@b0030000 { | |
184 | compatible = "sirf,prima2-nand"; | |
185 | reg = <0xb0030000 0x10000>; | |
186 | interrupts = <41>; | |
eb8b8f2e | 187 | clocks = <&clks 26>; |
02c981c0 BD |
188 | }; |
189 | ||
190 | audio@b0040000 { | |
191 | compatible = "sirf,prima2-audio"; | |
192 | reg = <0xb0040000 0x10000>; | |
193 | interrupts = <35>; | |
eb8b8f2e | 194 | clocks = <&clks 27>; |
02c981c0 BD |
195 | }; |
196 | ||
197 | uart0: uart@b0050000 { | |
198 | cell-index = <0>; | |
199 | compatible = "sirf,prima2-uart"; | |
a1369978 | 200 | reg = <0xb0050000 0x1000>; |
02c981c0 | 201 | interrupts = <17>; |
a1369978 | 202 | fifosize = <128>; |
eb8b8f2e | 203 | clocks = <&clks 13>; |
a1369978 QL |
204 | sirf,uart-dma-rx-channel = <21>; |
205 | sirf,uart-dma-tx-channel = <2>; | |
02c981c0 BD |
206 | }; |
207 | ||
208 | uart1: uart@b0060000 { | |
209 | cell-index = <1>; | |
210 | compatible = "sirf,prima2-uart"; | |
a1369978 | 211 | reg = <0xb0060000 0x1000>; |
02c981c0 | 212 | interrupts = <18>; |
a1369978 | 213 | fifosize = <32>; |
eb8b8f2e | 214 | clocks = <&clks 14>; |
02c981c0 BD |
215 | }; |
216 | ||
217 | uart2: uart@b0070000 { | |
218 | cell-index = <2>; | |
219 | compatible = "sirf,prima2-uart"; | |
a1369978 | 220 | reg = <0xb0070000 0x1000>; |
02c981c0 | 221 | interrupts = <19>; |
a1369978 | 222 | fifosize = <128>; |
eb8b8f2e | 223 | clocks = <&clks 15>; |
a1369978 QL |
224 | sirf,uart-dma-rx-channel = <6>; |
225 | sirf,uart-dma-tx-channel = <7>; | |
02c981c0 BD |
226 | }; |
227 | ||
228 | usp0: usp@b0080000 { | |
229 | cell-index = <0>; | |
230 | compatible = "sirf,prima2-usp"; | |
231 | reg = <0xb0080000 0x10000>; | |
232 | interrupts = <20>; | |
a1369978 | 233 | fifosize = <128>; |
eb8b8f2e | 234 | clocks = <&clks 28>; |
a1369978 QL |
235 | sirf,usp-dma-rx-channel = <17>; |
236 | sirf,usp-dma-tx-channel = <18>; | |
02c981c0 BD |
237 | }; |
238 | ||
239 | usp1: usp@b0090000 { | |
240 | cell-index = <1>; | |
241 | compatible = "sirf,prima2-usp"; | |
242 | reg = <0xb0090000 0x10000>; | |
243 | interrupts = <21>; | |
a1369978 | 244 | fifosize = <128>; |
eb8b8f2e | 245 | clocks = <&clks 29>; |
a1369978 QL |
246 | sirf,usp-dma-rx-channel = <14>; |
247 | sirf,usp-dma-tx-channel = <15>; | |
02c981c0 BD |
248 | }; |
249 | ||
250 | usp2: usp@b00a0000 { | |
251 | cell-index = <2>; | |
252 | compatible = "sirf,prima2-usp"; | |
253 | reg = <0xb00a0000 0x10000>; | |
254 | interrupts = <22>; | |
a1369978 | 255 | fifosize = <128>; |
eb8b8f2e | 256 | clocks = <&clks 30>; |
a1369978 QL |
257 | sirf,usp-dma-rx-channel = <10>; |
258 | sirf,usp-dma-tx-channel = <11>; | |
02c981c0 BD |
259 | }; |
260 | ||
261 | dmac0: dma-controller@b00b0000 { | |
262 | cell-index = <0>; | |
263 | compatible = "sirf,prima2-dmac"; | |
264 | reg = <0xb00b0000 0x10000>; | |
265 | interrupts = <12>; | |
eb8b8f2e | 266 | clocks = <&clks 24>; |
02c981c0 BD |
267 | }; |
268 | ||
269 | dmac1: dma-controller@b0160000 { | |
270 | cell-index = <1>; | |
271 | compatible = "sirf,prima2-dmac"; | |
272 | reg = <0xb0160000 0x10000>; | |
273 | interrupts = <13>; | |
eb8b8f2e | 274 | clocks = <&clks 25>; |
02c981c0 BD |
275 | }; |
276 | ||
277 | vip@b00C0000 { | |
278 | compatible = "sirf,prima2-vip"; | |
279 | reg = <0xb00C0000 0x10000>; | |
eb8b8f2e | 280 | clocks = <&clks 31>; |
262bcc1d RW |
281 | interrupts = <14>; |
282 | sirf,vip-dma-rx-channel = <16>; | |
02c981c0 BD |
283 | }; |
284 | ||
285 | spi0: spi@b00d0000 { | |
286 | cell-index = <0>; | |
287 | compatible = "sirf,prima2-spi"; | |
288 | reg = <0xb00d0000 0x10000>; | |
289 | interrupts = <15>; | |
eb8b8f2e | 290 | clocks = <&clks 19>; |
02c981c0 BD |
291 | }; |
292 | ||
293 | spi1: spi@b0170000 { | |
294 | cell-index = <1>; | |
295 | compatible = "sirf,prima2-spi"; | |
296 | reg = <0xb0170000 0x10000>; | |
297 | interrupts = <16>; | |
eb8b8f2e | 298 | clocks = <&clks 20>; |
02c981c0 BD |
299 | }; |
300 | ||
301 | i2c0: i2c@b00e0000 { | |
302 | cell-index = <0>; | |
303 | compatible = "sirf,prima2-i2c"; | |
304 | reg = <0xb00e0000 0x10000>; | |
305 | interrupts = <24>; | |
eb8b8f2e | 306 | clocks = <&clks 17>; |
02c981c0 BD |
307 | }; |
308 | ||
309 | i2c1: i2c@b00f0000 { | |
310 | cell-index = <1>; | |
311 | compatible = "sirf,prima2-i2c"; | |
312 | reg = <0xb00f0000 0x10000>; | |
313 | interrupts = <25>; | |
eb8b8f2e | 314 | clocks = <&clks 18>; |
02c981c0 BD |
315 | }; |
316 | ||
317 | tsc@b0110000 { | |
318 | compatible = "sirf,prima2-tsc"; | |
319 | reg = <0xb0110000 0x10000>; | |
320 | interrupts = <33>; | |
eb8b8f2e | 321 | clocks = <&clks 16>; |
02c981c0 BD |
322 | }; |
323 | ||
056876f6 | 324 | gpio: pinctrl@b0120000 { |
02c981c0 BD |
325 | #gpio-cells = <2>; |
326 | #interrupt-cells = <2>; | |
056876f6 | 327 | compatible = "sirf,prima2-pinctrl"; |
02c981c0 | 328 | reg = <0xb0120000 0x10000>; |
500b6ae3 | 329 | interrupts = <43 44 45 46 47>; |
02c981c0 BD |
330 | gpio-controller; |
331 | interrupt-controller; | |
056876f6 BS |
332 | |
333 | lcd_16pins_a: lcd0@0 { | |
334 | lcd { | |
335 | sirf,pins = "lcd_16bitsgrp"; | |
336 | sirf,function = "lcd_16bits"; | |
337 | }; | |
338 | }; | |
339 | lcd_18pins_a: lcd0@1 { | |
340 | lcd { | |
341 | sirf,pins = "lcd_18bitsgrp"; | |
342 | sirf,function = "lcd_18bits"; | |
343 | }; | |
344 | }; | |
345 | lcd_24pins_a: lcd0@2 { | |
346 | lcd { | |
347 | sirf,pins = "lcd_24bitsgrp"; | |
348 | sirf,function = "lcd_24bits"; | |
349 | }; | |
350 | }; | |
351 | lcdrom_pins_a: lcdrom0@0 { | |
352 | lcd { | |
353 | sirf,pins = "lcdromgrp"; | |
354 | sirf,function = "lcdrom"; | |
355 | }; | |
356 | }; | |
357 | uart0_pins_a: uart0@0 { | |
358 | uart { | |
359 | sirf,pins = "uart0grp"; | |
360 | sirf,function = "uart0"; | |
361 | }; | |
362 | }; | |
363 | uart1_pins_a: uart1@0 { | |
364 | uart { | |
365 | sirf,pins = "uart1grp"; | |
366 | sirf,function = "uart1"; | |
367 | }; | |
368 | }; | |
369 | uart2_pins_a: uart2@0 { | |
370 | uart { | |
371 | sirf,pins = "uart2grp"; | |
372 | sirf,function = "uart2"; | |
373 | }; | |
374 | }; | |
375 | uart2_noflow_pins_a: uart2@1 { | |
376 | uart { | |
377 | sirf,pins = "uart2_nostreamctrlgrp"; | |
378 | sirf,function = "uart2_nostreamctrl"; | |
379 | }; | |
380 | }; | |
381 | spi0_pins_a: spi0@0 { | |
382 | spi { | |
383 | sirf,pins = "spi0grp"; | |
384 | sirf,function = "spi0"; | |
385 | }; | |
386 | }; | |
387 | spi1_pins_a: spi1@0 { | |
388 | spi { | |
389 | sirf,pins = "spi1grp"; | |
390 | sirf,function = "spi1"; | |
391 | }; | |
392 | }; | |
393 | i2c0_pins_a: i2c0@0 { | |
394 | i2c { | |
395 | sirf,pins = "i2c0grp"; | |
396 | sirf,function = "i2c0"; | |
397 | }; | |
398 | }; | |
399 | i2c1_pins_a: i2c1@0 { | |
400 | i2c { | |
401 | sirf,pins = "i2c1grp"; | |
402 | sirf,function = "i2c1"; | |
403 | }; | |
404 | }; | |
405 | pwm0_pins_a: pwm0@0 { | |
406 | pwm { | |
407 | sirf,pins = "pwm0grp"; | |
408 | sirf,function = "pwm0"; | |
409 | }; | |
410 | }; | |
411 | pwm1_pins_a: pwm1@0 { | |
412 | pwm { | |
413 | sirf,pins = "pwm1grp"; | |
414 | sirf,function = "pwm1"; | |
415 | }; | |
416 | }; | |
417 | pwm2_pins_a: pwm2@0 { | |
418 | pwm { | |
419 | sirf,pins = "pwm2grp"; | |
420 | sirf,function = "pwm2"; | |
421 | }; | |
422 | }; | |
423 | pwm3_pins_a: pwm3@0 { | |
424 | pwm { | |
425 | sirf,pins = "pwm3grp"; | |
426 | sirf,function = "pwm3"; | |
427 | }; | |
428 | }; | |
429 | gps_pins_a: gps@0 { | |
430 | gps { | |
431 | sirf,pins = "gpsgrp"; | |
432 | sirf,function = "gps"; | |
433 | }; | |
434 | }; | |
435 | vip_pins_a: vip@0 { | |
436 | vip { | |
437 | sirf,pins = "vipgrp"; | |
438 | sirf,function = "vip"; | |
439 | }; | |
440 | }; | |
441 | sdmmc0_pins_a: sdmmc0@0 { | |
442 | sdmmc0 { | |
443 | sirf,pins = "sdmmc0grp"; | |
444 | sirf,function = "sdmmc0"; | |
445 | }; | |
446 | }; | |
447 | sdmmc1_pins_a: sdmmc1@0 { | |
448 | sdmmc1 { | |
449 | sirf,pins = "sdmmc1grp"; | |
450 | sirf,function = "sdmmc1"; | |
451 | }; | |
452 | }; | |
453 | sdmmc2_pins_a: sdmmc2@0 { | |
454 | sdmmc2 { | |
455 | sirf,pins = "sdmmc2grp"; | |
456 | sirf,function = "sdmmc2"; | |
457 | }; | |
458 | }; | |
459 | sdmmc3_pins_a: sdmmc3@0 { | |
460 | sdmmc3 { | |
461 | sirf,pins = "sdmmc3grp"; | |
462 | sirf,function = "sdmmc3"; | |
463 | }; | |
464 | }; | |
465 | sdmmc4_pins_a: sdmmc4@0 { | |
466 | sdmmc4 { | |
467 | sirf,pins = "sdmmc4grp"; | |
468 | sirf,function = "sdmmc4"; | |
469 | }; | |
470 | }; | |
471 | sdmmc5_pins_a: sdmmc5@0 { | |
472 | sdmmc5 { | |
473 | sirf,pins = "sdmmc5grp"; | |
474 | sirf,function = "sdmmc5"; | |
475 | }; | |
476 | }; | |
477 | i2s_pins_a: i2s@0 { | |
478 | i2s { | |
479 | sirf,pins = "i2sgrp"; | |
480 | sirf,function = "i2s"; | |
481 | }; | |
482 | }; | |
483 | ac97_pins_a: ac97@0 { | |
484 | ac97 { | |
485 | sirf,pins = "ac97grp"; | |
486 | sirf,function = "ac97"; | |
487 | }; | |
488 | }; | |
489 | nand_pins_a: nand@0 { | |
490 | nand { | |
491 | sirf,pins = "nandgrp"; | |
492 | sirf,function = "nand"; | |
493 | }; | |
494 | }; | |
495 | usp0_pins_a: usp0@0 { | |
496 | usp0 { | |
497 | sirf,pins = "usp0grp"; | |
498 | sirf,function = "usp0"; | |
499 | }; | |
500 | }; | |
501 | usp1_pins_a: usp1@0 { | |
502 | usp1 { | |
503 | sirf,pins = "usp1grp"; | |
504 | sirf,function = "usp1"; | |
505 | }; | |
506 | }; | |
507 | usp2_pins_a: usp2@0 { | |
508 | usp2 { | |
509 | sirf,pins = "usp2grp"; | |
510 | sirf,function = "usp2"; | |
511 | }; | |
512 | }; | |
513 | usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { | |
514 | usb0_utmi_drvbus { | |
515 | sirf,pins = "usb0_utmi_drvbusgrp"; | |
516 | sirf,function = "usb0_utmi_drvbus"; | |
517 | }; | |
518 | }; | |
519 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | |
520 | usb1_utmi_drvbus { | |
521 | sirf,pins = "usb1_utmi_drvbusgrp"; | |
522 | sirf,function = "usb1_utmi_drvbus"; | |
523 | }; | |
524 | }; | |
525 | warm_rst_pins_a: warm_rst@0 { | |
526 | warm_rst { | |
527 | sirf,pins = "warm_rstgrp"; | |
528 | sirf,function = "warm_rst"; | |
529 | }; | |
530 | }; | |
531 | pulse_count_pins_a: pulse_count@0 { | |
532 | pulse_count { | |
533 | sirf,pins = "pulse_countgrp"; | |
534 | sirf,function = "pulse_count"; | |
535 | }; | |
536 | }; | |
c8078de8 BS |
537 | cko0_pins_a: cko0@0 { |
538 | cko0 { | |
539 | sirf,pins = "cko0grp"; | |
540 | sirf,function = "cko0"; | |
056876f6 BS |
541 | }; |
542 | }; | |
c8078de8 BS |
543 | cko1_pins_a: cko1@0 { |
544 | cko1 { | |
545 | sirf,pins = "cko1grp"; | |
546 | sirf,function = "cko1"; | |
056876f6 BS |
547 | }; |
548 | }; | |
02c981c0 BD |
549 | }; |
550 | ||
551 | pwm@b0130000 { | |
552 | compatible = "sirf,prima2-pwm"; | |
553 | reg = <0xb0130000 0x10000>; | |
eb8b8f2e | 554 | clocks = <&clks 21>; |
02c981c0 BD |
555 | }; |
556 | ||
557 | efusesys@b0140000 { | |
558 | compatible = "sirf,prima2-efuse"; | |
559 | reg = <0xb0140000 0x10000>; | |
eb8b8f2e | 560 | clocks = <&clks 22>; |
02c981c0 BD |
561 | }; |
562 | ||
563 | pulsec@b0150000 { | |
564 | compatible = "sirf,prima2-pulsec"; | |
565 | reg = <0xb0150000 0x10000>; | |
566 | interrupts = <48>; | |
eb8b8f2e | 567 | clocks = <&clks 23>; |
02c981c0 BD |
568 | }; |
569 | ||
570 | pci-iobg { | |
571 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | |
572 | #address-cells = <1>; | |
573 | #size-cells = <1>; | |
574 | ranges = <0x56000000 0x56000000 0x1b00000>; | |
575 | ||
576 | sd0: sdhci@56000000 { | |
577 | cell-index = <0>; | |
578 | compatible = "sirf,prima2-sdhc"; | |
579 | reg = <0x56000000 0x100000>; | |
580 | interrupts = <38>; | |
581 | }; | |
582 | ||
583 | sd1: sdhci@56100000 { | |
584 | cell-index = <1>; | |
585 | compatible = "sirf,prima2-sdhc"; | |
586 | reg = <0x56100000 0x100000>; | |
587 | interrupts = <38>; | |
588 | }; | |
589 | ||
590 | sd2: sdhci@56200000 { | |
591 | cell-index = <2>; | |
592 | compatible = "sirf,prima2-sdhc"; | |
593 | reg = <0x56200000 0x100000>; | |
594 | interrupts = <23>; | |
595 | }; | |
596 | ||
597 | sd3: sdhci@56300000 { | |
598 | cell-index = <3>; | |
599 | compatible = "sirf,prima2-sdhc"; | |
600 | reg = <0x56300000 0x100000>; | |
601 | interrupts = <23>; | |
602 | }; | |
603 | ||
604 | sd4: sdhci@56400000 { | |
605 | cell-index = <4>; | |
606 | compatible = "sirf,prima2-sdhc"; | |
607 | reg = <0x56400000 0x100000>; | |
608 | interrupts = <39>; | |
609 | }; | |
610 | ||
611 | sd5: sdhci@56500000 { | |
612 | cell-index = <5>; | |
613 | compatible = "sirf,prima2-sdhc"; | |
614 | reg = <0x56500000 0x100000>; | |
615 | interrupts = <39>; | |
616 | }; | |
617 | ||
618 | pci-copy@57900000 { | |
619 | compatible = "sirf,prima2-pcicp"; | |
620 | reg = <0x57900000 0x100000>; | |
621 | interrupts = <40>; | |
622 | }; | |
623 | ||
624 | rom-interface@57a00000 { | |
625 | compatible = "sirf,prima2-romif"; | |
626 | reg = <0x57a00000 0x100000>; | |
627 | }; | |
628 | }; | |
629 | }; | |
630 | ||
631 | rtc-iobg { | |
e88b815e | 632 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus"; |
02c981c0 BD |
633 | #address-cells = <1>; |
634 | #size-cells = <1>; | |
635 | reg = <0x80030000 0x10000>; | |
636 | ||
637 | gpsrtc@1000 { | |
638 | compatible = "sirf,prima2-gpsrtc"; | |
639 | reg = <0x1000 0x1000>; | |
640 | interrupts = <55 56 57>; | |
641 | }; | |
642 | ||
643 | sysrtc@2000 { | |
644 | compatible = "sirf,prima2-sysrtc"; | |
645 | reg = <0x2000 0x1000>; | |
646 | interrupts = <52 53 54>; | |
647 | }; | |
648 | ||
649 | pwrc@3000 { | |
650 | compatible = "sirf,prima2-pwrc"; | |
651 | reg = <0x3000 0x1000>; | |
652 | interrupts = <32>; | |
653 | }; | |
654 | }; | |
655 | ||
656 | uus-iobg { | |
657 | compatible = "simple-bus"; | |
658 | #address-cells = <1>; | |
659 | #size-cells = <1>; | |
660 | ranges = <0xb8000000 0xb8000000 0x40000>; | |
661 | ||
662 | usb0: usb@b00e0000 { | |
663 | compatible = "chipidea,ci13611a-prima2"; | |
664 | reg = <0xb8000000 0x10000>; | |
665 | interrupts = <10>; | |
eb8b8f2e | 666 | clocks = <&clks 40>; |
02c981c0 BD |
667 | }; |
668 | ||
669 | usb1: usb@b00f0000 { | |
670 | compatible = "chipidea,ci13611a-prima2"; | |
671 | reg = <0xb8010000 0x10000>; | |
672 | interrupts = <11>; | |
eb8b8f2e | 673 | clocks = <&clks 41>; |
02c981c0 BD |
674 | }; |
675 | ||
676 | sata@b00f0000 { | |
677 | compatible = "synopsys,dwc-ahsata"; | |
678 | reg = <0xb8020000 0x10000>; | |
679 | interrupts = <37>; | |
680 | }; | |
681 | ||
682 | security@b00f0000 { | |
683 | compatible = "sirf,prima2-security"; | |
684 | reg = <0xb8030000 0x10000>; | |
685 | interrupts = <42>; | |
eb8b8f2e | 686 | clocks = <&clks 7>; |
02c981c0 BD |
687 | }; |
688 | }; | |
689 | }; | |
690 | }; |