[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};

			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};

			i2c3_pins: i2c3 {
				mux {
					pins = "gpio8", "gpio9";
					function = "gsbi3";
				};
			};

			uart_pins: uart_pins {
				mux {
					pins = "gpio14", "gpio15", "gpio16", "gpio17";
					function = "gsbi6";
				};
			};
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			i2c3: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
			};
		};

		gsbi6: gsbi@16500000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <6>;
			reg = <0x16500000 0x03>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x100>,
				      <0x16500000 0x03>;
				interrupts = <0 156 0x0>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio";
					reg = <0x150>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;

					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1	5	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce	6	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	7	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	9	/ {
	10	model = "Qualcomm APQ8064";
	11	compatible = "qcom,apq8064";
	12	interrupt-parent = <&intc>;
	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	compatible = "qcom,krait";
	20	enable-method = "qcom,kpss-acc-v1";
	21	device_type = "cpu";
	22	reg = <0>;
	23	next-level-cache = <&L2>;
	24	qcom,acc = <&acc0>;
	25	qcom,saw = <&saw0>;
06c49f2b	26	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	27	};
	28
	29	cpu@1 {
	30	compatible = "qcom,krait";
	31	enable-method = "qcom,kpss-acc-v1";
	32	device_type = "cpu";
	33	reg = <1>;
	34	next-level-cache = <&L2>;
	35	qcom,acc = <&acc1>;
	36	qcom,saw = <&saw1>;
06c49f2b	37	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	38	};
	39
	40	cpu@2 {
	41	compatible = "qcom,krait";
	42	enable-method = "qcom,kpss-acc-v1";
	43	device_type = "cpu";
	44	reg = <2>;
	45	next-level-cache = <&L2>;
	46	qcom,acc = <&acc2>;
	47	qcom,saw = <&saw2>;
06c49f2b	48	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	49	};
	50
	51	cpu@3 {
	52	compatible = "qcom,krait";
	53	enable-method = "qcom,kpss-acc-v1";
	54	device_type = "cpu";
	55	reg = <3>;
	56	next-level-cache = <&L2>;
	57	qcom,acc = <&acc3>;
	58	qcom,saw = <&saw3>;
06c49f2b	59	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	60	};
	61
	62	L2: l2-cache {
	63	compatible = "cache";
	64	cache-level = <2>;
	65	};
06c49f2b LI	66
	67	idle-states {
	68	CPU_SPC: spc {
	69	compatible = "qcom,idle-state-spc",
	70	"arm,idle-state";
	71	entry-latency-us = <400>;
	72	exit-latency-us = <900>;
	73	min-residency-us = <3000>;
	74	};
	75	};
f335b8af KG	76	};
	77
	78	cpu-pmu {
	79	compatible = "qcom,krait-pmu";
	80	interrupts = <1 10 0x304>;
	81	};
	82
	83	soc: soc {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87	compatible = "simple-bus";
	88
8b8936fc PG	89	tlmm_pinmux: pinctrl@800000 {
	90	compatible = "qcom,apq8064-pinctrl";
	91	reg = <0x800000 0x4000>;
	92
	93	gpio-controller;
	94	#gpio-cells = <2>;
	95	interrupt-controller;
	96	#interrupt-cells = <2>;
	97	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	98
	99	pinctrl-names = "default";
	100	pinctrl-0 = <&ps_hold>;
	101
0be5fef1 SK	102	sdc4_gpios: sdc4-gpios {
	103	pios {
	104	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	105	function = "sdc4";
	106	};
	107	};
	108
cd6dd11a PG	109	ps_hold: ps_hold {
	110	mux {
	111	pins = "gpio78";
	112	function = "ps_hold";
	113	};
	114	};
bc0d3076 SK	115
	116	i2c1_pins: i2c1 {
	117	mux {
	118	pins = "gpio20", "gpio21";
	119	function = "gsbi1";
	120	};
	121	};
3f62b46b SK	122
	123	i2c3_pins: i2c3 {
	124	mux {
	125	pins = "gpio8", "gpio9";
	126	function = "gsbi3";
	127	};
	128	};
86e252a4 PG	129
	130	uart_pins: uart_pins {
	131	mux {
	132	pins = "gpio14", "gpio15", "gpio16", "gpio17";
	133	function = "gsbi6";
	134	};
	135	};
8b8936fc PG	136	};
8b8936fc PG	137
f335b8af KG	138	intc: interrupt-controller@2000000 {
	139	compatible = "qcom,msm-qgic2";
	140	interrupt-controller;
	141	#interrupt-cells = <3>;
	142	reg = <0x02000000 0x1000>,
	143	<0x02002000 0x1000>;
	144	};
	145
	146	timer@200a000 {
	147	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	148	interrupts = <1 1 0x301>,
	149	<1 2 0x301>,
	150	<1 3 0x301>;
	151	reg = <0x0200a000 0x100>;
	152	clock-frequency = <27000000>,
	153	<32768>;
	154	cpu-offset = <0x80000>;
	155	};
	156
	157	acc0: clock-controller@2088000 {
	158	compatible = "qcom,kpss-acc-v1";
	159	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	160	};
	161
	162	acc1: clock-controller@2098000 {
	163	compatible = "qcom,kpss-acc-v1";
	164	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	165	};
	166
	167	acc2: clock-controller@20a8000 {
	168	compatible = "qcom,kpss-acc-v1";
	169	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	170	};
	171
	172	acc3: clock-controller@20b8000 {
	173	compatible = "qcom,kpss-acc-v1";
	174	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	175	};
	176
9fc23ce3 LI	177	saw0: power-controller@2089000 {
9fc23ce3 LI	178	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	179	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	180	regulator;
	181	};
	182
9fc23ce3 LI	183	saw1: power-controller@2099000 {
9fc23ce3 LI	184	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	185	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	186	regulator;
	187	};
	188
9fc23ce3 LI	189	saw2: power-controller@20a9000 {
9fc23ce3 LI	190	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	191	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	192	regulator;
	193	};
	194
9fc23ce3 LI	195	saw3: power-controller@20b9000 {
9fc23ce3 LI	196	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	197	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	198	regulator;
	199	};
	200
8c3166f5	201	gsbi1: gsbi@12440000 {
	202	status = "disabled";
	203	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	204	cell-index = <1>;
8c3166f5	205	reg = <0x12440000 0x100>;
	206	clocks = <&gcc GSBI1_H_CLK>;
	207	clock-names = "iface";
	208	#address-cells = <1>;
	209	#size-cells = <1>;
	210	ranges;
	211
4105d9d6 AG	212	syscon-tcsr = <&tcsr>;
4105d9d6 AG	213
8c3166f5	214	i2c1: i2c@12460000 {
	215	compatible = "qcom,i2c-qup-v1.1.1";
	216	reg = <0x12460000 0x1000>;
	217	interrupts = <0 194 IRQ_TYPE_NONE>;
	218	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	219	clock-names = "core", "iface";
	220	#address-cells = <1>;
	221	#size-cells = <0>;
	222	};
	223	};
	224
	225	gsbi2: gsbi@12480000 {
	226	status = "disabled";
	227	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	228	cell-index = <2>;
8c3166f5	229	reg = <0x12480000 0x100>;
	230	clocks = <&gcc GSBI2_H_CLK>;
	231	clock-names = "iface";
	232	#address-cells = <1>;
	233	#size-cells = <1>;
	234	ranges;
	235
4105d9d6 AG	236	syscon-tcsr = <&tcsr>;
4105d9d6 AG	237
8c3166f5	238	i2c2: i2c@124a0000 {
	239	compatible = "qcom,i2c-qup-v1.1.1";
	240	reg = <0x124a0000 0x1000>;
	241	interrupts = <0 196 IRQ_TYPE_NONE>;
	242	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	243	clock-names = "core", "iface";
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246	};
	247	};
	248
3f62b46b SK	249	gsbi3: gsbi@16200000 {
	250	status = "disabled";
	251	compatible = "qcom,gsbi-v1.0.0";
504155ca	252	cell-index = <3>;
3f62b46b SK	253	reg = <0x16200000 0x100>;
	254	clocks = <&gcc GSBI3_H_CLK>;
	255	clock-names = "iface";
	256	#address-cells = <1>;
	257	#size-cells = <1>;
	258	ranges;
3f62b46b SK	259	i2c3: i2c@16280000 {
	260	compatible = "qcom,i2c-qup-v1.1.1";
	261	reg = <0x16280000 0x1000>;
	262	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	263	clocks = <&gcc GSBI3_QUP_CLK>,
	264	<&gcc GSBI3_H_CLK>;
	265	clock-names = "core", "iface";
	266	};
	267	};
	268
86e252a4 PG	269	gsbi6: gsbi@16500000 {
	270	status = "disabled";
	271	compatible = "qcom,gsbi-v1.0.0";
	272	cell-index = <6>;
	273	reg = <0x16500000 0x03>;
	274	clocks = <&gcc GSBI6_H_CLK>;
	275	clock-names = "iface";
	276	#address-cells = <1>;
	277	#size-cells = <1>;
	278	ranges;
	279
	280	gsbi6_serial: serial@16540000 {
	281	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	282	reg = <0x16540000 0x100>,
	283	<0x16500000 0x03>;
	284	interrupts = <0 156 0x0>;
	285	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	286	clock-names = "core", "iface";
	287	status = "disabled";
	288	};
	289	};
	290
f335b8af KG	291	gsbi7: gsbi@16600000 {
	292	status = "disabled";
	293	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	294	cell-index = <7>;
f335b8af KG	295	reg = <0x16600000 0x100>;
	296	clocks = <&gcc GSBI7_H_CLK>;
	297	clock-names = "iface";
	298	#address-cells = <1>;
	299	#size-cells = <1>;
	300	ranges;
4105d9d6 AG	301	syscon-tcsr = <&tcsr>;
4105d9d6 AG	302
d5d4654e	303	gsbi7_serial: serial@16640000 {
f335b8af KG	304	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	305	reg = <0x16640000 0x1000>,
	306	<0x16600000 0x1000>;
	307	interrupts = <0 158 0x0>;
	308	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	309	clock-names = "core", "iface";
	310	status = "disabled";
	311	};
	312	};
	313
	314	qcom,ssbi@500000 {
	315	compatible = "qcom,ssbi";
	316	reg = <0x00500000 0x1000>;
	317	qcom,controller-type = "pmic-arbiter";
874443fe SK	318
	319	pmicintc: pmic@0 {
	320	compatible = "qcom,pm8921";
	321	interrupt-parent = <&tlmm_pinmux>;
	322	interrupts = <74 8>;
	323	#interrupt-cells = <2>;
	324	interrupt-controller;
	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327
	328	pm8921_gpio: gpio@150 {
	329
	330	compatible = "qcom,pm8921-gpio";
	331	reg = <0x150>;
	332	interrupts = <192 1>, <193 1>, <194 1>,
	333	<195 1>, <196 1>, <197 1>,
	334	<198 1>, <199 1>, <200 1>,
	335	<201 1>, <202 1>, <203 1>,
	336	<204 1>, <205 1>, <206 1>,
	337	<207 1>, <208 1>, <209 1>,
	338	<210 1>, <211 1>, <212 1>,
	339	<213 1>, <214 1>, <215 1>,
	340	<216 1>, <217 1>, <218 1>,
	341	<219 1>, <220 1>, <221 1>,
	342	<222 1>, <223 1>, <224 1>,
	343	<225 1>, <226 1>, <227 1>,
	344	<228 1>, <229 1>, <230 1>,
	345	<231 1>, <232 1>, <233 1>,
	346	<234 1>, <235 1>;
	347
	348	gpio-controller;
	349	#gpio-cells = <2>;
	350
	351	};
bce36046 SK	352
	353	pm8921_mpps: mpps@50 {
	354	compatible = "qcom,pm8921-mpp";
	355	reg = <0x50>;
	356	gpio-controller;
	357	#gpio-cells = <2>;
	358	interrupts =
	359	<128 1>, <129 1>, <130 1>, <131 1>,
	360	<132 1>, <133 1>, <134 1>, <135 1>,
	361	<136 1>, <137 1>, <138 1>, <139 1>;
	362	};
	363
874443fe	364	};
f335b8af KG	365	};
	366
	367	gcc: clock-controller@900000 {
	368	compatible = "qcom,gcc-apq8064";
	369	reg = <0x00900000 0x4000>;
	370	#clock-cells = <1>;
	371	#reset-cells = <1>;
	372	};
3fe5e3ce	373
1e1177bf KG	374	lcc: clock-controller@28000000 {
	375	compatible = "qcom,lcc-apq8064";
	376	reg = <0x28000000 0x1000>;
	377	#clock-cells = <1>;
	378	#reset-cells = <1>;
	379	};
	380
3fe5e3ce SB	381	mmcc: clock-controller@4000000 {
	382	compatible = "qcom,mmcc-apq8064";
	383	reg = <0x4000000 0x1000>;
	384	#clock-cells = <1>;
	385	#reset-cells = <1>;
	386	};
045644ff	387
dc2f8152 SK	388	l2cc: clock-controller@2011000 {
	389	compatible = "syscon";
	390	reg = <0x2011000 0x1000>;
	391	};
	392
	393	rpm@108000 {
	394	compatible = "qcom,rpm-apq8064";
	395	reg = <0x108000 0x1000>;
	396	qcom,ipc = <&l2cc 0x8 2>;
	397
	398	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	399	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	400	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	401	interrupt-names = "ack", "err", "wakeup";
	402
	403	regulators {
	404	compatible = "qcom,rpm-pm8921-regulators";
	405
	406	pm8921_hdmi_switch: hdmi-switch {
	407	bias-pull-down;
	408	};
	409	};
	410	};
	411
ea986611 SK	412	usb1_phy: phy@12500000 {
	413	compatible = "qcom,usb-otg-ci";
	414	reg = <0x12500000 0x400>;
	415	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	416	status = "disabled";
	417	dr_mode = "host";
	418
	419	clocks = <&gcc USB_HS1_XCVR_CLK>,
	420	<&gcc USB_HS1_H_CLK>;
	421	clock-names = "core", "iface";
	422
	423	resets = <&gcc USB_HS1_RESET>;
	424	reset-names = "link";
	425	};
	426
223280b1 SK	427	usb3_phy: phy@12520000 {
	428	compatible = "qcom,usb-otg-ci";
	429	reg = <0x12520000 0x400>;
	430	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	431	status = "disabled";
	432	dr_mode = "host";
	433
	434	clocks = <&gcc USB_HS3_XCVR_CLK>,
	435	<&gcc USB_HS3_H_CLK>;
	436	clock-names = "core", "iface";
	437
	438	resets = <&gcc USB_HS3_RESET>;
	439	reset-names = "link";
	440	};
	441
	442	usb4_phy: phy@12530000 {
	443	compatible = "qcom,usb-otg-ci";
	444	reg = <0x12530000 0x400>;
	445	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	446	status = "disabled";
	447	dr_mode = "host";
	448
	449	clocks = <&gcc USB_HS4_XCVR_CLK>,
	450	<&gcc USB_HS4_H_CLK>;
	451	clock-names = "core", "iface";
	452
	453	resets = <&gcc USB_HS4_RESET>;
	454	reset-names = "link";
	455	};
	456
ea986611 SK	457	gadget1: gadget@12500000 {
	458	compatible = "qcom,ci-hdrc";
	459	reg = <0x12500000 0x400>;
	460	status = "disabled";
	461	dr_mode = "peripheral";
	462	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	463	usb-phy = <&usb1_phy>;
	464	};
	465
	466	usb1: usb@12500000 {
	467	compatible = "qcom,ehci-host";
	468	reg = <0x12500000 0x400>;
	469	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	470	status = "disabled";
	471	usb-phy = <&usb1_phy>;
	472	};
	473
223280b1 SK	474	usb3: usb@12520000 {
	475	compatible = "qcom,ehci-host";
	476	reg = <0x12520000 0x400>;
	477	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	478	status = "disabled";
	479	usb-phy = <&usb3_phy>;
	480	};
	481
	482	usb4: usb@12530000 {
	483	compatible = "qcom,ehci-host";
	484	reg = <0x12530000 0x400>;
	485	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	486	status = "disabled";
	487	usb-phy = <&usb4_phy>;
	488	};
	489
e629335f SK	490	sata_phy0: phy@1b400000 {
	491	compatible = "qcom,apq8064-sata-phy";
	492	status = "disabled";
	493	reg = <0x1b400000 0x200>;
	494	reg-names = "phy_mem";
	495	clocks = <&gcc SATA_PHY_CFG_CLK>;
	496	clock-names = "cfg";
	497	#phy-cells = <0>;
	498	};
	499
	500	sata0: sata@29000000 {
	501	compatible = "generic-ahci";
	502	status = "disabled";
	503	reg = <0x29000000 0x180>;
	504	interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
	505
	506	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	507	<&gcc SATA_H_CLK>,
	508	<&gcc SATA_A_CLK>,
	509	<&gcc SATA_RXOOB_CLK>,
	510	<&gcc SATA_PMALIVE_CLK>;
	511	clock-names = "slave_iface",
	512	"iface",
	513	"bus",
	514	"rxoob",
	515	"core_pmalive";
	516
	517	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	518	<&gcc SATA_PMALIVE_CLK>;
	519	assigned-clock-rates = <100000000>, <100000000>;
	520
	521	phys = <&sata_phy0>;
	522	phy-names = "sata-phy";
	523	};
	524
045644ff	525	/* Temporary fixed regulator */
edb81ca3 SK	526	sdcc1bam:dma@12402000{
	527	compatible = "qcom,bam-v1.3.0";
	528	reg = <0x12402000 0x8000>;
	529	interrupts = <0 98 0>;
	530	clocks = <&gcc SDC1_H_CLK>;
	531	clock-names = "bam_clk";
	532	#dma-cells = <1>;
	533	qcom,ee = <0>;
	534	};
	535
	536	sdcc3bam:dma@12182000{
	537	compatible = "qcom,bam-v1.3.0";
	538	reg = <0x12182000 0x8000>;
	539	interrupts = <0 96 0>;
	540	clocks = <&gcc SDC3_H_CLK>;
	541	clock-names = "bam_clk";
	542	#dma-cells = <1>;
	543	qcom,ee = <0>;
	544	};
	545
0be5fef1 SK	546	sdcc4bam:dma@121c2000{
	547	compatible = "qcom,bam-v1.3.0";
	548	reg = <0x121c2000 0x8000>;
	549	interrupts = <0 95 0>;
	550	clocks = <&gcc SDC4_H_CLK>;
	551	clock-names = "bam_clk";
	552	#dma-cells = <1>;
	553	qcom,ee = <0>;
	554	};
	555
045644ff SK	556	amba {
	557	compatible = "arm,amba-bus";
	558	#address-cells = <1>;
	559	#size-cells = <1>;
	560	ranges;
	561	sdcc1: sdcc@12400000 {
	562	status = "disabled";
	563	compatible = "arm,pl18x", "arm,primecell";
	564	arm,primecell-periphid = <0x00051180>;
	565	reg = <0x12400000 0x2000>;
	566	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	567	interrupt-names = "cmd_irq";
	568	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	569	clock-names = "mclk", "apb_pclk";
	570	bus-width = <8>;
	571	max-frequency = <96000000>;
	572	non-removable;
	573	cap-sd-highspeed;
	574	cap-mmc-highspeed;
edb81ca3 SK	575	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	576	dma-names = "tx", "rx";
045644ff SK	577	};
	578
	579	sdcc3: sdcc@12180000 {
	580	compatible = "arm,pl18x", "arm,primecell";
	581	arm,primecell-periphid = <0x00051180>;
	582	status = "disabled";
	583	reg = <0x12180000 0x2000>;
	584	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	585	interrupt-names = "cmd_irq";
	586	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	587	clock-names = "mclk", "apb_pclk";
	588	bus-width = <4>;
	589	cap-sd-highspeed;
	590	cap-mmc-highspeed;
	591	max-frequency = <192000000>;
	592	no-1-8-v;
edb81ca3 SK	593	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	594	dma-names = "tx", "rx";
045644ff	595	};
0be5fef1 SK	596
	597	sdcc4: sdcc@121c0000 {
	598	compatible = "arm,pl18x", "arm,primecell";
	599	arm,primecell-periphid = <0x00051180>;
	600	status = "disabled";
	601	reg = <0x121c0000 0x2000>;
	602	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	603	interrupt-names = "cmd_irq";
	604	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	605	clock-names = "mclk", "apb_pclk";
	606	bus-width = <4>;
	607	cap-sd-highspeed;
	608	cap-mmc-highspeed;
	609	max-frequency = <48000000>;
0be5fef1 SK	610	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	611	dma-names = "tx", "rx";
	612	pinctrl-names = "default";
	613	pinctrl-0 = <&sdc4_gpios>;
	614	};
045644ff	615	};
4105d9d6 AG	616
	617	tcsr: syscon@1a400000 {
	618	compatible = "qcom,tcsr-apq8064", "syscon";
	619	reg = <0x1a400000 0x100>;
	620	};
f335b8af KG	621	};
f335b8af KG	622	};