Commit | Line | Data |
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f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
3fe5e3ce | 5 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
f335b8af | 6 | #include <dt-bindings/soc/qcom,gsbi.h> |
8b8936fc | 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
f335b8af KG |
8 | |
9 | / { | |
10 | model = "Qualcomm APQ8064"; | |
11 | compatible = "qcom,apq8064"; | |
12 | interrupt-parent = <&intc>; | |
13 | ||
14 | cpus { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <0>; | |
17 | ||
18 | cpu@0 { | |
19 | compatible = "qcom,krait"; | |
20 | enable-method = "qcom,kpss-acc-v1"; | |
21 | device_type = "cpu"; | |
22 | reg = <0>; | |
23 | next-level-cache = <&L2>; | |
24 | qcom,acc = <&acc0>; | |
25 | qcom,saw = <&saw0>; | |
26 | }; | |
27 | ||
28 | cpu@1 { | |
29 | compatible = "qcom,krait"; | |
30 | enable-method = "qcom,kpss-acc-v1"; | |
31 | device_type = "cpu"; | |
32 | reg = <1>; | |
33 | next-level-cache = <&L2>; | |
34 | qcom,acc = <&acc1>; | |
35 | qcom,saw = <&saw1>; | |
36 | }; | |
37 | ||
38 | cpu@2 { | |
39 | compatible = "qcom,krait"; | |
40 | enable-method = "qcom,kpss-acc-v1"; | |
41 | device_type = "cpu"; | |
42 | reg = <2>; | |
43 | next-level-cache = <&L2>; | |
44 | qcom,acc = <&acc2>; | |
45 | qcom,saw = <&saw2>; | |
46 | }; | |
47 | ||
48 | cpu@3 { | |
49 | compatible = "qcom,krait"; | |
50 | enable-method = "qcom,kpss-acc-v1"; | |
51 | device_type = "cpu"; | |
52 | reg = <3>; | |
53 | next-level-cache = <&L2>; | |
54 | qcom,acc = <&acc3>; | |
55 | qcom,saw = <&saw3>; | |
56 | }; | |
57 | ||
58 | L2: l2-cache { | |
59 | compatible = "cache"; | |
60 | cache-level = <2>; | |
61 | }; | |
62 | }; | |
63 | ||
64 | cpu-pmu { | |
65 | compatible = "qcom,krait-pmu"; | |
66 | interrupts = <1 10 0x304>; | |
67 | }; | |
68 | ||
69 | soc: soc { | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | ranges; | |
73 | compatible = "simple-bus"; | |
74 | ||
8b8936fc PG |
75 | tlmm_pinmux: pinctrl@800000 { |
76 | compatible = "qcom,apq8064-pinctrl"; | |
77 | reg = <0x800000 0x4000>; | |
78 | ||
79 | gpio-controller; | |
80 | #gpio-cells = <2>; | |
81 | interrupt-controller; | |
82 | #interrupt-cells = <2>; | |
83 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
cd6dd11a PG |
84 | |
85 | pinctrl-names = "default"; | |
86 | pinctrl-0 = <&ps_hold>; | |
87 | ||
88 | ps_hold: ps_hold { | |
89 | mux { | |
90 | pins = "gpio78"; | |
91 | function = "ps_hold"; | |
92 | }; | |
93 | }; | |
8b8936fc PG |
94 | }; |
95 | ||
f335b8af KG |
96 | intc: interrupt-controller@2000000 { |
97 | compatible = "qcom,msm-qgic2"; | |
98 | interrupt-controller; | |
99 | #interrupt-cells = <3>; | |
100 | reg = <0x02000000 0x1000>, | |
101 | <0x02002000 0x1000>; | |
102 | }; | |
103 | ||
104 | timer@200a000 { | |
105 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
106 | interrupts = <1 1 0x301>, | |
107 | <1 2 0x301>, | |
108 | <1 3 0x301>; | |
109 | reg = <0x0200a000 0x100>; | |
110 | clock-frequency = <27000000>, | |
111 | <32768>; | |
112 | cpu-offset = <0x80000>; | |
113 | }; | |
114 | ||
115 | acc0: clock-controller@2088000 { | |
116 | compatible = "qcom,kpss-acc-v1"; | |
117 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
118 | }; | |
119 | ||
120 | acc1: clock-controller@2098000 { | |
121 | compatible = "qcom,kpss-acc-v1"; | |
122 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
123 | }; | |
124 | ||
125 | acc2: clock-controller@20a8000 { | |
126 | compatible = "qcom,kpss-acc-v1"; | |
127 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
128 | }; | |
129 | ||
130 | acc3: clock-controller@20b8000 { | |
131 | compatible = "qcom,kpss-acc-v1"; | |
132 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
133 | }; | |
134 | ||
135 | saw0: regulator@2089000 { | |
136 | compatible = "qcom,saw2"; | |
137 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | |
138 | regulator; | |
139 | }; | |
140 | ||
141 | saw1: regulator@2099000 { | |
142 | compatible = "qcom,saw2"; | |
143 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | |
144 | regulator; | |
145 | }; | |
146 | ||
147 | saw2: regulator@20a9000 { | |
148 | compatible = "qcom,saw2"; | |
149 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; | |
150 | regulator; | |
151 | }; | |
152 | ||
153 | saw3: regulator@20b9000 { | |
154 | compatible = "qcom,saw2"; | |
155 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; | |
156 | regulator; | |
157 | }; | |
158 | ||
159 | gsbi7: gsbi@16600000 { | |
160 | status = "disabled"; | |
161 | compatible = "qcom,gsbi-v1.0.0"; | |
162 | reg = <0x16600000 0x100>; | |
163 | clocks = <&gcc GSBI7_H_CLK>; | |
164 | clock-names = "iface"; | |
165 | #address-cells = <1>; | |
166 | #size-cells = <1>; | |
167 | ranges; | |
168 | ||
169 | serial@16640000 { | |
170 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
171 | reg = <0x16640000 0x1000>, | |
172 | <0x16600000 0x1000>; | |
173 | interrupts = <0 158 0x0>; | |
174 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
175 | clock-names = "core", "iface"; | |
176 | status = "disabled"; | |
177 | }; | |
178 | }; | |
179 | ||
180 | qcom,ssbi@500000 { | |
181 | compatible = "qcom,ssbi"; | |
182 | reg = <0x00500000 0x1000>; | |
183 | qcom,controller-type = "pmic-arbiter"; | |
184 | }; | |
185 | ||
186 | gcc: clock-controller@900000 { | |
187 | compatible = "qcom,gcc-apq8064"; | |
188 | reg = <0x00900000 0x4000>; | |
189 | #clock-cells = <1>; | |
190 | #reset-cells = <1>; | |
191 | }; | |
3fe5e3ce SB |
192 | |
193 | mmcc: clock-controller@4000000 { | |
194 | compatible = "qcom,mmcc-apq8064"; | |
195 | reg = <0x4000000 0x1000>; | |
196 | #clock-cells = <1>; | |
197 | #reset-cells = <1>; | |
198 | }; | |
045644ff SK |
199 | |
200 | /* Temporary fixed regulator */ | |
201 | vsdcc_fixed: vsdcc-regulator { | |
202 | compatible = "regulator-fixed"; | |
203 | regulator-name = "SDCC Power"; | |
204 | regulator-min-microvolt = <2700000>; | |
205 | regulator-max-microvolt = <2700000>; | |
206 | regulator-always-on; | |
207 | }; | |
208 | ||
209 | amba { | |
210 | compatible = "arm,amba-bus"; | |
211 | #address-cells = <1>; | |
212 | #size-cells = <1>; | |
213 | ranges; | |
214 | sdcc1: sdcc@12400000 { | |
215 | status = "disabled"; | |
216 | compatible = "arm,pl18x", "arm,primecell"; | |
217 | arm,primecell-periphid = <0x00051180>; | |
218 | reg = <0x12400000 0x2000>; | |
219 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
220 | interrupt-names = "cmd_irq"; | |
221 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
222 | clock-names = "mclk", "apb_pclk"; | |
223 | bus-width = <8>; | |
224 | max-frequency = <96000000>; | |
225 | non-removable; | |
226 | cap-sd-highspeed; | |
227 | cap-mmc-highspeed; | |
228 | vmmc-supply = <&vsdcc_fixed>; | |
229 | }; | |
230 | ||
231 | sdcc3: sdcc@12180000 { | |
232 | compatible = "arm,pl18x", "arm,primecell"; | |
233 | arm,primecell-periphid = <0x00051180>; | |
234 | status = "disabled"; | |
235 | reg = <0x12180000 0x2000>; | |
236 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
237 | interrupt-names = "cmd_irq"; | |
238 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
239 | clock-names = "mclk", "apb_pclk"; | |
240 | bus-width = <4>; | |
241 | cap-sd-highspeed; | |
242 | cap-mmc-highspeed; | |
243 | max-frequency = <192000000>; | |
244 | no-1-8-v; | |
245 | vmmc-supply = <&vsdcc_fixed>; | |
246 | }; | |
247 | }; | |
f335b8af KG |
248 | }; |
249 | }; |