[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};

			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};

			i2c3_pins: i2c3 {
				mux {
					pins = "gpio8", "gpio9";
					function = "gsbi3";
				};
			};
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			i2c3: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio";
					reg = <0x150>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;

					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};

		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				vmmc-supply = <&vsdcc_fixed>;
				vqmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1	5	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce	6	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	7	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	9	/ {
	10	model = "Qualcomm APQ8064";
	11	compatible = "qcom,apq8064";
	12	interrupt-parent = <&intc>;
	13
	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
	17
	18	cpu@0 {
	19	compatible = "qcom,krait";
	20	enable-method = "qcom,kpss-acc-v1";
	21	device_type = "cpu";
	22	reg = <0>;
	23	next-level-cache = <&L2>;
	24	qcom,acc = <&acc0>;
	25	qcom,saw = <&saw0>;
06c49f2b	26	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	27	};
	28
	29	cpu@1 {
	30	compatible = "qcom,krait";
	31	enable-method = "qcom,kpss-acc-v1";
	32	device_type = "cpu";
	33	reg = <1>;
	34	next-level-cache = <&L2>;
	35	qcom,acc = <&acc1>;
	36	qcom,saw = <&saw1>;
06c49f2b	37	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	38	};
	39
	40	cpu@2 {
	41	compatible = "qcom,krait";
	42	enable-method = "qcom,kpss-acc-v1";
	43	device_type = "cpu";
	44	reg = <2>;
	45	next-level-cache = <&L2>;
	46	qcom,acc = <&acc2>;
	47	qcom,saw = <&saw2>;
06c49f2b	48	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	49	};
	50
	51	cpu@3 {
	52	compatible = "qcom,krait";
	53	enable-method = "qcom,kpss-acc-v1";
	54	device_type = "cpu";
	55	reg = <3>;
	56	next-level-cache = <&L2>;
	57	qcom,acc = <&acc3>;
	58	qcom,saw = <&saw3>;
06c49f2b	59	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	60	};
	61
	62	L2: l2-cache {
	63	compatible = "cache";
	64	cache-level = <2>;
	65	};
06c49f2b LI	66
	67	idle-states {
	68	CPU_SPC: spc {
	69	compatible = "qcom,idle-state-spc",
	70	"arm,idle-state";
	71	entry-latency-us = <400>;
	72	exit-latency-us = <900>;
	73	min-residency-us = <3000>;
	74	};
	75	};
f335b8af KG	76	};
	77
	78	cpu-pmu {
	79	compatible = "qcom,krait-pmu";
	80	interrupts = <1 10 0x304>;
	81	};
	82
	83	soc: soc {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges;
	87	compatible = "simple-bus";
	88
8b8936fc PG	89	tlmm_pinmux: pinctrl@800000 {
	90	compatible = "qcom,apq8064-pinctrl";
	91	reg = <0x800000 0x4000>;
	92
	93	gpio-controller;
	94	#gpio-cells = <2>;
	95	interrupt-controller;
	96	#interrupt-cells = <2>;
	97	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	98
	99	pinctrl-names = "default";
	100	pinctrl-0 = <&ps_hold>;
	101
0be5fef1 SK	102	sdc4_gpios: sdc4-gpios {
	103	pios {
	104	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	105	function = "sdc4";
	106	};
	107	};
	108
cd6dd11a PG	109	ps_hold: ps_hold {
	110	mux {
	111	pins = "gpio78";
	112	function = "ps_hold";
	113	};
	114	};
bc0d3076 SK	115
	116	i2c1_pins: i2c1 {
	117	mux {
	118	pins = "gpio20", "gpio21";
	119	function = "gsbi1";
	120	};
	121	};
3f62b46b SK	122
	123	i2c3_pins: i2c3 {
	124	mux {
	125	pins = "gpio8", "gpio9";
	126	function = "gsbi3";
	127	};
	128	};
8b8936fc PG	129	};
8b8936fc PG	130
f335b8af KG	131	intc: interrupt-controller@2000000 {
	132	compatible = "qcom,msm-qgic2";
	133	interrupt-controller;
	134	#interrupt-cells = <3>;
	135	reg = <0x02000000 0x1000>,
	136	<0x02002000 0x1000>;
	137	};
	138
	139	timer@200a000 {
	140	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	141	interrupts = <1 1 0x301>,
	142	<1 2 0x301>,
	143	<1 3 0x301>;
	144	reg = <0x0200a000 0x100>;
	145	clock-frequency = <27000000>,
	146	<32768>;
	147	cpu-offset = <0x80000>;
	148	};
	149
	150	acc0: clock-controller@2088000 {
	151	compatible = "qcom,kpss-acc-v1";
	152	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	153	};
	154
	155	acc1: clock-controller@2098000 {
	156	compatible = "qcom,kpss-acc-v1";
	157	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	158	};
	159
	160	acc2: clock-controller@20a8000 {
	161	compatible = "qcom,kpss-acc-v1";
	162	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	163	};
	164
	165	acc3: clock-controller@20b8000 {
	166	compatible = "qcom,kpss-acc-v1";
	167	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	168	};
	169
9fc23ce3 LI	170	saw0: power-controller@2089000 {
9fc23ce3 LI	171	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	172	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	173	regulator;
	174	};
	175
9fc23ce3 LI	176	saw1: power-controller@2099000 {
9fc23ce3 LI	177	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	178	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	179	regulator;
	180	};
	181
9fc23ce3 LI	182	saw2: power-controller@20a9000 {
9fc23ce3 LI	183	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	184	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	185	regulator;
	186	};
	187
9fc23ce3 LI	188	saw3: power-controller@20b9000 {
9fc23ce3 LI	189	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	190	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	191	regulator;
	192	};
	193
8c3166f5	194	gsbi1: gsbi@12440000 {
	195	status = "disabled";
	196	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	197	cell-index = <1>;
8c3166f5	198	reg = <0x12440000 0x100>;
	199	clocks = <&gcc GSBI1_H_CLK>;
	200	clock-names = "iface";
	201	#address-cells = <1>;
	202	#size-cells = <1>;
	203	ranges;
	204
4105d9d6 AG	205	syscon-tcsr = <&tcsr>;
4105d9d6 AG	206
8c3166f5	207	i2c1: i2c@12460000 {
	208	compatible = "qcom,i2c-qup-v1.1.1";
	209	reg = <0x12460000 0x1000>;
	210	interrupts = <0 194 IRQ_TYPE_NONE>;
	211	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	212	clock-names = "core", "iface";
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215	};
	216	};
	217
	218	gsbi2: gsbi@12480000 {
	219	status = "disabled";
	220	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	221	cell-index = <2>;
8c3166f5	222	reg = <0x12480000 0x100>;
	223	clocks = <&gcc GSBI2_H_CLK>;
	224	clock-names = "iface";
	225	#address-cells = <1>;
	226	#size-cells = <1>;
	227	ranges;
	228
4105d9d6 AG	229	syscon-tcsr = <&tcsr>;
4105d9d6 AG	230
8c3166f5	231	i2c2: i2c@124a0000 {
	232	compatible = "qcom,i2c-qup-v1.1.1";
	233	reg = <0x124a0000 0x1000>;
	234	interrupts = <0 196 IRQ_TYPE_NONE>;
	235	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	236	clock-names = "core", "iface";
	237	#address-cells = <1>;
	238	#size-cells = <0>;
	239	};
	240	};
	241
3f62b46b SK	242	gsbi3: gsbi@16200000 {
	243	status = "disabled";
	244	compatible = "qcom,gsbi-v1.0.0";
	245	reg = <0x16200000 0x100>;
	246	clocks = <&gcc GSBI3_H_CLK>;
	247	clock-names = "iface";
	248	#address-cells = <1>;
	249	#size-cells = <1>;
	250	ranges;
	251
	252	i2c3: i2c@16280000 {
	253	compatible = "qcom,i2c-qup-v1.1.1";
	254	reg = <0x16280000 0x1000>;
	255	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	256	clocks = <&gcc GSBI3_QUP_CLK>,
	257	<&gcc GSBI3_H_CLK>;
	258	clock-names = "core", "iface";
	259	};
	260	};
	261
f335b8af KG	262	gsbi7: gsbi@16600000 {
	263	status = "disabled";
	264	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	265	cell-index = <7>;
f335b8af KG	266	reg = <0x16600000 0x100>;
	267	clocks = <&gcc GSBI7_H_CLK>;
	268	clock-names = "iface";
	269	#address-cells = <1>;
	270	#size-cells = <1>;
	271	ranges;
4105d9d6 AG	272	syscon-tcsr = <&tcsr>;
4105d9d6 AG	273
d5d4654e	274	gsbi7_serial: serial@16640000 {
f335b8af KG	275	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	276	reg = <0x16640000 0x1000>,
	277	<0x16600000 0x1000>;
	278	interrupts = <0 158 0x0>;
	279	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	280	clock-names = "core", "iface";
	281	status = "disabled";
	282	};
	283	};
	284
	285	qcom,ssbi@500000 {
	286	compatible = "qcom,ssbi";
	287	reg = <0x00500000 0x1000>;
	288	qcom,controller-type = "pmic-arbiter";
874443fe SK	289
	290	pmicintc: pmic@0 {
	291	compatible = "qcom,pm8921";
	292	interrupt-parent = <&tlmm_pinmux>;
	293	interrupts = <74 8>;
	294	#interrupt-cells = <2>;
	295	interrupt-controller;
	296	#address-cells = <1>;
	297	#size-cells = <0>;
	298
	299	pm8921_gpio: gpio@150 {
	300
	301	compatible = "qcom,pm8921-gpio";
	302	reg = <0x150>;
	303	interrupts = <192 1>, <193 1>, <194 1>,
	304	<195 1>, <196 1>, <197 1>,
	305	<198 1>, <199 1>, <200 1>,
	306	<201 1>, <202 1>, <203 1>,
	307	<204 1>, <205 1>, <206 1>,
	308	<207 1>, <208 1>, <209 1>,
	309	<210 1>, <211 1>, <212 1>,
	310	<213 1>, <214 1>, <215 1>,
	311	<216 1>, <217 1>, <218 1>,
	312	<219 1>, <220 1>, <221 1>,
	313	<222 1>, <223 1>, <224 1>,
	314	<225 1>, <226 1>, <227 1>,
	315	<228 1>, <229 1>, <230 1>,
	316	<231 1>, <232 1>, <233 1>,
	317	<234 1>, <235 1>;
	318
	319	gpio-controller;
	320	#gpio-cells = <2>;
	321
	322	};
bce36046 SK	323
	324	pm8921_mpps: mpps@50 {
	325	compatible = "qcom,pm8921-mpp";
	326	reg = <0x50>;
	327	gpio-controller;
	328	#gpio-cells = <2>;
	329	interrupts =
	330	<128 1>, <129 1>, <130 1>, <131 1>,
	331	<132 1>, <133 1>, <134 1>, <135 1>,
	332	<136 1>, <137 1>, <138 1>, <139 1>;
	333	};
	334
874443fe	335	};
f335b8af KG	336	};
	337
	338	gcc: clock-controller@900000 {
	339	compatible = "qcom,gcc-apq8064";
	340	reg = <0x00900000 0x4000>;
	341	#clock-cells = <1>;
	342	#reset-cells = <1>;
	343	};
3fe5e3ce	344
1e1177bf KG	345	lcc: clock-controller@28000000 {
	346	compatible = "qcom,lcc-apq8064";
	347	reg = <0x28000000 0x1000>;
	348	#clock-cells = <1>;
	349	#reset-cells = <1>;
	350	};
	351
3fe5e3ce SB	352	mmcc: clock-controller@4000000 {
	353	compatible = "qcom,mmcc-apq8064";
	354	reg = <0x4000000 0x1000>;
	355	#clock-cells = <1>;
	356	#reset-cells = <1>;
	357	};
045644ff	358
dc2f8152 SK	359	l2cc: clock-controller@2011000 {
	360	compatible = "syscon";
	361	reg = <0x2011000 0x1000>;
	362	};
	363
	364	rpm@108000 {
	365	compatible = "qcom,rpm-apq8064";
	366	reg = <0x108000 0x1000>;
	367	qcom,ipc = <&l2cc 0x8 2>;
	368
	369	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	370	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	371	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	372	interrupt-names = "ack", "err", "wakeup";
	373
	374	regulators {
	375	compatible = "qcom,rpm-pm8921-regulators";
	376
	377	pm8921_hdmi_switch: hdmi-switch {
	378	bias-pull-down;
	379	};
	380	};
	381	};
	382
ea986611 SK	383	usb1_phy: phy@12500000 {
	384	compatible = "qcom,usb-otg-ci";
	385	reg = <0x12500000 0x400>;
	386	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	387	status = "disabled";
	388	dr_mode = "host";
	389
	390	clocks = <&gcc USB_HS1_XCVR_CLK>,
	391	<&gcc USB_HS1_H_CLK>;
	392	clock-names = "core", "iface";
	393
	394	resets = <&gcc USB_HS1_RESET>;
	395	reset-names = "link";
	396	};
	397
223280b1 SK	398	usb3_phy: phy@12520000 {
	399	compatible = "qcom,usb-otg-ci";
	400	reg = <0x12520000 0x400>;
	401	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	402	status = "disabled";
	403	dr_mode = "host";
	404
	405	clocks = <&gcc USB_HS3_XCVR_CLK>,
	406	<&gcc USB_HS3_H_CLK>;
	407	clock-names = "core", "iface";
	408
	409	resets = <&gcc USB_HS3_RESET>;
	410	reset-names = "link";
	411	};
	412
	413	usb4_phy: phy@12530000 {
	414	compatible = "qcom,usb-otg-ci";
	415	reg = <0x12530000 0x400>;
	416	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	417	status = "disabled";
	418	dr_mode = "host";
	419
	420	clocks = <&gcc USB_HS4_XCVR_CLK>,
	421	<&gcc USB_HS4_H_CLK>;
	422	clock-names = "core", "iface";
	423
	424	resets = <&gcc USB_HS4_RESET>;
	425	reset-names = "link";
	426	};
	427
ea986611 SK	428	gadget1: gadget@12500000 {
	429	compatible = "qcom,ci-hdrc";
	430	reg = <0x12500000 0x400>;
	431	status = "disabled";
	432	dr_mode = "peripheral";
	433	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	434	usb-phy = <&usb1_phy>;
	435	};
	436
	437	usb1: usb@12500000 {
	438	compatible = "qcom,ehci-host";
	439	reg = <0x12500000 0x400>;
	440	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	441	status = "disabled";
	442	usb-phy = <&usb1_phy>;
	443	};
	444
223280b1 SK	445	usb3: usb@12520000 {
	446	compatible = "qcom,ehci-host";
	447	reg = <0x12520000 0x400>;
	448	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	449	status = "disabled";
	450	usb-phy = <&usb3_phy>;
	451	};
	452
	453	usb4: usb@12530000 {
	454	compatible = "qcom,ehci-host";
	455	reg = <0x12530000 0x400>;
	456	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	457	status = "disabled";
	458	usb-phy = <&usb4_phy>;
	459	};
	460
e629335f SK	461	sata_phy0: phy@1b400000 {
	462	compatible = "qcom,apq8064-sata-phy";
	463	status = "disabled";
	464	reg = <0x1b400000 0x200>;
	465	reg-names = "phy_mem";
	466	clocks = <&gcc SATA_PHY_CFG_CLK>;
	467	clock-names = "cfg";
	468	#phy-cells = <0>;
	469	};
	470
	471	sata0: sata@29000000 {
	472	compatible = "generic-ahci";
	473	status = "disabled";
	474	reg = <0x29000000 0x180>;
	475	interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
	476
	477	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	478	<&gcc SATA_H_CLK>,
	479	<&gcc SATA_A_CLK>,
	480	<&gcc SATA_RXOOB_CLK>,
	481	<&gcc SATA_PMALIVE_CLK>;
	482	clock-names = "slave_iface",
	483	"iface",
	484	"bus",
	485	"rxoob",
	486	"core_pmalive";
	487
	488	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	489	<&gcc SATA_PMALIVE_CLK>;
	490	assigned-clock-rates = <100000000>, <100000000>;
	491
	492	phys = <&sata_phy0>;
	493	phy-names = "sata-phy";
	494	};
	495
045644ff SK	496	/* Temporary fixed regulator */
	497	vsdcc_fixed: vsdcc-regulator {
	498	compatible = "regulator-fixed";
	499	regulator-name = "SDCC Power";
	500	regulator-min-microvolt = <2700000>;
	501	regulator-max-microvolt = <2700000>;
	502	regulator-always-on;
	503	};
	504
edb81ca3 SK	505	sdcc1bam:dma@12402000{
	506	compatible = "qcom,bam-v1.3.0";
	507	reg = <0x12402000 0x8000>;
	508	interrupts = <0 98 0>;
	509	clocks = <&gcc SDC1_H_CLK>;
	510	clock-names = "bam_clk";
	511	#dma-cells = <1>;
	512	qcom,ee = <0>;
	513	};
	514
	515	sdcc3bam:dma@12182000{
	516	compatible = "qcom,bam-v1.3.0";
	517	reg = <0x12182000 0x8000>;
	518	interrupts = <0 96 0>;
	519	clocks = <&gcc SDC3_H_CLK>;
	520	clock-names = "bam_clk";
	521	#dma-cells = <1>;
	522	qcom,ee = <0>;
	523	};
	524
0be5fef1 SK	525	sdcc4bam:dma@121c2000{
	526	compatible = "qcom,bam-v1.3.0";
	527	reg = <0x121c2000 0x8000>;
	528	interrupts = <0 95 0>;
	529	clocks = <&gcc SDC4_H_CLK>;
	530	clock-names = "bam_clk";
	531	#dma-cells = <1>;
	532	qcom,ee = <0>;
	533	};
	534
045644ff SK	535	amba {
	536	compatible = "arm,amba-bus";
	537	#address-cells = <1>;
	538	#size-cells = <1>;
	539	ranges;
	540	sdcc1: sdcc@12400000 {
	541	status = "disabled";
	542	compatible = "arm,pl18x", "arm,primecell";
	543	arm,primecell-periphid = <0x00051180>;
	544	reg = <0x12400000 0x2000>;
	545	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	546	interrupt-names = "cmd_irq";
	547	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	548	clock-names = "mclk", "apb_pclk";
	549	bus-width = <8>;
	550	max-frequency = <96000000>;
	551	non-removable;
	552	cap-sd-highspeed;
	553	cap-mmc-highspeed;
	554	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	555	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	556	dma-names = "tx", "rx";
045644ff SK	557	};
	558
	559	sdcc3: sdcc@12180000 {
	560	compatible = "arm,pl18x", "arm,primecell";
	561	arm,primecell-periphid = <0x00051180>;
	562	status = "disabled";
	563	reg = <0x12180000 0x2000>;
	564	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	565	interrupt-names = "cmd_irq";
	566	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	567	clock-names = "mclk", "apb_pclk";
	568	bus-width = <4>;
	569	cap-sd-highspeed;
	570	cap-mmc-highspeed;
	571	max-frequency = <192000000>;
	572	no-1-8-v;
	573	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	574	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	575	dma-names = "tx", "rx";
045644ff	576	};
0be5fef1 SK	577
	578	sdcc4: sdcc@121c0000 {
	579	compatible = "arm,pl18x", "arm,primecell";
	580	arm,primecell-periphid = <0x00051180>;
	581	status = "disabled";
	582	reg = <0x121c0000 0x2000>;
	583	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	584	interrupt-names = "cmd_irq";
	585	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	586	clock-names = "mclk", "apb_pclk";
	587	bus-width = <4>;
	588	cap-sd-highspeed;
	589	cap-mmc-highspeed;
	590	max-frequency = <48000000>;
	591	vmmc-supply = <&vsdcc_fixed>;
	592	vqmmc-supply = <&vsdcc_fixed>;
	593	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	594	dma-names = "tx", "rx";
	595	pinctrl-names = "default";
	596	pinctrl-0 = <&sdc4_gpios>;
	597	};
045644ff	598	};
4105d9d6 AG	599
	600	tcsr: syscon@1a400000 {
	601	compatible = "qcom,tcsr-apq8064", "syscon";
	602	reg = <0x1a400000 0x100>;
	603	};
f335b8af KG	604	};
f335b8af KG	605	};