Commit | Line | Data |
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f335b8af KG |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
223280b1 | 5 | #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
3fe5e3ce | 6 | #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
f335b8af | 7 | #include <dt-bindings/soc/qcom,gsbi.h> |
8b8936fc | 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
f335b8af KG |
9 | / { |
10 | model = "Qualcomm APQ8064"; | |
11 | compatible = "qcom,apq8064"; | |
12 | interrupt-parent = <&intc>; | |
13 | ||
24a9baf9 BA |
14 | reserved-memory { |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ranges; | |
18 | ||
19 | smem_region: smem@80000000 { | |
20 | reg = <0x80000000 0x200000>; | |
21 | no-map; | |
22 | }; | |
23 | }; | |
24 | ||
f335b8af KG |
25 | cpus { |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | ||
29 | cpu@0 { | |
30 | compatible = "qcom,krait"; | |
31 | enable-method = "qcom,kpss-acc-v1"; | |
32 | device_type = "cpu"; | |
33 | reg = <0>; | |
34 | next-level-cache = <&L2>; | |
35 | qcom,acc = <&acc0>; | |
36 | qcom,saw = <&saw0>; | |
06c49f2b | 37 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
38 | }; |
39 | ||
40 | cpu@1 { | |
41 | compatible = "qcom,krait"; | |
42 | enable-method = "qcom,kpss-acc-v1"; | |
43 | device_type = "cpu"; | |
44 | reg = <1>; | |
45 | next-level-cache = <&L2>; | |
46 | qcom,acc = <&acc1>; | |
47 | qcom,saw = <&saw1>; | |
06c49f2b | 48 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
49 | }; |
50 | ||
51 | cpu@2 { | |
52 | compatible = "qcom,krait"; | |
53 | enable-method = "qcom,kpss-acc-v1"; | |
54 | device_type = "cpu"; | |
55 | reg = <2>; | |
56 | next-level-cache = <&L2>; | |
57 | qcom,acc = <&acc2>; | |
58 | qcom,saw = <&saw2>; | |
06c49f2b | 59 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
60 | }; |
61 | ||
62 | cpu@3 { | |
63 | compatible = "qcom,krait"; | |
64 | enable-method = "qcom,kpss-acc-v1"; | |
65 | device_type = "cpu"; | |
66 | reg = <3>; | |
67 | next-level-cache = <&L2>; | |
68 | qcom,acc = <&acc3>; | |
69 | qcom,saw = <&saw3>; | |
06c49f2b | 70 | cpu-idle-states = <&CPU_SPC>; |
f335b8af KG |
71 | }; |
72 | ||
73 | L2: l2-cache { | |
74 | compatible = "cache"; | |
75 | cache-level = <2>; | |
76 | }; | |
06c49f2b LI |
77 | |
78 | idle-states { | |
79 | CPU_SPC: spc { | |
80 | compatible = "qcom,idle-state-spc", | |
81 | "arm,idle-state"; | |
82 | entry-latency-us = <400>; | |
83 | exit-latency-us = <900>; | |
84 | min-residency-us = <3000>; | |
85 | }; | |
86 | }; | |
f335b8af KG |
87 | }; |
88 | ||
89 | cpu-pmu { | |
90 | compatible = "qcom,krait-pmu"; | |
91 | interrupts = <1 10 0x304>; | |
92 | }; | |
93 | ||
aa269127 GD |
94 | clocks { |
95 | cxo_board { | |
96 | compatible = "fixed-clock"; | |
97 | #clock-cells = <0>; | |
98 | clock-frequency = <19200000>; | |
99 | }; | |
100 | ||
101 | pxo_board { | |
102 | compatible = "fixed-clock"; | |
103 | #clock-cells = <0>; | |
104 | clock-frequency = <27000000>; | |
105 | }; | |
106 | ||
107 | sleep_clk { | |
108 | compatible = "fixed-clock"; | |
109 | #clock-cells = <0>; | |
110 | clock-frequency = <32768>; | |
111 | }; | |
112 | }; | |
113 | ||
24a9baf9 BA |
114 | sfpb_mutex: hwmutex { |
115 | compatible = "qcom,sfpb-mutex"; | |
116 | syscon = <&sfpb_wrapper_mutex 0x604 0x4>; | |
117 | #hwlock-cells = <1>; | |
118 | }; | |
119 | ||
120 | smem { | |
121 | compatible = "qcom,smem"; | |
122 | memory-region = <&smem_region>; | |
123 | ||
124 | hwlocks = <&sfpb_mutex 3>; | |
125 | }; | |
126 | ||
2afc5287 BA |
127 | smd { |
128 | compatible = "qcom,smd"; | |
129 | ||
130 | modem@0 { | |
131 | interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; | |
132 | ||
133 | qcom,ipc = <&l2cc 8 3>; | |
134 | qcom,smd-edge = <0>; | |
135 | ||
136 | status = "disabled"; | |
137 | }; | |
138 | ||
139 | q6@1 { | |
140 | interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; | |
141 | ||
142 | qcom,ipc = <&l2cc 8 15>; | |
143 | qcom,smd-edge = <1>; | |
144 | ||
145 | status = "disabled"; | |
146 | }; | |
147 | ||
148 | dsps@3 { | |
149 | interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; | |
150 | ||
151 | qcom,ipc = <&sps_sic_non_secure 0x4080 0>; | |
152 | qcom,smd-edge = <3>; | |
153 | ||
154 | status = "disabled"; | |
155 | }; | |
156 | ||
157 | riva@6 { | |
158 | interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; | |
159 | ||
160 | qcom,ipc = <&l2cc 8 25>; | |
161 | qcom,smd-edge = <6>; | |
162 | ||
163 | status = "disabled"; | |
164 | }; | |
165 | }; | |
166 | ||
b4d4582f BA |
167 | smsm { |
168 | compatible = "qcom,smsm"; | |
169 | ||
170 | #address-cells = <1>; | |
171 | #size-cells = <0>; | |
172 | ||
173 | qcom,ipc-1 = <&l2cc 8 4>; | |
174 | qcom,ipc-2 = <&l2cc 8 14>; | |
175 | qcom,ipc-3 = <&l2cc 8 23>; | |
176 | qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; | |
177 | ||
178 | apps_smsm: apps@0 { | |
179 | reg = <0>; | |
30f1e2dd | 180 | #qcom,smem-state-cells = <1>; |
b4d4582f BA |
181 | }; |
182 | ||
183 | modem_smsm: modem@1 { | |
184 | reg = <1>; | |
185 | interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; | |
186 | ||
187 | interrupt-controller; | |
188 | #interrupt-cells = <2>; | |
189 | }; | |
190 | ||
191 | q6_smsm: q6@2 { | |
192 | reg = <2>; | |
193 | interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; | |
194 | ||
195 | interrupt-controller; | |
196 | #interrupt-cells = <2>; | |
197 | }; | |
198 | ||
199 | wcnss_smsm: wcnss@3 { | |
200 | reg = <3>; | |
201 | interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; | |
202 | ||
203 | interrupt-controller; | |
204 | #interrupt-cells = <2>; | |
205 | }; | |
206 | ||
207 | dsps_smsm: dsps@4 { | |
208 | reg = <4>; | |
209 | interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; | |
210 | ||
211 | interrupt-controller; | |
212 | #interrupt-cells = <2>; | |
213 | }; | |
214 | }; | |
215 | ||
9e5d41d4 AG |
216 | firmware { |
217 | scm { | |
218 | compatible = "qcom,scm-apq8064"; | |
219 | }; | |
220 | }; | |
221 | ||
f335b8af KG |
222 | soc: soc { |
223 | #address-cells = <1>; | |
224 | #size-cells = <1>; | |
225 | ranges; | |
226 | compatible = "simple-bus"; | |
227 | ||
8b8936fc PG |
228 | tlmm_pinmux: pinctrl@800000 { |
229 | compatible = "qcom,apq8064-pinctrl"; | |
230 | reg = <0x800000 0x4000>; | |
231 | ||
232 | gpio-controller; | |
233 | #gpio-cells = <2>; | |
234 | interrupt-controller; | |
235 | #interrupt-cells = <2>; | |
236 | interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; | |
cd6dd11a PG |
237 | |
238 | pinctrl-names = "default"; | |
239 | pinctrl-0 = <&ps_hold>; | |
8b8936fc PG |
240 | }; |
241 | ||
24a9baf9 BA |
242 | sfpb_wrapper_mutex: syscon@1200000 { |
243 | compatible = "syscon"; | |
244 | reg = <0x01200000 0x8000>; | |
245 | }; | |
246 | ||
f335b8af KG |
247 | intc: interrupt-controller@2000000 { |
248 | compatible = "qcom,msm-qgic2"; | |
249 | interrupt-controller; | |
250 | #interrupt-cells = <3>; | |
251 | reg = <0x02000000 0x1000>, | |
252 | <0x02002000 0x1000>; | |
253 | }; | |
254 | ||
255 | timer@200a000 { | |
6e062696 MM |
256 | compatible = "qcom,kpss-timer", |
257 | "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; | |
f335b8af KG |
258 | interrupts = <1 1 0x301>, |
259 | <1 2 0x301>, | |
260 | <1 3 0x301>; | |
261 | reg = <0x0200a000 0x100>; | |
262 | clock-frequency = <27000000>, | |
263 | <32768>; | |
264 | cpu-offset = <0x80000>; | |
265 | }; | |
266 | ||
267 | acc0: clock-controller@2088000 { | |
268 | compatible = "qcom,kpss-acc-v1"; | |
269 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
270 | }; | |
271 | ||
272 | acc1: clock-controller@2098000 { | |
273 | compatible = "qcom,kpss-acc-v1"; | |
274 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
275 | }; | |
276 | ||
277 | acc2: clock-controller@20a8000 { | |
278 | compatible = "qcom,kpss-acc-v1"; | |
279 | reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; | |
280 | }; | |
281 | ||
282 | acc3: clock-controller@20b8000 { | |
283 | compatible = "qcom,kpss-acc-v1"; | |
284 | reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; | |
285 | }; | |
286 | ||
9fc23ce3 LI |
287 | saw0: power-controller@2089000 { |
288 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
289 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
290 | regulator; | |
291 | }; | |
292 | ||
9fc23ce3 LI |
293 | saw1: power-controller@2099000 { |
294 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
295 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
296 | regulator; | |
297 | }; | |
298 | ||
9fc23ce3 LI |
299 | saw2: power-controller@20a9000 { |
300 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
301 | reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; |
302 | regulator; | |
303 | }; | |
304 | ||
9fc23ce3 LI |
305 | saw3: power-controller@20b9000 { |
306 | compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; | |
f335b8af KG |
307 | reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; |
308 | regulator; | |
309 | }; | |
310 | ||
b9e4c5e6 BA |
311 | sps_sic_non_secure: sps-sic-non-secure@12100000 { |
312 | compatible = "syscon"; | |
313 | reg = <0x12100000 0x10000>; | |
314 | }; | |
315 | ||
8c3166f5 | 316 | gsbi1: gsbi@12440000 { |
317 | status = "disabled"; | |
318 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 319 | cell-index = <1>; |
8c3166f5 | 320 | reg = <0x12440000 0x100>; |
321 | clocks = <&gcc GSBI1_H_CLK>; | |
322 | clock-names = "iface"; | |
323 | #address-cells = <1>; | |
324 | #size-cells = <1>; | |
325 | ranges; | |
326 | ||
4105d9d6 AG |
327 | syscon-tcsr = <&tcsr>; |
328 | ||
12861674 SK |
329 | gsbi1_serial: serial@12450000 { |
330 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
331 | reg = <0x12450000 0x100>, | |
332 | <0x12400000 0x03>; | |
333 | interrupts = <0 193 0x0>; | |
334 | clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; | |
335 | clock-names = "core", "iface"; | |
336 | status = "disabled"; | |
337 | }; | |
338 | ||
e07214db | 339 | gsbi1_i2c: i2c@12460000 { |
8c3166f5 | 340 | compatible = "qcom,i2c-qup-v1.1.1"; |
67b5ad57 SK |
341 | pinctrl-0 = <&i2c1_pins>; |
342 | pinctrl-1 = <&i2c1_pins_sleep>; | |
64b22b25 | 343 | pinctrl-names = "default", "sleep"; |
8c3166f5 | 344 | reg = <0x12460000 0x1000>; |
345 | interrupts = <0 194 IRQ_TYPE_NONE>; | |
346 | clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; | |
347 | clock-names = "core", "iface"; | |
348 | #address-cells = <1>; | |
349 | #size-cells = <0>; | |
350 | }; | |
b2dc04c5 | 351 | |
8c3166f5 | 352 | }; |
353 | ||
354 | gsbi2: gsbi@12480000 { | |
355 | status = "disabled"; | |
356 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 357 | cell-index = <2>; |
8c3166f5 | 358 | reg = <0x12480000 0x100>; |
359 | clocks = <&gcc GSBI2_H_CLK>; | |
360 | clock-names = "iface"; | |
361 | #address-cells = <1>; | |
362 | #size-cells = <1>; | |
363 | ranges; | |
364 | ||
4105d9d6 AG |
365 | syscon-tcsr = <&tcsr>; |
366 | ||
e07214db | 367 | gsbi2_i2c: i2c@124a0000 { |
8c3166f5 | 368 | compatible = "qcom,i2c-qup-v1.1.1"; |
369 | reg = <0x124a0000 0x1000>; | |
67b5ad57 SK |
370 | pinctrl-0 = <&i2c2_pins>; |
371 | pinctrl-1 = <&i2c2_pins_sleep>; | |
7788d439 | 372 | pinctrl-names = "default", "sleep"; |
8c3166f5 | 373 | interrupts = <0 196 IRQ_TYPE_NONE>; |
374 | clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; | |
375 | clock-names = "core", "iface"; | |
376 | #address-cells = <1>; | |
377 | #size-cells = <0>; | |
378 | }; | |
379 | }; | |
380 | ||
3f62b46b SK |
381 | gsbi3: gsbi@16200000 { |
382 | status = "disabled"; | |
383 | compatible = "qcom,gsbi-v1.0.0"; | |
504155ca | 384 | cell-index = <3>; |
3f62b46b SK |
385 | reg = <0x16200000 0x100>; |
386 | clocks = <&gcc GSBI3_H_CLK>; | |
387 | clock-names = "iface"; | |
388 | #address-cells = <1>; | |
389 | #size-cells = <1>; | |
390 | ranges; | |
e07214db | 391 | gsbi3_i2c: i2c@16280000 { |
3f62b46b | 392 | compatible = "qcom,i2c-qup-v1.1.1"; |
67b5ad57 SK |
393 | pinctrl-0 = <&i2c3_pins>; |
394 | pinctrl-1 = <&i2c3_pins_sleep>; | |
64b22b25 | 395 | pinctrl-names = "default", "sleep"; |
3f62b46b SK |
396 | reg = <0x16280000 0x1000>; |
397 | interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; | |
398 | clocks = <&gcc GSBI3_QUP_CLK>, | |
399 | <&gcc GSBI3_H_CLK>; | |
400 | clock-names = "core", "iface"; | |
5d31f606 JS |
401 | #address-cells = <1>; |
402 | #size-cells = <0>; | |
1099b26e BA |
403 | }; |
404 | }; | |
405 | ||
2a5cbc15 SK |
406 | gsbi4: gsbi@16300000 { |
407 | status = "disabled"; | |
408 | compatible = "qcom,gsbi-v1.0.0"; | |
409 | cell-index = <4>; | |
410 | reg = <0x16300000 0x03>; | |
411 | clocks = <&gcc GSBI4_H_CLK>; | |
412 | clock-names = "iface"; | |
413 | #address-cells = <1>; | |
414 | #size-cells = <1>; | |
415 | ranges; | |
416 | ||
417 | gsbi4_i2c: i2c@16380000 { | |
418 | compatible = "qcom,i2c-qup-v1.1.1"; | |
67b5ad57 SK |
419 | pinctrl-0 = <&i2c4_pins>; |
420 | pinctrl-1 = <&i2c4_pins_sleep>; | |
2a5cbc15 SK |
421 | pinctrl-names = "default", "sleep"; |
422 | reg = <0x16380000 0x1000>; | |
423 | interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; | |
424 | clocks = <&gcc GSBI4_QUP_CLK>, | |
425 | <&gcc GSBI4_H_CLK>; | |
426 | clock-names = "core", "iface"; | |
427 | }; | |
428 | }; | |
429 | ||
1099b26e BA |
430 | gsbi5: gsbi@1a200000 { |
431 | status = "disabled"; | |
432 | compatible = "qcom,gsbi-v1.0.0"; | |
433 | cell-index = <5>; | |
434 | reg = <0x1a200000 0x03>; | |
435 | clocks = <&gcc GSBI5_H_CLK>; | |
436 | clock-names = "iface"; | |
437 | #address-cells = <1>; | |
438 | #size-cells = <1>; | |
439 | ranges; | |
440 | ||
441 | gsbi5_serial: serial@1a240000 { | |
442 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
443 | reg = <0x1a240000 0x100>, | |
444 | <0x1a200000 0x03>; | |
445 | interrupts = <0 154 0x0>; | |
446 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
447 | clock-names = "core", "iface"; | |
448 | status = "disabled"; | |
3f62b46b | 449 | }; |
b2dc04c5 SK |
450 | |
451 | gsbi5_spi: spi@1a280000 { | |
452 | compatible = "qcom,spi-qup-v1.1.1"; | |
453 | reg = <0x1a280000 0x1000>; | |
454 | interrupts = <0 155 0>; | |
67b5ad57 SK |
455 | pinctrl-0 = <&spi5_default>; |
456 | pinctrl-1 = <&spi5_sleep>; | |
b2dc04c5 SK |
457 | pinctrl-names = "default", "sleep"; |
458 | clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; | |
459 | clock-names = "core", "iface"; | |
460 | status = "disabled"; | |
461 | #address-cells = <1>; | |
462 | #size-cells = <0>; | |
463 | }; | |
3f62b46b SK |
464 | }; |
465 | ||
86e252a4 PG |
466 | gsbi6: gsbi@16500000 { |
467 | status = "disabled"; | |
468 | compatible = "qcom,gsbi-v1.0.0"; | |
469 | cell-index = <6>; | |
470 | reg = <0x16500000 0x03>; | |
471 | clocks = <&gcc GSBI6_H_CLK>; | |
472 | clock-names = "iface"; | |
473 | #address-cells = <1>; | |
474 | #size-cells = <1>; | |
475 | ranges; | |
476 | ||
477 | gsbi6_serial: serial@16540000 { | |
478 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
479 | reg = <0x16540000 0x100>, | |
480 | <0x16500000 0x03>; | |
481 | interrupts = <0 156 0x0>; | |
482 | clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; | |
483 | clock-names = "core", "iface"; | |
484 | status = "disabled"; | |
485 | }; | |
806334ed SK |
486 | |
487 | gsbi6_i2c: i2c@16580000 { | |
488 | compatible = "qcom,i2c-qup-v1.1.1"; | |
67b5ad57 SK |
489 | pinctrl-0 = <&i2c6_pins>; |
490 | pinctrl-1 = <&i2c6_pins_sleep>; | |
806334ed SK |
491 | pinctrl-names = "default", "sleep"; |
492 | reg = <0x16580000 0x1000>; | |
493 | interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; | |
494 | clocks = <&gcc GSBI6_QUP_CLK>, | |
495 | <&gcc GSBI6_H_CLK>; | |
496 | clock-names = "core", "iface"; | |
497 | }; | |
86e252a4 PG |
498 | }; |
499 | ||
f335b8af KG |
500 | gsbi7: gsbi@16600000 { |
501 | status = "disabled"; | |
502 | compatible = "qcom,gsbi-v1.0.0"; | |
4105d9d6 | 503 | cell-index = <7>; |
f335b8af KG |
504 | reg = <0x16600000 0x100>; |
505 | clocks = <&gcc GSBI7_H_CLK>; | |
506 | clock-names = "iface"; | |
507 | #address-cells = <1>; | |
508 | #size-cells = <1>; | |
509 | ranges; | |
4105d9d6 AG |
510 | syscon-tcsr = <&tcsr>; |
511 | ||
d5d4654e | 512 | gsbi7_serial: serial@16640000 { |
f335b8af KG |
513 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
514 | reg = <0x16640000 0x1000>, | |
515 | <0x16600000 0x1000>; | |
516 | interrupts = <0 158 0x0>; | |
517 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; | |
518 | clock-names = "core", "iface"; | |
519 | status = "disabled"; | |
520 | }; | |
e4b01fda SK |
521 | |
522 | gsbi7_i2c: i2c@16680000 { | |
523 | compatible = "qcom,i2c-qup-v1.1.1"; | |
524 | pinctrl-0 = <&i2c7_pins>; | |
525 | pinctrl-1 = <&i2c7_pins_sleep>; | |
526 | pinctrl-names = "default", "sleep"; | |
527 | reg = <0x16680000 0x1000>; | |
528 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
529 | clocks = <&gcc GSBI7_QUP_CLK>, | |
530 | <&gcc GSBI7_H_CLK>; | |
531 | clock-names = "core", "iface"; | |
532 | status = "disabled"; | |
533 | }; | |
f335b8af KG |
534 | }; |
535 | ||
6a607e03 JS |
536 | rng@1a500000 { |
537 | compatible = "qcom,prng"; | |
538 | reg = <0x1a500000 0x200>; | |
539 | clocks = <&gcc PRNG_CLK>; | |
540 | clock-names = "core"; | |
541 | }; | |
542 | ||
f335b8af KG |
543 | qcom,ssbi@500000 { |
544 | compatible = "qcom,ssbi"; | |
545 | reg = <0x00500000 0x1000>; | |
546 | qcom,controller-type = "pmic-arbiter"; | |
874443fe SK |
547 | |
548 | pmicintc: pmic@0 { | |
549 | compatible = "qcom,pm8921"; | |
550 | interrupt-parent = <&tlmm_pinmux>; | |
551 | interrupts = <74 8>; | |
552 | #interrupt-cells = <2>; | |
553 | interrupt-controller; | |
554 | #address-cells = <1>; | |
555 | #size-cells = <0>; | |
556 | ||
557 | pm8921_gpio: gpio@150 { | |
558 | ||
2ca9c2a4 SB |
559 | compatible = "qcom,pm8921-gpio", |
560 | "qcom,ssbi-gpio"; | |
874443fe SK |
561 | reg = <0x150>; |
562 | interrupts = <192 1>, <193 1>, <194 1>, | |
563 | <195 1>, <196 1>, <197 1>, | |
564 | <198 1>, <199 1>, <200 1>, | |
565 | <201 1>, <202 1>, <203 1>, | |
566 | <204 1>, <205 1>, <206 1>, | |
567 | <207 1>, <208 1>, <209 1>, | |
568 | <210 1>, <211 1>, <212 1>, | |
569 | <213 1>, <214 1>, <215 1>, | |
570 | <216 1>, <217 1>, <218 1>, | |
571 | <219 1>, <220 1>, <221 1>, | |
572 | <222 1>, <223 1>, <224 1>, | |
573 | <225 1>, <226 1>, <227 1>, | |
574 | <228 1>, <229 1>, <230 1>, | |
575 | <231 1>, <232 1>, <233 1>, | |
576 | <234 1>, <235 1>; | |
577 | ||
578 | gpio-controller; | |
579 | #gpio-cells = <2>; | |
580 | ||
581 | }; | |
bce36046 SK |
582 | |
583 | pm8921_mpps: mpps@50 { | |
2ca9c2a4 SB |
584 | compatible = "qcom,pm8921-mpp", |
585 | "qcom,ssbi-mpp"; | |
bce36046 SK |
586 | reg = <0x50>; |
587 | gpio-controller; | |
588 | #gpio-cells = <2>; | |
589 | interrupts = | |
590 | <128 1>, <129 1>, <130 1>, <131 1>, | |
591 | <132 1>, <133 1>, <134 1>, <135 1>, | |
592 | <136 1>, <137 1>, <138 1>, <139 1>; | |
593 | }; | |
594 | ||
bbf89b96 SK |
595 | rtc@11d { |
596 | compatible = "qcom,pm8921-rtc"; | |
597 | interrupt-parent = <&pmicintc>; | |
598 | interrupts = <39 1>; | |
599 | reg = <0x11d>; | |
600 | allow-set-time; | |
601 | }; | |
602 | ||
3050c5f5 SK |
603 | pwrkey@1c { |
604 | compatible = "qcom,pm8921-pwrkey"; | |
605 | reg = <0x1c>; | |
606 | interrupt-parent = <&pmicintc>; | |
607 | interrupts = <50 1>, <51 1>; | |
608 | debounce = <15625>; | |
609 | pull-up; | |
610 | }; | |
874443fe | 611 | }; |
f335b8af KG |
612 | }; |
613 | ||
614 | gcc: clock-controller@900000 { | |
615 | compatible = "qcom,gcc-apq8064"; | |
616 | reg = <0x00900000 0x4000>; | |
617 | #clock-cells = <1>; | |
618 | #reset-cells = <1>; | |
619 | }; | |
3fe5e3ce | 620 | |
1e1177bf KG |
621 | lcc: clock-controller@28000000 { |
622 | compatible = "qcom,lcc-apq8064"; | |
623 | reg = <0x28000000 0x1000>; | |
624 | #clock-cells = <1>; | |
625 | #reset-cells = <1>; | |
626 | }; | |
627 | ||
3fe5e3ce SB |
628 | mmcc: clock-controller@4000000 { |
629 | compatible = "qcom,mmcc-apq8064"; | |
630 | reg = <0x4000000 0x1000>; | |
631 | #clock-cells = <1>; | |
632 | #reset-cells = <1>; | |
633 | }; | |
045644ff | 634 | |
dc2f8152 SK |
635 | l2cc: clock-controller@2011000 { |
636 | compatible = "syscon"; | |
637 | reg = <0x2011000 0x1000>; | |
638 | }; | |
639 | ||
640 | rpm@108000 { | |
641 | compatible = "qcom,rpm-apq8064"; | |
642 | reg = <0x108000 0x1000>; | |
643 | qcom,ipc = <&l2cc 0x8 2>; | |
644 | ||
645 | interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, | |
646 | <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, | |
647 | <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; | |
648 | interrupt-names = "ack", "err", "wakeup"; | |
649 | ||
aac1b297 GD |
650 | rpmcc: clock-controller { |
651 | compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; | |
652 | #clock-cells = <1>; | |
653 | }; | |
654 | ||
dc2f8152 SK |
655 | regulators { |
656 | compatible = "qcom,rpm-pm8921-regulators"; | |
657 | ||
2bce6e26 BA |
658 | pm8921_s1: s1 {}; |
659 | pm8921_s2: s2 {}; | |
660 | pm8921_s3: s3 {}; | |
661 | pm8921_s4: s4 {}; | |
662 | pm8921_s7: s7 {}; | |
663 | pm8921_s8: s8 {}; | |
664 | ||
665 | pm8921_l1: l1 {}; | |
666 | pm8921_l2: l2 {}; | |
667 | pm8921_l3: l3 {}; | |
668 | pm8921_l4: l4 {}; | |
669 | pm8921_l5: l5 {}; | |
670 | pm8921_l6: l6 {}; | |
671 | pm8921_l7: l7 {}; | |
672 | pm8921_l8: l8 {}; | |
673 | pm8921_l9: l9 {}; | |
674 | pm8921_l10: l10 {}; | |
675 | pm8921_l11: l11 {}; | |
676 | pm8921_l12: l12 {}; | |
677 | pm8921_l14: l14 {}; | |
678 | pm8921_l15: l15 {}; | |
679 | pm8921_l16: l16 {}; | |
680 | pm8921_l17: l17 {}; | |
681 | pm8921_l18: l18 {}; | |
682 | pm8921_l21: l21 {}; | |
683 | pm8921_l22: l22 {}; | |
684 | pm8921_l23: l23 {}; | |
685 | pm8921_l24: l24 {}; | |
686 | pm8921_l25: l25 {}; | |
687 | pm8921_l26: l26 {}; | |
688 | pm8921_l27: l27 {}; | |
689 | pm8921_l28: l28 {}; | |
690 | pm8921_l29: l29 {}; | |
691 | ||
692 | pm8921_lvs1: lvs1 {}; | |
693 | pm8921_lvs2: lvs2 {}; | |
694 | pm8921_lvs3: lvs3 {}; | |
695 | pm8921_lvs4: lvs4 {}; | |
696 | pm8921_lvs5: lvs5 {}; | |
697 | pm8921_lvs6: lvs6 {}; | |
698 | pm8921_lvs7: lvs7 {}; | |
699 | ||
700 | pm8921_usb_switch: usb-switch {}; | |
701 | ||
dc2f8152 SK |
702 | pm8921_hdmi_switch: hdmi-switch { |
703 | bias-pull-down; | |
704 | }; | |
2bce6e26 BA |
705 | |
706 | pm8921_ncp: ncp {}; | |
dc2f8152 SK |
707 | }; |
708 | }; | |
709 | ||
ea986611 SK |
710 | usb1_phy: phy@12500000 { |
711 | compatible = "qcom,usb-otg-ci"; | |
712 | reg = <0x12500000 0x400>; | |
713 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
714 | status = "disabled"; | |
715 | dr_mode = "host"; | |
716 | ||
717 | clocks = <&gcc USB_HS1_XCVR_CLK>, | |
718 | <&gcc USB_HS1_H_CLK>; | |
719 | clock-names = "core", "iface"; | |
720 | ||
721 | resets = <&gcc USB_HS1_RESET>; | |
722 | reset-names = "link"; | |
723 | }; | |
724 | ||
223280b1 SK |
725 | usb3_phy: phy@12520000 { |
726 | compatible = "qcom,usb-otg-ci"; | |
727 | reg = <0x12520000 0x400>; | |
728 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
729 | status = "disabled"; | |
730 | dr_mode = "host"; | |
731 | ||
732 | clocks = <&gcc USB_HS3_XCVR_CLK>, | |
733 | <&gcc USB_HS3_H_CLK>; | |
734 | clock-names = "core", "iface"; | |
735 | ||
736 | resets = <&gcc USB_HS3_RESET>; | |
737 | reset-names = "link"; | |
738 | }; | |
739 | ||
740 | usb4_phy: phy@12530000 { | |
741 | compatible = "qcom,usb-otg-ci"; | |
742 | reg = <0x12530000 0x400>; | |
743 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
744 | status = "disabled"; | |
745 | dr_mode = "host"; | |
746 | ||
747 | clocks = <&gcc USB_HS4_XCVR_CLK>, | |
748 | <&gcc USB_HS4_H_CLK>; | |
749 | clock-names = "core", "iface"; | |
750 | ||
751 | resets = <&gcc USB_HS4_RESET>; | |
752 | reset-names = "link"; | |
753 | }; | |
754 | ||
ea986611 SK |
755 | gadget1: gadget@12500000 { |
756 | compatible = "qcom,ci-hdrc"; | |
757 | reg = <0x12500000 0x400>; | |
758 | status = "disabled"; | |
759 | dr_mode = "peripheral"; | |
760 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
761 | usb-phy = <&usb1_phy>; | |
762 | }; | |
763 | ||
764 | usb1: usb@12500000 { | |
765 | compatible = "qcom,ehci-host"; | |
766 | reg = <0x12500000 0x400>; | |
767 | interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; | |
768 | status = "disabled"; | |
769 | usb-phy = <&usb1_phy>; | |
770 | }; | |
771 | ||
223280b1 SK |
772 | usb3: usb@12520000 { |
773 | compatible = "qcom,ehci-host"; | |
774 | reg = <0x12520000 0x400>; | |
775 | interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; | |
776 | status = "disabled"; | |
777 | usb-phy = <&usb3_phy>; | |
778 | }; | |
779 | ||
780 | usb4: usb@12530000 { | |
781 | compatible = "qcom,ehci-host"; | |
782 | reg = <0x12530000 0x400>; | |
783 | interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; | |
784 | status = "disabled"; | |
785 | usb-phy = <&usb4_phy>; | |
786 | }; | |
787 | ||
e629335f SK |
788 | sata_phy0: phy@1b400000 { |
789 | compatible = "qcom,apq8064-sata-phy"; | |
790 | status = "disabled"; | |
791 | reg = <0x1b400000 0x200>; | |
792 | reg-names = "phy_mem"; | |
793 | clocks = <&gcc SATA_PHY_CFG_CLK>; | |
794 | clock-names = "cfg"; | |
795 | #phy-cells = <0>; | |
796 | }; | |
797 | ||
798 | sata0: sata@29000000 { | |
bb4add2c | 799 | compatible = "qcom,apq8064-ahci", "generic-ahci"; |
e629335f SK |
800 | status = "disabled"; |
801 | reg = <0x29000000 0x180>; | |
802 | interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; | |
803 | ||
804 | clocks = <&gcc SFAB_SATA_S_H_CLK>, | |
805 | <&gcc SATA_H_CLK>, | |
806 | <&gcc SATA_A_CLK>, | |
807 | <&gcc SATA_RXOOB_CLK>, | |
808 | <&gcc SATA_PMALIVE_CLK>; | |
809 | clock-names = "slave_iface", | |
810 | "iface", | |
811 | "bus", | |
812 | "rxoob", | |
813 | "core_pmalive"; | |
814 | ||
815 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, | |
816 | <&gcc SATA_PMALIVE_CLK>; | |
817 | assigned-clock-rates = <100000000>, <100000000>; | |
818 | ||
819 | phys = <&sata_phy0>; | |
820 | phy-names = "sata-phy"; | |
bb4add2c | 821 | ports-implemented = <0x1>; |
e629335f SK |
822 | }; |
823 | ||
045644ff | 824 | /* Temporary fixed regulator */ |
edb81ca3 SK |
825 | sdcc1bam:dma@12402000{ |
826 | compatible = "qcom,bam-v1.3.0"; | |
827 | reg = <0x12402000 0x8000>; | |
828 | interrupts = <0 98 0>; | |
829 | clocks = <&gcc SDC1_H_CLK>; | |
830 | clock-names = "bam_clk"; | |
831 | #dma-cells = <1>; | |
832 | qcom,ee = <0>; | |
833 | }; | |
834 | ||
835 | sdcc3bam:dma@12182000{ | |
836 | compatible = "qcom,bam-v1.3.0"; | |
837 | reg = <0x12182000 0x8000>; | |
838 | interrupts = <0 96 0>; | |
839 | clocks = <&gcc SDC3_H_CLK>; | |
840 | clock-names = "bam_clk"; | |
841 | #dma-cells = <1>; | |
842 | qcom,ee = <0>; | |
843 | }; | |
844 | ||
0be5fef1 SK |
845 | sdcc4bam:dma@121c2000{ |
846 | compatible = "qcom,bam-v1.3.0"; | |
847 | reg = <0x121c2000 0x8000>; | |
848 | interrupts = <0 95 0>; | |
849 | clocks = <&gcc SDC4_H_CLK>; | |
850 | clock-names = "bam_clk"; | |
851 | #dma-cells = <1>; | |
852 | qcom,ee = <0>; | |
853 | }; | |
854 | ||
045644ff | 855 | amba { |
2ef7d5f3 | 856 | compatible = "simple-bus"; |
045644ff SK |
857 | #address-cells = <1>; |
858 | #size-cells = <1>; | |
859 | ranges; | |
860 | sdcc1: sdcc@12400000 { | |
861 | status = "disabled"; | |
862 | compatible = "arm,pl18x", "arm,primecell"; | |
ccd140b5 SK |
863 | pinctrl-names = "default"; |
864 | pinctrl-0 = <&sdcc1_pins>; | |
045644ff SK |
865 | arm,primecell-periphid = <0x00051180>; |
866 | reg = <0x12400000 0x2000>; | |
867 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
868 | interrupt-names = "cmd_irq"; | |
869 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
870 | clock-names = "mclk", "apb_pclk"; | |
871 | bus-width = <8>; | |
872 | max-frequency = <96000000>; | |
873 | non-removable; | |
874 | cap-sd-highspeed; | |
875 | cap-mmc-highspeed; | |
edb81ca3 SK |
876 | dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
877 | dma-names = "tx", "rx"; | |
045644ff SK |
878 | }; |
879 | ||
880 | sdcc3: sdcc@12180000 { | |
881 | compatible = "arm,pl18x", "arm,primecell"; | |
882 | arm,primecell-periphid = <0x00051180>; | |
883 | status = "disabled"; | |
884 | reg = <0x12180000 0x2000>; | |
885 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
886 | interrupt-names = "cmd_irq"; | |
887 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
888 | clock-names = "mclk", "apb_pclk"; | |
889 | bus-width = <4>; | |
890 | cap-sd-highspeed; | |
891 | cap-mmc-highspeed; | |
892 | max-frequency = <192000000>; | |
893 | no-1-8-v; | |
edb81ca3 SK |
894 | dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
895 | dma-names = "tx", "rx"; | |
045644ff | 896 | }; |
0be5fef1 SK |
897 | |
898 | sdcc4: sdcc@121c0000 { | |
899 | compatible = "arm,pl18x", "arm,primecell"; | |
900 | arm,primecell-periphid = <0x00051180>; | |
901 | status = "disabled"; | |
902 | reg = <0x121c0000 0x2000>; | |
903 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
904 | interrupt-names = "cmd_irq"; | |
905 | clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; | |
906 | clock-names = "mclk", "apb_pclk"; | |
907 | bus-width = <4>; | |
908 | cap-sd-highspeed; | |
909 | cap-mmc-highspeed; | |
910 | max-frequency = <48000000>; | |
0be5fef1 SK |
911 | dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; |
912 | dma-names = "tx", "rx"; | |
913 | pinctrl-names = "default"; | |
914 | pinctrl-0 = <&sdc4_gpios>; | |
915 | }; | |
045644ff | 916 | }; |
4105d9d6 AG |
917 | |
918 | tcsr: syscon@1a400000 { | |
919 | compatible = "qcom,tcsr-apq8064", "syscon"; | |
920 | reg = <0x1a400000 0x100>; | |
921 | }; | |
bcc74b09 SV |
922 | |
923 | pcie: pci@1b500000 { | |
924 | compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; | |
925 | reg = <0x1b500000 0x1000 | |
926 | 0x1b502000 0x80 | |
927 | 0x1b600000 0x100 | |
928 | 0x0ff00000 0x100000>; | |
929 | reg-names = "dbi", "elbi", "parf", "config"; | |
930 | device_type = "pci"; | |
931 | linux,pci-domain = <0>; | |
932 | bus-range = <0x00 0xff>; | |
933 | num-lanes = <1>; | |
934 | #address-cells = <3>; | |
935 | #size-cells = <2>; | |
936 | ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ | |
937 | 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ | |
938 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
939 | interrupt-names = "msi"; | |
940 | #interrupt-cells = <1>; | |
941 | interrupt-map-mask = <0 0 0 0x7>; | |
942 | interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
943 | <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
944 | <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
945 | <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
946 | clocks = <&gcc PCIE_A_CLK>, | |
947 | <&gcc PCIE_H_CLK>, | |
948 | <&gcc PCIE_PHY_REF_CLK>; | |
949 | clock-names = "core", "iface", "phy"; | |
950 | resets = <&gcc PCIE_ACLK_RESET>, | |
951 | <&gcc PCIE_HCLK_RESET>, | |
952 | <&gcc PCIE_POR_RESET>, | |
953 | <&gcc PCIE_PCI_RESET>, | |
954 | <&gcc PCIE_PHY_RESET>; | |
955 | reset-names = "axi", "ahb", "por", "pci", "phy"; | |
956 | status = "disabled"; | |
957 | }; | |
f335b8af KG |
958 | }; |
959 | }; | |
a30e78bd | 960 | #include "qcom-apq8064-pins.dtsi" |