[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};

		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				vmmc-supply = <&vsdcc_fixed>;
				vqmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1	5	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce	6	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	7	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	9
	10	/ {
	11	model = "Qualcomm APQ8064";
	12	compatible = "qcom,apq8064";
	13	interrupt-parent = <&intc>;
	14
	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18
	19	cpu@0 {
	20	compatible = "qcom,krait";
	21	enable-method = "qcom,kpss-acc-v1";
	22	device_type = "cpu";
	23	reg = <0>;
	24	next-level-cache = <&L2>;
	25	qcom,acc = <&acc0>;
	26	qcom,saw = <&saw0>;
06c49f2b	27	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	28	};
	29
	30	cpu@1 {
	31	compatible = "qcom,krait";
	32	enable-method = "qcom,kpss-acc-v1";
	33	device_type = "cpu";
	34	reg = <1>;
	35	next-level-cache = <&L2>;
	36	qcom,acc = <&acc1>;
	37	qcom,saw = <&saw1>;
06c49f2b	38	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	39	};
	40
	41	cpu@2 {
	42	compatible = "qcom,krait";
	43	enable-method = "qcom,kpss-acc-v1";
	44	device_type = "cpu";
	45	reg = <2>;
	46	next-level-cache = <&L2>;
	47	qcom,acc = <&acc2>;
	48	qcom,saw = <&saw2>;
06c49f2b	49	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	50	};
	51
	52	cpu@3 {
	53	compatible = "qcom,krait";
	54	enable-method = "qcom,kpss-acc-v1";
	55	device_type = "cpu";
	56	reg = <3>;
	57	next-level-cache = <&L2>;
	58	qcom,acc = <&acc3>;
	59	qcom,saw = <&saw3>;
06c49f2b	60	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	61	};
	62
	63	L2: l2-cache {
	64	compatible = "cache";
	65	cache-level = <2>;
	66	};
06c49f2b LI	67
	68	idle-states {
	69	CPU_SPC: spc {
	70	compatible = "qcom,idle-state-spc",
	71	"arm,idle-state";
	72	entry-latency-us = <400>;
	73	exit-latency-us = <900>;
	74	min-residency-us = <3000>;
	75	};
	76	};
f335b8af KG	77	};
	78
	79	cpu-pmu {
	80	compatible = "qcom,krait-pmu";
	81	interrupts = <1 10 0x304>;
	82	};
	83
	84	soc: soc {
	85	#address-cells = <1>;
	86	#size-cells = <1>;
	87	ranges;
	88	compatible = "simple-bus";
	89
8b8936fc PG	90	tlmm_pinmux: pinctrl@800000 {
	91	compatible = "qcom,apq8064-pinctrl";
	92	reg = <0x800000 0x4000>;
	93
	94	gpio-controller;
	95	#gpio-cells = <2>;
	96	interrupt-controller;
	97	#interrupt-cells = <2>;
	98	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	99
	100	pinctrl-names = "default";
	101	pinctrl-0 = <&ps_hold>;
	102
0be5fef1 SK	103	sdc4_gpios: sdc4-gpios {
	104	pios {
	105	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	106	function = "sdc4";
	107	};
	108	};
	109
cd6dd11a PG	110	ps_hold: ps_hold {
	111	mux {
	112	pins = "gpio78";
	113	function = "ps_hold";
	114	};
	115	};
8b8936fc PG	116	};
8b8936fc PG	117
f335b8af KG	118	intc: interrupt-controller@2000000 {
	119	compatible = "qcom,msm-qgic2";
	120	interrupt-controller;
	121	#interrupt-cells = <3>;
	122	reg = <0x02000000 0x1000>,
	123	<0x02002000 0x1000>;
	124	};
	125
	126	timer@200a000 {
	127	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	128	interrupts = <1 1 0x301>,
	129	<1 2 0x301>,
	130	<1 3 0x301>;
	131	reg = <0x0200a000 0x100>;
	132	clock-frequency = <27000000>,
	133	<32768>;
	134	cpu-offset = <0x80000>;
	135	};
	136
	137	acc0: clock-controller@2088000 {
	138	compatible = "qcom,kpss-acc-v1";
	139	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	140	};
	141
	142	acc1: clock-controller@2098000 {
	143	compatible = "qcom,kpss-acc-v1";
	144	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	145	};
	146
	147	acc2: clock-controller@20a8000 {
	148	compatible = "qcom,kpss-acc-v1";
	149	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	150	};
	151
	152	acc3: clock-controller@20b8000 {
	153	compatible = "qcom,kpss-acc-v1";
	154	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	155	};
	156
9fc23ce3 LI	157	saw0: power-controller@2089000 {
9fc23ce3 LI	158	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	159	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	160	regulator;
	161	};
	162
9fc23ce3 LI	163	saw1: power-controller@2099000 {
9fc23ce3 LI	164	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	165	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	166	regulator;
	167	};
	168
9fc23ce3 LI	169	saw2: power-controller@20a9000 {
9fc23ce3 LI	170	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	171	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	172	regulator;
	173	};
	174
9fc23ce3 LI	175	saw3: power-controller@20b9000 {
9fc23ce3 LI	176	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	177	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	178	regulator;
	179	};
	180
8c3166f5	181	gsbi1: gsbi@12440000 {
	182	status = "disabled";
	183	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	184	cell-index = <1>;
8c3166f5	185	reg = <0x12440000 0x100>;
	186	clocks = <&gcc GSBI1_H_CLK>;
	187	clock-names = "iface";
	188	#address-cells = <1>;
	189	#size-cells = <1>;
	190	ranges;
	191
4105d9d6 AG	192	syscon-tcsr = <&tcsr>;
4105d9d6 AG	193
8c3166f5	194	i2c1: i2c@12460000 {
	195	compatible = "qcom,i2c-qup-v1.1.1";
	196	reg = <0x12460000 0x1000>;
	197	interrupts = <0 194 IRQ_TYPE_NONE>;
	198	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	199	clock-names = "core", "iface";
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202	};
	203	};
	204
	205	gsbi2: gsbi@12480000 {
	206	status = "disabled";
	207	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	208	cell-index = <2>;
8c3166f5	209	reg = <0x12480000 0x100>;
	210	clocks = <&gcc GSBI2_H_CLK>;
	211	clock-names = "iface";
	212	#address-cells = <1>;
	213	#size-cells = <1>;
	214	ranges;
	215
4105d9d6 AG	216	syscon-tcsr = <&tcsr>;
4105d9d6 AG	217
8c3166f5	218	i2c2: i2c@124a0000 {
	219	compatible = "qcom,i2c-qup-v1.1.1";
	220	reg = <0x124a0000 0x1000>;
	221	interrupts = <0 196 IRQ_TYPE_NONE>;
	222	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	223	clock-names = "core", "iface";
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	};
	227	};
	228
f335b8af KG	229	gsbi7: gsbi@16600000 {
	230	status = "disabled";
	231	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	232	cell-index = <7>;
f335b8af KG	233	reg = <0x16600000 0x100>;
	234	clocks = <&gcc GSBI7_H_CLK>;
	235	clock-names = "iface";
	236	#address-cells = <1>;
	237	#size-cells = <1>;
	238	ranges;
4105d9d6 AG	239	syscon-tcsr = <&tcsr>;
4105d9d6 AG	240
d5d4654e	241	gsbi7_serial: serial@16640000 {
f335b8af KG	242	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	243	reg = <0x16640000 0x1000>,
	244	<0x16600000 0x1000>;
	245	interrupts = <0 158 0x0>;
	246	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	247	clock-names = "core", "iface";
	248	status = "disabled";
	249	};
	250	};
	251
	252	qcom,ssbi@500000 {
	253	compatible = "qcom,ssbi";
	254	reg = <0x00500000 0x1000>;
	255	qcom,controller-type = "pmic-arbiter";
	256	};
	257
	258	gcc: clock-controller@900000 {
	259	compatible = "qcom,gcc-apq8064";
	260	reg = <0x00900000 0x4000>;
	261	#clock-cells = <1>;
	262	#reset-cells = <1>;
	263	};
3fe5e3ce	264
1e1177bf KG	265	lcc: clock-controller@28000000 {
	266	compatible = "qcom,lcc-apq8064";
	267	reg = <0x28000000 0x1000>;
	268	#clock-cells = <1>;
	269	#reset-cells = <1>;
	270	};
	271
3fe5e3ce SB	272	mmcc: clock-controller@4000000 {
	273	compatible = "qcom,mmcc-apq8064";
	274	reg = <0x4000000 0x1000>;
	275	#clock-cells = <1>;
	276	#reset-cells = <1>;
	277	};
045644ff	278
dc2f8152 SK	279	l2cc: clock-controller@2011000 {
	280	compatible = "syscon";
	281	reg = <0x2011000 0x1000>;
	282	};
	283
	284	rpm@108000 {
	285	compatible = "qcom,rpm-apq8064";
	286	reg = <0x108000 0x1000>;
	287	qcom,ipc = <&l2cc 0x8 2>;
	288
	289	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	290	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	291	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	292	interrupt-names = "ack", "err", "wakeup";
	293
	294	regulators {
	295	compatible = "qcom,rpm-pm8921-regulators";
	296
	297	pm8921_hdmi_switch: hdmi-switch {
	298	bias-pull-down;
	299	};
	300	};
	301	};
	302
ea986611 SK	303	usb1_phy: phy@12500000 {
	304	compatible = "qcom,usb-otg-ci";
	305	reg = <0x12500000 0x400>;
	306	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	307	status = "disabled";
	308	dr_mode = "host";
	309
	310	clocks = <&gcc USB_HS1_XCVR_CLK>,
	311	<&gcc USB_HS1_H_CLK>;
	312	clock-names = "core", "iface";
	313
	314	resets = <&gcc USB_HS1_RESET>;
	315	reset-names = "link";
	316	};
	317
223280b1 SK	318	usb3_phy: phy@12520000 {
	319	compatible = "qcom,usb-otg-ci";
	320	reg = <0x12520000 0x400>;
	321	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	322	status = "disabled";
	323	dr_mode = "host";
	324
	325	clocks = <&gcc USB_HS3_XCVR_CLK>,
	326	<&gcc USB_HS3_H_CLK>;
	327	clock-names = "core", "iface";
	328
	329	resets = <&gcc USB_HS3_RESET>;
	330	reset-names = "link";
	331	};
	332
	333	usb4_phy: phy@12530000 {
	334	compatible = "qcom,usb-otg-ci";
	335	reg = <0x12530000 0x400>;
	336	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	337	status = "disabled";
	338	dr_mode = "host";
	339
	340	clocks = <&gcc USB_HS4_XCVR_CLK>,
	341	<&gcc USB_HS4_H_CLK>;
	342	clock-names = "core", "iface";
	343
	344	resets = <&gcc USB_HS4_RESET>;
	345	reset-names = "link";
	346	};
	347
ea986611 SK	348	gadget1: gadget@12500000 {
	349	compatible = "qcom,ci-hdrc";
	350	reg = <0x12500000 0x400>;
	351	status = "disabled";
	352	dr_mode = "peripheral";
	353	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	354	usb-phy = <&usb1_phy>;
	355	};
	356
	357	usb1: usb@12500000 {
	358	compatible = "qcom,ehci-host";
	359	reg = <0x12500000 0x400>;
	360	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	361	status = "disabled";
	362	usb-phy = <&usb1_phy>;
	363	};
	364
223280b1 SK	365	usb3: usb@12520000 {
	366	compatible = "qcom,ehci-host";
	367	reg = <0x12520000 0x400>;
	368	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	369	status = "disabled";
	370	usb-phy = <&usb3_phy>;
	371	};
	372
	373	usb4: usb@12530000 {
	374	compatible = "qcom,ehci-host";
	375	reg = <0x12530000 0x400>;
	376	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	377	status = "disabled";
	378	usb-phy = <&usb4_phy>;
	379	};
	380
e629335f SK	381	sata_phy0: phy@1b400000 {
	382	compatible = "qcom,apq8064-sata-phy";
	383	status = "disabled";
	384	reg = <0x1b400000 0x200>;
	385	reg-names = "phy_mem";
	386	clocks = <&gcc SATA_PHY_CFG_CLK>;
	387	clock-names = "cfg";
	388	#phy-cells = <0>;
	389	};
	390
	391	sata0: sata@29000000 {
	392	compatible = "generic-ahci";
	393	status = "disabled";
	394	reg = <0x29000000 0x180>;
	395	interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
	396
	397	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	398	<&gcc SATA_H_CLK>,
	399	<&gcc SATA_A_CLK>,
	400	<&gcc SATA_RXOOB_CLK>,
	401	<&gcc SATA_PMALIVE_CLK>;
	402	clock-names = "slave_iface",
	403	"iface",
	404	"bus",
	405	"rxoob",
	406	"core_pmalive";
	407
	408	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	409	<&gcc SATA_PMALIVE_CLK>;
	410	assigned-clock-rates = <100000000>, <100000000>;
	411
	412	phys = <&sata_phy0>;
	413	phy-names = "sata-phy";
	414	};
	415
045644ff SK	416	/* Temporary fixed regulator */
	417	vsdcc_fixed: vsdcc-regulator {
	418	compatible = "regulator-fixed";
	419	regulator-name = "SDCC Power";
	420	regulator-min-microvolt = <2700000>;
	421	regulator-max-microvolt = <2700000>;
	422	regulator-always-on;
	423	};
	424
edb81ca3 SK	425	sdcc1bam:dma@12402000{
	426	compatible = "qcom,bam-v1.3.0";
	427	reg = <0x12402000 0x8000>;
	428	interrupts = <0 98 0>;
	429	clocks = <&gcc SDC1_H_CLK>;
	430	clock-names = "bam_clk";
	431	#dma-cells = <1>;
	432	qcom,ee = <0>;
	433	};
	434
	435	sdcc3bam:dma@12182000{
	436	compatible = "qcom,bam-v1.3.0";
	437	reg = <0x12182000 0x8000>;
	438	interrupts = <0 96 0>;
	439	clocks = <&gcc SDC3_H_CLK>;
	440	clock-names = "bam_clk";
	441	#dma-cells = <1>;
	442	qcom,ee = <0>;
	443	};
	444
0be5fef1 SK	445	sdcc4bam:dma@121c2000{
	446	compatible = "qcom,bam-v1.3.0";
	447	reg = <0x121c2000 0x8000>;
	448	interrupts = <0 95 0>;
	449	clocks = <&gcc SDC4_H_CLK>;
	450	clock-names = "bam_clk";
	451	#dma-cells = <1>;
	452	qcom,ee = <0>;
	453	};
	454
045644ff SK	455	amba {
	456	compatible = "arm,amba-bus";
	457	#address-cells = <1>;
	458	#size-cells = <1>;
	459	ranges;
	460	sdcc1: sdcc@12400000 {
	461	status = "disabled";
	462	compatible = "arm,pl18x", "arm,primecell";
	463	arm,primecell-periphid = <0x00051180>;
	464	reg = <0x12400000 0x2000>;
	465	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	466	interrupt-names = "cmd_irq";
	467	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	468	clock-names = "mclk", "apb_pclk";
	469	bus-width = <8>;
	470	max-frequency = <96000000>;
	471	non-removable;
	472	cap-sd-highspeed;
	473	cap-mmc-highspeed;
	474	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	475	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	476	dma-names = "tx", "rx";
045644ff SK	477	};
	478
	479	sdcc3: sdcc@12180000 {
	480	compatible = "arm,pl18x", "arm,primecell";
	481	arm,primecell-periphid = <0x00051180>;
	482	status = "disabled";
	483	reg = <0x12180000 0x2000>;
	484	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	485	interrupt-names = "cmd_irq";
	486	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	487	clock-names = "mclk", "apb_pclk";
	488	bus-width = <4>;
	489	cap-sd-highspeed;
	490	cap-mmc-highspeed;
	491	max-frequency = <192000000>;
	492	no-1-8-v;
	493	vmmc-supply = <&vsdcc_fixed>;
edb81ca3 SK	494	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	495	dma-names = "tx", "rx";
045644ff	496	};
0be5fef1 SK	497
	498	sdcc4: sdcc@121c0000 {
	499	compatible = "arm,pl18x", "arm,primecell";
	500	arm,primecell-periphid = <0x00051180>;
	501	status = "disabled";
	502	reg = <0x121c0000 0x2000>;
	503	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	504	interrupt-names = "cmd_irq";
	505	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	506	clock-names = "mclk", "apb_pclk";
	507	bus-width = <4>;
	508	cap-sd-highspeed;
	509	cap-mmc-highspeed;
	510	max-frequency = <48000000>;
	511	vmmc-supply = <&vsdcc_fixed>;
	512	vqmmc-supply = <&vsdcc_fixed>;
	513	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	514	dma-names = "tx", "rx";
	515	pinctrl-names = "default";
	516	pinctrl-0 = <&sdc4_gpios>;
	517	};
045644ff	518	};
4105d9d6 AG	519
	520	tcsr: syscon@1a400000 {
	521	compatible = "qcom,tcsr-apq8064", "syscon";
	522	reg = <0x1a400000 0x100>;
	523	};
f335b8af KG	524	};
f335b8af KG	525	};