[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi

/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@80000000 {
			reg = <0x80000000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	sfpb_mutex: hwmutex {
		compatible = "qcom,sfpb-mutex";
		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;

		hwlocks = <&sfpb_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};

			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};

			i2c3_pins: i2c3 {
				mux {
					pins = "gpio8", "gpio9";
					function = "gsbi3";
				};
			};

			gsbi6_uart_2pins: gsbi6_uart_2pins {
				mux {
					pins = "gpio14", "gpio15";
					function = "gsbi6";
				};
			};

			gsbi6_uart_4pins: gsbi6_uart_4pins {
				mux {
					pins = "gpio14", "gpio15", "gpio16", "gpio17";
					function = "gsbi6";
				};
			};

			gsbi7_uart_2pins: gsbi7_uart_2pins {
				mux {
					pins = "gpio82", "gpio83";
					function = "gsbi7";
				};
			};

			gsbi7_uart_4pins: gsbi7_uart_4pins {
				mux {
					pins = "gpio82", "gpio83", "gpio84", "gpio85";
					function = "gsbi7";
				};
			};
		};

		sfpb_wrapper_mutex: syscon@1200000 {
			compatible = "syscon";
			reg = <0x01200000 0x8000>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi1_i2c: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-names = "default";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi2_i2c: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			gsbi3_i2c: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c3_pins>;
				pinctrl-names = "default";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi5: gsbi@1a200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x1a200000 0x03>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi5_serial: serial@1a240000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x1a240000 0x100>,
				      <0x1a200000 0x03>;
				interrupts = <0 154 0x0>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi6: gsbi@16500000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <6>;
			reg = <0x16500000 0x03>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x100>,
				      <0x16500000 0x03>;
				interrupts = <0 156 0x0>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;

					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

				rtc@11d {
					compatible = "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};

				pwrkey@1c {
					compatible = "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};
			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			rpmcc: clock-controller {
				compatible	= "qcom,rpmcc-apq8064", "qcom,rpmcc";
				#clock-cells = <1>;
			};

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_s1: s1 {};
				pm8921_s2: s2 {};
				pm8921_s3: s3 {};
				pm8921_s4: s4 {};
				pm8921_s7: s7 {};
				pm8921_s8: s8 {};

				pm8921_l1: l1 {};
				pm8921_l2: l2 {};
				pm8921_l3: l3 {};
				pm8921_l4: l4 {};
				pm8921_l5: l5 {};
				pm8921_l6: l6 {};
				pm8921_l7: l7 {};
				pm8921_l8: l8 {};
				pm8921_l9: l9 {};
				pm8921_l10: l10 {};
				pm8921_l11: l11 {};
				pm8921_l12: l12 {};
				pm8921_l14: l14 {};
				pm8921_l15: l15 {};
				pm8921_l16: l16 {};
				pm8921_l17: l17 {};
				pm8921_l18: l18 {};
				pm8921_l21: l21 {};
				pm8921_l22: l22 {};
				pm8921_l23: l23 {};
				pm8921_l24: l24 {};
				pm8921_l25: l25 {};
				pm8921_l26: l26 {};
				pm8921_l27: l27 {};
				pm8921_l28: l28 {};
				pm8921_l29: l29 {};

				pm8921_lvs1: lvs1 {};
				pm8921_lvs2: lvs2 {};
				pm8921_lvs3: lvs3 {};
				pm8921_lvs4: lvs4 {};
				pm8921_lvs5: lvs5 {};
				pm8921_lvs6: lvs6 {};
				pm8921_lvs7: lvs7 {};

				pm8921_usb_switch: usb-switch {};

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};

				pm8921_ncp: ncp {};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};

		pcie: pci@1b500000 {
			compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
			reg = <0x1b500000 0x1000
			       0x1b502000 0x80
			       0x1b600000 0x100
			       0x0ff00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
				  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc PCIE_A_CLK>,
				 <&gcc PCIE_H_CLK>,
				 <&gcc PCIE_PHY_REF_CLK>;
			clock-names = "core", "iface", "phy";
			resets = <&gcc PCIE_ACLK_RESET>,
				 <&gcc PCIE_HCLK_RESET>,
				 <&gcc PCIE_POR_RESET>,
				 <&gcc PCIE_PCI_RESET>,
				 <&gcc PCIE_PHY_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy";
			status = "disabled";
		};
	};
};
Commit	Line	Data
f335b8af KG	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
223280b1	5	#include <dt-bindings/reset/qcom,gcc-msm8960.h>
3fe5e3ce	6	#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
f335b8af	7	#include <dt-bindings/soc/qcom,gsbi.h>
8b8936fc	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
f335b8af KG	9	/ {
	10	model = "Qualcomm APQ8064";
	11	compatible = "qcom,apq8064";
	12	interrupt-parent = <&intc>;
	13
24a9baf9 BA	14	reserved-memory {
	15	#address-cells = <1>;
	16	#size-cells = <1>;
	17	ranges;
	18
	19	smem_region: smem@80000000 {
	20	reg = <0x80000000 0x200000>;
	21	no-map;
	22	};
	23	};
	24
f335b8af KG	25	cpus {
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28
	29	cpu@0 {
	30	compatible = "qcom,krait";
	31	enable-method = "qcom,kpss-acc-v1";
	32	device_type = "cpu";
	33	reg = <0>;
	34	next-level-cache = <&L2>;
	35	qcom,acc = <&acc0>;
	36	qcom,saw = <&saw0>;
06c49f2b	37	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	38	};
	39
	40	cpu@1 {
	41	compatible = "qcom,krait";
	42	enable-method = "qcom,kpss-acc-v1";
	43	device_type = "cpu";
	44	reg = <1>;
	45	next-level-cache = <&L2>;
	46	qcom,acc = <&acc1>;
	47	qcom,saw = <&saw1>;
06c49f2b	48	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	49	};
	50
	51	cpu@2 {
	52	compatible = "qcom,krait";
	53	enable-method = "qcom,kpss-acc-v1";
	54	device_type = "cpu";
	55	reg = <2>;
	56	next-level-cache = <&L2>;
	57	qcom,acc = <&acc2>;
	58	qcom,saw = <&saw2>;
06c49f2b	59	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	60	};
	61
	62	cpu@3 {
	63	compatible = "qcom,krait";
	64	enable-method = "qcom,kpss-acc-v1";
	65	device_type = "cpu";
	66	reg = <3>;
	67	next-level-cache = <&L2>;
	68	qcom,acc = <&acc3>;
	69	qcom,saw = <&saw3>;
06c49f2b	70	cpu-idle-states = <&CPU_SPC>;
f335b8af KG	71	};
	72
	73	L2: l2-cache {
	74	compatible = "cache";
	75	cache-level = <2>;
	76	};
06c49f2b LI	77
	78	idle-states {
	79	CPU_SPC: spc {
	80	compatible = "qcom,idle-state-spc",
	81	"arm,idle-state";
	82	entry-latency-us = <400>;
	83	exit-latency-us = <900>;
	84	min-residency-us = <3000>;
	85	};
	86	};
f335b8af KG	87	};
	88
	89	cpu-pmu {
	90	compatible = "qcom,krait-pmu";
	91	interrupts = <1 10 0x304>;
	92	};
	93
aa269127 GD	94	clocks {
	95	cxo_board {
	96	compatible = "fixed-clock";
	97	#clock-cells = <0>;
	98	clock-frequency = <19200000>;
	99	};
	100
	101	pxo_board {
	102	compatible = "fixed-clock";
	103	#clock-cells = <0>;
	104	clock-frequency = <27000000>;
	105	};
	106
	107	sleep_clk {
	108	compatible = "fixed-clock";
	109	#clock-cells = <0>;
	110	clock-frequency = <32768>;
	111	};
	112	};
	113
24a9baf9 BA	114	sfpb_mutex: hwmutex {
	115	compatible = "qcom,sfpb-mutex";
	116	syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
	117	#hwlock-cells = <1>;
	118	};
	119
	120	smem {
	121	compatible = "qcom,smem";
	122	memory-region = <&smem_region>;
	123
	124	hwlocks = <&sfpb_mutex 3>;
	125	};
	126
f335b8af KG	127	soc: soc {
	128	#address-cells = <1>;
	129	#size-cells = <1>;
	130	ranges;
	131	compatible = "simple-bus";
	132
8b8936fc PG	133	tlmm_pinmux: pinctrl@800000 {
	134	compatible = "qcom,apq8064-pinctrl";
	135	reg = <0x800000 0x4000>;
	136
	137	gpio-controller;
	138	#gpio-cells = <2>;
	139	interrupt-controller;
	140	#interrupt-cells = <2>;
	141	interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
cd6dd11a PG	142
	143	pinctrl-names = "default";
	144	pinctrl-0 = <&ps_hold>;
	145
0be5fef1 SK	146	sdc4_gpios: sdc4-gpios {
	147	pios {
	148	pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
	149	function = "sdc4";
	150	};
	151	};
	152
cd6dd11a PG	153	ps_hold: ps_hold {
	154	mux {
	155	pins = "gpio78";
	156	function = "ps_hold";
	157	};
	158	};
bc0d3076 SK	159
	160	i2c1_pins: i2c1 {
	161	mux {
	162	pins = "gpio20", "gpio21";
	163	function = "gsbi1";
	164	};
	165	};
3f62b46b SK	166
	167	i2c3_pins: i2c3 {
	168	mux {
	169	pins = "gpio8", "gpio9";
	170	function = "gsbi3";
	171	};
	172	};
86e252a4	173
7648c7bf SK	174	gsbi6_uart_2pins: gsbi6_uart_2pins {
	175	mux {
	176	pins = "gpio14", "gpio15";
	177	function = "gsbi6";
	178	};
	179	};
	180
	181	gsbi6_uart_4pins: gsbi6_uart_4pins {
86e252a4 PG	182	mux {
	183	pins = "gpio14", "gpio15", "gpio16", "gpio17";
	184	function = "gsbi6";
	185	};
	186	};
892d6733 SK	187
	188	gsbi7_uart_2pins: gsbi7_uart_2pins {
	189	mux {
	190	pins = "gpio82", "gpio83";
	191	function = "gsbi7";
	192	};
	193	};
	194
	195	gsbi7_uart_4pins: gsbi7_uart_4pins {
	196	mux {
	197	pins = "gpio82", "gpio83", "gpio84", "gpio85";
	198	function = "gsbi7";
	199	};
	200	};
8b8936fc PG	201	};
8b8936fc PG	202
24a9baf9 BA	203	sfpb_wrapper_mutex: syscon@1200000 {
	204	compatible = "syscon";
	205	reg = <0x01200000 0x8000>;
	206	};
	207
f335b8af KG	208	intc: interrupt-controller@2000000 {
	209	compatible = "qcom,msm-qgic2";
	210	interrupt-controller;
	211	#interrupt-cells = <3>;
	212	reg = <0x02000000 0x1000>,
	213	<0x02002000 0x1000>;
	214	};
	215
	216	timer@200a000 {
	217	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	218	interrupts = <1 1 0x301>,
	219	<1 2 0x301>,
	220	<1 3 0x301>;
	221	reg = <0x0200a000 0x100>;
	222	clock-frequency = <27000000>,
	223	<32768>;
	224	cpu-offset = <0x80000>;
	225	};
	226
	227	acc0: clock-controller@2088000 {
	228	compatible = "qcom,kpss-acc-v1";
	229	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	230	};
	231
	232	acc1: clock-controller@2098000 {
	233	compatible = "qcom,kpss-acc-v1";
	234	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	235	};
	236
	237	acc2: clock-controller@20a8000 {
	238	compatible = "qcom,kpss-acc-v1";
	239	reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
	240	};
	241
	242	acc3: clock-controller@20b8000 {
	243	compatible = "qcom,kpss-acc-v1";
	244	reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
	245	};
	246
9fc23ce3 LI	247	saw0: power-controller@2089000 {
9fc23ce3 LI	248	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	249	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	250	regulator;
	251	};
	252
9fc23ce3 LI	253	saw1: power-controller@2099000 {
9fc23ce3 LI	254	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	255	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	256	regulator;
	257	};
	258
9fc23ce3 LI	259	saw2: power-controller@20a9000 {
9fc23ce3 LI	260	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	261	reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
	262	regulator;
	263	};
	264
9fc23ce3 LI	265	saw3: power-controller@20b9000 {
9fc23ce3 LI	266	compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
f335b8af KG	267	reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
	268	regulator;
	269	};
	270
8c3166f5	271	gsbi1: gsbi@12440000 {
	272	status = "disabled";
	273	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	274	cell-index = <1>;
8c3166f5	275	reg = <0x12440000 0x100>;
	276	clocks = <&gcc GSBI1_H_CLK>;
	277	clock-names = "iface";
	278	#address-cells = <1>;
	279	#size-cells = <1>;
	280	ranges;
	281
4105d9d6 AG	282	syscon-tcsr = <&tcsr>;
4105d9d6 AG	283
e07214db	284	gsbi1_i2c: i2c@12460000 {
8c3166f5	285	compatible = "qcom,i2c-qup-v1.1.1";
0fbf6104 SK	286	pinctrl-0 = <&i2c1_pins>;
0fbf6104 SK	287	pinctrl-names = "default";
8c3166f5	288	reg = <0x12460000 0x1000>;
	289	interrupts = <0 194 IRQ_TYPE_NONE>;
	290	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	291	clock-names = "core", "iface";
	292	#address-cells = <1>;
	293	#size-cells = <0>;
	294	};
	295	};
	296
	297	gsbi2: gsbi@12480000 {
	298	status = "disabled";
	299	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	300	cell-index = <2>;
8c3166f5	301	reg = <0x12480000 0x100>;
	302	clocks = <&gcc GSBI2_H_CLK>;
	303	clock-names = "iface";
	304	#address-cells = <1>;
	305	#size-cells = <1>;
	306	ranges;
	307
4105d9d6 AG	308	syscon-tcsr = <&tcsr>;
4105d9d6 AG	309
e07214db	310	gsbi2_i2c: i2c@124a0000 {
8c3166f5	311	compatible = "qcom,i2c-qup-v1.1.1";
	312	reg = <0x124a0000 0x1000>;
	313	interrupts = <0 196 IRQ_TYPE_NONE>;
	314	clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
	315	clock-names = "core", "iface";
	316	#address-cells = <1>;
	317	#size-cells = <0>;
	318	};
	319	};
	320
3f62b46b SK	321	gsbi3: gsbi@16200000 {
	322	status = "disabled";
	323	compatible = "qcom,gsbi-v1.0.0";
504155ca	324	cell-index = <3>;
3f62b46b SK	325	reg = <0x16200000 0x100>;
	326	clocks = <&gcc GSBI3_H_CLK>;
	327	clock-names = "iface";
	328	#address-cells = <1>;
	329	#size-cells = <1>;
	330	ranges;
e07214db	331	gsbi3_i2c: i2c@16280000 {
3f62b46b	332	compatible = "qcom,i2c-qup-v1.1.1";
0fbf6104 SK	333	pinctrl-0 = <&i2c3_pins>;
0fbf6104 SK	334	pinctrl-names = "default";
3f62b46b SK	335	reg = <0x16280000 0x1000>;
	336	interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
	337	clocks = <&gcc GSBI3_QUP_CLK>,
	338	<&gcc GSBI3_H_CLK>;
	339	clock-names = "core", "iface";
5d31f606 JS	340	#address-cells = <1>;
5d31f606 JS	341	#size-cells = <0>;
1099b26e BA	342	};
	343	};
	344
	345	gsbi5: gsbi@1a200000 {
	346	status = "disabled";
	347	compatible = "qcom,gsbi-v1.0.0";
	348	cell-index = <5>;
	349	reg = <0x1a200000 0x03>;
	350	clocks = <&gcc GSBI5_H_CLK>;
	351	clock-names = "iface";
	352	#address-cells = <1>;
	353	#size-cells = <1>;
	354	ranges;
	355
	356	gsbi5_serial: serial@1a240000 {
	357	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	358	reg = <0x1a240000 0x100>,
	359	<0x1a200000 0x03>;
	360	interrupts = <0 154 0x0>;
	361	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	362	clock-names = "core", "iface";
	363	status = "disabled";
3f62b46b SK	364	};
	365	};
	366
86e252a4 PG	367	gsbi6: gsbi@16500000 {
	368	status = "disabled";
	369	compatible = "qcom,gsbi-v1.0.0";
	370	cell-index = <6>;
	371	reg = <0x16500000 0x03>;
	372	clocks = <&gcc GSBI6_H_CLK>;
	373	clock-names = "iface";
	374	#address-cells = <1>;
	375	#size-cells = <1>;
	376	ranges;
	377
	378	gsbi6_serial: serial@16540000 {
	379	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	380	reg = <0x16540000 0x100>,
	381	<0x16500000 0x03>;
	382	interrupts = <0 156 0x0>;
	383	clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
	384	clock-names = "core", "iface";
	385	status = "disabled";
	386	};
	387	};
	388
f335b8af KG	389	gsbi7: gsbi@16600000 {
	390	status = "disabled";
	391	compatible = "qcom,gsbi-v1.0.0";
4105d9d6	392	cell-index = <7>;
f335b8af KG	393	reg = <0x16600000 0x100>;
	394	clocks = <&gcc GSBI7_H_CLK>;
	395	clock-names = "iface";
	396	#address-cells = <1>;
	397	#size-cells = <1>;
	398	ranges;
4105d9d6 AG	399	syscon-tcsr = <&tcsr>;
4105d9d6 AG	400
d5d4654e	401	gsbi7_serial: serial@16640000 {
f335b8af KG	402	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	403	reg = <0x16640000 0x1000>,
	404	<0x16600000 0x1000>;
	405	interrupts = <0 158 0x0>;
	406	clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
	407	clock-names = "core", "iface";
	408	status = "disabled";
	409	};
	410	};
	411
6a607e03 JS	412	rng@1a500000 {
	413	compatible = "qcom,prng";
	414	reg = <0x1a500000 0x200>;
	415	clocks = <&gcc PRNG_CLK>;
	416	clock-names = "core";
	417	};
	418
f335b8af KG	419	qcom,ssbi@500000 {
	420	compatible = "qcom,ssbi";
	421	reg = <0x00500000 0x1000>;
	422	qcom,controller-type = "pmic-arbiter";
874443fe SK	423
	424	pmicintc: pmic@0 {
	425	compatible = "qcom,pm8921";
	426	interrupt-parent = <&tlmm_pinmux>;
	427	interrupts = <74 8>;
	428	#interrupt-cells = <2>;
	429	interrupt-controller;
	430	#address-cells = <1>;
	431	#size-cells = <0>;
	432
	433	pm8921_gpio: gpio@150 {
	434
2ca9c2a4 SB	435	compatible = "qcom,pm8921-gpio",
2ca9c2a4 SB	436	"qcom,ssbi-gpio";
874443fe SK	437	reg = <0x150>;
	438	interrupts = <192 1>, <193 1>, <194 1>,
	439	<195 1>, <196 1>, <197 1>,
	440	<198 1>, <199 1>, <200 1>,
	441	<201 1>, <202 1>, <203 1>,
	442	<204 1>, <205 1>, <206 1>,
	443	<207 1>, <208 1>, <209 1>,
	444	<210 1>, <211 1>, <212 1>,
	445	<213 1>, <214 1>, <215 1>,
	446	<216 1>, <217 1>, <218 1>,
	447	<219 1>, <220 1>, <221 1>,
	448	<222 1>, <223 1>, <224 1>,
	449	<225 1>, <226 1>, <227 1>,
	450	<228 1>, <229 1>, <230 1>,
	451	<231 1>, <232 1>, <233 1>,
	452	<234 1>, <235 1>;
	453
	454	gpio-controller;
	455	#gpio-cells = <2>;
	456
	457	};
bce36046 SK	458
bce36046 SK	459	pm8921_mpps: mpps@50 {
2ca9c2a4 SB	460	compatible = "qcom,pm8921-mpp",
2ca9c2a4 SB	461	"qcom,ssbi-mpp";
bce36046 SK	462	reg = <0x50>;
	463	gpio-controller;
	464	#gpio-cells = <2>;
	465	interrupts =
	466	<128 1>, <129 1>, <130 1>, <131 1>,
	467	<132 1>, <133 1>, <134 1>, <135 1>,
	468	<136 1>, <137 1>, <138 1>, <139 1>;
	469	};
	470
bbf89b96 SK	471	rtc@11d {
	472	compatible = "qcom,pm8921-rtc";
	473	interrupt-parent = <&pmicintc>;
	474	interrupts = <39 1>;
	475	reg = <0x11d>;
	476	allow-set-time;
	477	};
	478
3050c5f5 SK	479	pwrkey@1c {
	480	compatible = "qcom,pm8921-pwrkey";
	481	reg = <0x1c>;
	482	interrupt-parent = <&pmicintc>;
	483	interrupts = <50 1>, <51 1>;
	484	debounce = <15625>;
	485	pull-up;
	486	};
874443fe	487	};
f335b8af KG	488	};
	489
	490	gcc: clock-controller@900000 {
	491	compatible = "qcom,gcc-apq8064";
	492	reg = <0x00900000 0x4000>;
	493	#clock-cells = <1>;
	494	#reset-cells = <1>;
	495	};
3fe5e3ce	496
1e1177bf KG	497	lcc: clock-controller@28000000 {
	498	compatible = "qcom,lcc-apq8064";
	499	reg = <0x28000000 0x1000>;
	500	#clock-cells = <1>;
	501	#reset-cells = <1>;
	502	};
	503
3fe5e3ce SB	504	mmcc: clock-controller@4000000 {
	505	compatible = "qcom,mmcc-apq8064";
	506	reg = <0x4000000 0x1000>;
	507	#clock-cells = <1>;
	508	#reset-cells = <1>;
	509	};
045644ff	510
dc2f8152 SK	511	l2cc: clock-controller@2011000 {
	512	compatible = "syscon";
	513	reg = <0x2011000 0x1000>;
	514	};
	515
	516	rpm@108000 {
	517	compatible = "qcom,rpm-apq8064";
	518	reg = <0x108000 0x1000>;
	519	qcom,ipc = <&l2cc 0x8 2>;
	520
	521	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	522	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	523	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	524	interrupt-names = "ack", "err", "wakeup";
	525
aac1b297 GD	526	rpmcc: clock-controller {
	527	compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
	528	#clock-cells = <1>;
	529	};
	530
dc2f8152 SK	531	regulators {
	532	compatible = "qcom,rpm-pm8921-regulators";
	533
2bce6e26 BA	534	pm8921_s1: s1 {};
	535	pm8921_s2: s2 {};
	536	pm8921_s3: s3 {};
	537	pm8921_s4: s4 {};
	538	pm8921_s7: s7 {};
	539	pm8921_s8: s8 {};
	540
	541	pm8921_l1: l1 {};
	542	pm8921_l2: l2 {};
	543	pm8921_l3: l3 {};
	544	pm8921_l4: l4 {};
	545	pm8921_l5: l5 {};
	546	pm8921_l6: l6 {};
	547	pm8921_l7: l7 {};
	548	pm8921_l8: l8 {};
	549	pm8921_l9: l9 {};
	550	pm8921_l10: l10 {};
	551	pm8921_l11: l11 {};
	552	pm8921_l12: l12 {};
	553	pm8921_l14: l14 {};
	554	pm8921_l15: l15 {};
	555	pm8921_l16: l16 {};
	556	pm8921_l17: l17 {};
	557	pm8921_l18: l18 {};
	558	pm8921_l21: l21 {};
	559	pm8921_l22: l22 {};
	560	pm8921_l23: l23 {};
	561	pm8921_l24: l24 {};
	562	pm8921_l25: l25 {};
	563	pm8921_l26: l26 {};
	564	pm8921_l27: l27 {};
	565	pm8921_l28: l28 {};
	566	pm8921_l29: l29 {};
	567
	568	pm8921_lvs1: lvs1 {};
	569	pm8921_lvs2: lvs2 {};
	570	pm8921_lvs3: lvs3 {};
	571	pm8921_lvs4: lvs4 {};
	572	pm8921_lvs5: lvs5 {};
	573	pm8921_lvs6: lvs6 {};
	574	pm8921_lvs7: lvs7 {};
	575
	576	pm8921_usb_switch: usb-switch {};
	577
dc2f8152 SK	578	pm8921_hdmi_switch: hdmi-switch {
	579	bias-pull-down;
	580	};
2bce6e26 BA	581
2bce6e26 BA	582	pm8921_ncp: ncp {};
dc2f8152 SK	583	};
	584	};
	585
ea986611 SK	586	usb1_phy: phy@12500000 {
	587	compatible = "qcom,usb-otg-ci";
	588	reg = <0x12500000 0x400>;
	589	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	590	status = "disabled";
	591	dr_mode = "host";
	592
	593	clocks = <&gcc USB_HS1_XCVR_CLK>,
	594	<&gcc USB_HS1_H_CLK>;
	595	clock-names = "core", "iface";
	596
	597	resets = <&gcc USB_HS1_RESET>;
	598	reset-names = "link";
	599	};
	600
223280b1 SK	601	usb3_phy: phy@12520000 {
	602	compatible = "qcom,usb-otg-ci";
	603	reg = <0x12520000 0x400>;
	604	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	605	status = "disabled";
	606	dr_mode = "host";
	607
	608	clocks = <&gcc USB_HS3_XCVR_CLK>,
	609	<&gcc USB_HS3_H_CLK>;
	610	clock-names = "core", "iface";
	611
	612	resets = <&gcc USB_HS3_RESET>;
	613	reset-names = "link";
	614	};
	615
	616	usb4_phy: phy@12530000 {
	617	compatible = "qcom,usb-otg-ci";
	618	reg = <0x12530000 0x400>;
	619	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	620	status = "disabled";
	621	dr_mode = "host";
	622
	623	clocks = <&gcc USB_HS4_XCVR_CLK>,
	624	<&gcc USB_HS4_H_CLK>;
	625	clock-names = "core", "iface";
	626
	627	resets = <&gcc USB_HS4_RESET>;
	628	reset-names = "link";
	629	};
	630
ea986611 SK	631	gadget1: gadget@12500000 {
	632	compatible = "qcom,ci-hdrc";
	633	reg = <0x12500000 0x400>;
	634	status = "disabled";
	635	dr_mode = "peripheral";
	636	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	637	usb-phy = <&usb1_phy>;
	638	};
	639
	640	usb1: usb@12500000 {
	641	compatible = "qcom,ehci-host";
	642	reg = <0x12500000 0x400>;
	643	interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
	644	status = "disabled";
	645	usb-phy = <&usb1_phy>;
	646	};
	647
223280b1 SK	648	usb3: usb@12520000 {
	649	compatible = "qcom,ehci-host";
	650	reg = <0x12520000 0x400>;
	651	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
	652	status = "disabled";
	653	usb-phy = <&usb3_phy>;
	654	};
	655
	656	usb4: usb@12530000 {
	657	compatible = "qcom,ehci-host";
	658	reg = <0x12530000 0x400>;
	659	interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
	660	status = "disabled";
	661	usb-phy = <&usb4_phy>;
	662	};
	663
e629335f SK	664	sata_phy0: phy@1b400000 {
	665	compatible = "qcom,apq8064-sata-phy";
	666	status = "disabled";
	667	reg = <0x1b400000 0x200>;
	668	reg-names = "phy_mem";
	669	clocks = <&gcc SATA_PHY_CFG_CLK>;
	670	clock-names = "cfg";
	671	#phy-cells = <0>;
	672	};
	673
	674	sata0: sata@29000000 {
	675	compatible = "generic-ahci";
	676	status = "disabled";
	677	reg = <0x29000000 0x180>;
	678	interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
	679
	680	clocks = <&gcc SFAB_SATA_S_H_CLK>,
	681	<&gcc SATA_H_CLK>,
	682	<&gcc SATA_A_CLK>,
	683	<&gcc SATA_RXOOB_CLK>,
	684	<&gcc SATA_PMALIVE_CLK>;
	685	clock-names = "slave_iface",
	686	"iface",
	687	"bus",
	688	"rxoob",
	689	"core_pmalive";
	690
	691	assigned-clocks = <&gcc SATA_RXOOB_CLK>,
	692	<&gcc SATA_PMALIVE_CLK>;
	693	assigned-clock-rates = <100000000>, <100000000>;
	694
	695	phys = <&sata_phy0>;
	696	phy-names = "sata-phy";
	697	};
	698
045644ff	699	/* Temporary fixed regulator */
edb81ca3 SK	700	sdcc1bam:dma@12402000{
	701	compatible = "qcom,bam-v1.3.0";
	702	reg = <0x12402000 0x8000>;
	703	interrupts = <0 98 0>;
	704	clocks = <&gcc SDC1_H_CLK>;
	705	clock-names = "bam_clk";
	706	#dma-cells = <1>;
	707	qcom,ee = <0>;
	708	};
	709
	710	sdcc3bam:dma@12182000{
	711	compatible = "qcom,bam-v1.3.0";
	712	reg = <0x12182000 0x8000>;
	713	interrupts = <0 96 0>;
	714	clocks = <&gcc SDC3_H_CLK>;
	715	clock-names = "bam_clk";
	716	#dma-cells = <1>;
	717	qcom,ee = <0>;
	718	};
	719
0be5fef1 SK	720	sdcc4bam:dma@121c2000{
	721	compatible = "qcom,bam-v1.3.0";
	722	reg = <0x121c2000 0x8000>;
	723	interrupts = <0 95 0>;
	724	clocks = <&gcc SDC4_H_CLK>;
	725	clock-names = "bam_clk";
	726	#dma-cells = <1>;
	727	qcom,ee = <0>;
	728	};
	729
045644ff SK	730	amba {
	731	compatible = "arm,amba-bus";
	732	#address-cells = <1>;
	733	#size-cells = <1>;
	734	ranges;
	735	sdcc1: sdcc@12400000 {
	736	status = "disabled";
	737	compatible = "arm,pl18x", "arm,primecell";
	738	arm,primecell-periphid = <0x00051180>;
	739	reg = <0x12400000 0x2000>;
	740	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	741	interrupt-names = "cmd_irq";
	742	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	743	clock-names = "mclk", "apb_pclk";
	744	bus-width = <8>;
	745	max-frequency = <96000000>;
	746	non-removable;
	747	cap-sd-highspeed;
	748	cap-mmc-highspeed;
edb81ca3 SK	749	dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
edb81ca3 SK	750	dma-names = "tx", "rx";
045644ff SK	751	};
	752
	753	sdcc3: sdcc@12180000 {
	754	compatible = "arm,pl18x", "arm,primecell";
	755	arm,primecell-periphid = <0x00051180>;
	756	status = "disabled";
	757	reg = <0x12180000 0x2000>;
	758	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	759	interrupt-names = "cmd_irq";
	760	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	761	clock-names = "mclk", "apb_pclk";
	762	bus-width = <4>;
	763	cap-sd-highspeed;
	764	cap-mmc-highspeed;
	765	max-frequency = <192000000>;
	766	no-1-8-v;
edb81ca3 SK	767	dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
edb81ca3 SK	768	dma-names = "tx", "rx";
045644ff	769	};
0be5fef1 SK	770
	771	sdcc4: sdcc@121c0000 {
	772	compatible = "arm,pl18x", "arm,primecell";
	773	arm,primecell-periphid = <0x00051180>;
	774	status = "disabled";
	775	reg = <0x121c0000 0x2000>;
	776	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	777	interrupt-names = "cmd_irq";
	778	clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
	779	clock-names = "mclk", "apb_pclk";
	780	bus-width = <4>;
	781	cap-sd-highspeed;
	782	cap-mmc-highspeed;
	783	max-frequency = <48000000>;
0be5fef1 SK	784	dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
	785	dma-names = "tx", "rx";
	786	pinctrl-names = "default";
	787	pinctrl-0 = <&sdc4_gpios>;
	788	};
045644ff	789	};
4105d9d6 AG	790
	791	tcsr: syscon@1a400000 {
	792	compatible = "qcom,tcsr-apq8064", "syscon";
	793	reg = <0x1a400000 0x100>;
	794	};
bcc74b09 SV	795
	796	pcie: pci@1b500000 {
	797	compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
	798	reg = <0x1b500000 0x1000
	799	0x1b502000 0x80
	800	0x1b600000 0x100
	801	0x0ff00000 0x100000>;
	802	reg-names = "dbi", "elbi", "parf", "config";
	803	device_type = "pci";
	804	linux,pci-domain = <0>;
	805	bus-range = <0x00 0xff>;
	806	num-lanes = <1>;
	807	#address-cells = <3>;
	808	#size-cells = <2>;
	809	ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
	810	0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
	811	interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
	812	interrupt-names = "msi";
	813	#interrupt-cells = <1>;
	814	interrupt-map-mask = <0 0 0 0x7>;
	815	interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	816	<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	817	<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	818	<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	819	clocks = <&gcc PCIE_A_CLK>,
	820	<&gcc PCIE_H_CLK>,
	821	<&gcc PCIE_PHY_REF_CLK>;
	822	clock-names = "core", "iface", "phy";
	823	resets = <&gcc PCIE_ACLK_RESET>,
	824	<&gcc PCIE_HCLK_RESET>,
	825	<&gcc PCIE_POR_RESET>,
	826	<&gcc PCIE_PCI_RESET>,
	827	<&gcc PCIE_PHY_RESET>;
	828	reset-names = "axi", "ahb", "por", "pci", "phy";
	829	status = "disabled";
	830	};
f335b8af KG	831	};
f335b8af KG	832	};