Commit | Line | Data |
---|---|---|
975fd0f6 GD |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | ||
98a29533 | 5 | #include <dt-bindings/clock/qcom,gcc-apq8084.h> |
66c04e30 | 6 | #include <dt-bindings/gpio/gpio.h> |
98a29533 | 7 | |
975fd0f6 GD |
8 | / { |
9 | model = "Qualcomm APQ 8084"; | |
10 | compatible = "qcom,apq8084"; | |
11 | interrupt-parent = <&intc>; | |
12 | ||
64ab8863 AG |
13 | reserved-memory { |
14 | #address-cells = <1>; | |
15 | #size-cells = <1>; | |
16 | ranges; | |
17 | ||
18 | smem_mem: smem_region@fa00000 { | |
19 | reg = <0xfa00000 0x200000>; | |
20 | no-map; | |
21 | }; | |
22 | }; | |
23 | ||
975fd0f6 GD |
24 | cpus { |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | cpu@0 { | |
29 | device_type = "cpu"; | |
30 | compatible = "qcom,krait"; | |
31 | reg = <0>; | |
32 | enable-method = "qcom,kpss-acc-v2"; | |
33 | next-level-cache = <&L2>; | |
34 | qcom,acc = <&acc0>; | |
030e27f6 | 35 | qcom,saw = <&saw0>; |
d8664979 | 36 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
37 | }; |
38 | ||
39 | cpu@1 { | |
40 | device_type = "cpu"; | |
41 | compatible = "qcom,krait"; | |
42 | reg = <1>; | |
43 | enable-method = "qcom,kpss-acc-v2"; | |
44 | next-level-cache = <&L2>; | |
45 | qcom,acc = <&acc1>; | |
030e27f6 | 46 | qcom,saw = <&saw1>; |
d8664979 | 47 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
48 | }; |
49 | ||
50 | cpu@2 { | |
51 | device_type = "cpu"; | |
52 | compatible = "qcom,krait"; | |
53 | reg = <2>; | |
54 | enable-method = "qcom,kpss-acc-v2"; | |
55 | next-level-cache = <&L2>; | |
56 | qcom,acc = <&acc2>; | |
030e27f6 | 57 | qcom,saw = <&saw2>; |
d8664979 | 58 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
59 | }; |
60 | ||
61 | cpu@3 { | |
62 | device_type = "cpu"; | |
63 | compatible = "qcom,krait"; | |
64 | reg = <3>; | |
65 | enable-method = "qcom,kpss-acc-v2"; | |
66 | next-level-cache = <&L2>; | |
67 | qcom,acc = <&acc3>; | |
030e27f6 | 68 | qcom,saw = <&saw3>; |
d8664979 | 69 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
70 | }; |
71 | ||
72 | L2: l2-cache { | |
73 | compatible = "qcom,arch-cache"; | |
74 | cache-level = <2>; | |
75 | qcom,saw = <&saw_l2>; | |
76 | }; | |
d8664979 LI |
77 | |
78 | idle-states { | |
79 | CPU_SPC: spc { | |
80 | compatible = "qcom,idle-state-spc", | |
81 | "arm,idle-state"; | |
82 | entry-latency-us = <150>; | |
83 | exit-latency-us = <200>; | |
84 | min-residency-us = <2000>; | |
85 | }; | |
86 | }; | |
975fd0f6 GD |
87 | }; |
88 | ||
89 | cpu-pmu { | |
90 | compatible = "qcom,krait-pmu"; | |
91 | interrupts = <1 7 0xf04>; | |
92 | }; | |
93 | ||
94 | timer { | |
95 | compatible = "arm,armv7-timer"; | |
96 | interrupts = <1 2 0xf08>, | |
97 | <1 3 0xf08>, | |
98 | <1 4 0xf08>, | |
99 | <1 1 0xf08>; | |
100 | clock-frequency = <19200000>; | |
101 | }; | |
102 | ||
64ab8863 AG |
103 | smem { |
104 | compatible = "qcom,smem"; | |
105 | ||
106 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
107 | memory-region = <&smem_mem>; | |
108 | ||
109 | hwlocks = <&tcsr_mutex 3>; | |
110 | }; | |
111 | ||
975fd0f6 GD |
112 | soc: soc { |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | ranges; | |
116 | compatible = "simple-bus"; | |
117 | ||
118 | intc: interrupt-controller@f9000000 { | |
119 | compatible = "qcom,msm-qgic2"; | |
120 | interrupt-controller; | |
121 | #interrupt-cells = <3>; | |
122 | reg = <0xf9000000 0x1000>, | |
123 | <0xf9002000 0x1000>; | |
124 | }; | |
125 | ||
53ced99d AG |
126 | apcs: syscon@f9011000 { |
127 | compatible = "syscon"; | |
128 | reg = <0xf9011000 0x1000>; | |
129 | }; | |
130 | ||
975fd0f6 GD |
131 | timer@f9020000 { |
132 | #address-cells = <1>; | |
133 | #size-cells = <1>; | |
134 | ranges; | |
135 | compatible = "arm,armv7-timer-mem"; | |
136 | reg = <0xf9020000 0x1000>; | |
137 | clock-frequency = <19200000>; | |
138 | ||
139 | frame@f9021000 { | |
140 | frame-number = <0>; | |
141 | interrupts = <0 8 0x4>, | |
142 | <0 7 0x4>; | |
143 | reg = <0xf9021000 0x1000>, | |
144 | <0xf9022000 0x1000>; | |
145 | }; | |
146 | ||
147 | frame@f9023000 { | |
148 | frame-number = <1>; | |
149 | interrupts = <0 9 0x4>; | |
150 | reg = <0xf9023000 0x1000>; | |
151 | status = "disabled"; | |
152 | }; | |
153 | ||
154 | frame@f9024000 { | |
155 | frame-number = <2>; | |
156 | interrupts = <0 10 0x4>; | |
157 | reg = <0xf9024000 0x1000>; | |
158 | status = "disabled"; | |
159 | }; | |
160 | ||
161 | frame@f9025000 { | |
162 | frame-number = <3>; | |
163 | interrupts = <0 11 0x4>; | |
164 | reg = <0xf9025000 0x1000>; | |
165 | status = "disabled"; | |
166 | }; | |
167 | ||
168 | frame@f9026000 { | |
169 | frame-number = <4>; | |
170 | interrupts = <0 12 0x4>; | |
171 | reg = <0xf9026000 0x1000>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | ||
175 | frame@f9027000 { | |
176 | frame-number = <5>; | |
177 | interrupts = <0 13 0x4>; | |
178 | reg = <0xf9027000 0x1000>; | |
179 | status = "disabled"; | |
180 | }; | |
181 | ||
182 | frame@f9028000 { | |
183 | frame-number = <6>; | |
184 | interrupts = <0 14 0x4>; | |
185 | reg = <0xf9028000 0x1000>; | |
186 | status = "disabled"; | |
187 | }; | |
188 | }; | |
189 | ||
030e27f6 LI |
190 | saw0: power-controller@f9089000 { |
191 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
192 | reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; | |
193 | }; | |
194 | ||
195 | saw1: power-controller@f9099000 { | |
196 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
197 | reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; | |
198 | }; | |
199 | ||
200 | saw2: power-controller@f90a9000 { | |
201 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
202 | reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; | |
203 | }; | |
204 | ||
205 | saw3: power-controller@f90b9000 { | |
206 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
207 | reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; | |
208 | }; | |
209 | ||
210 | saw_l2: power-controller@f9012000 { | |
975fd0f6 GD |
211 | compatible = "qcom,saw2"; |
212 | reg = <0xf9012000 0x1000>; | |
213 | regulator; | |
214 | }; | |
215 | ||
216 | acc0: clock-controller@f9088000 { | |
217 | compatible = "qcom,kpss-acc-v2"; | |
218 | reg = <0xf9088000 0x1000>, | |
219 | <0xf9008000 0x1000>; | |
220 | }; | |
221 | ||
222 | acc1: clock-controller@f9098000 { | |
223 | compatible = "qcom,kpss-acc-v2"; | |
224 | reg = <0xf9098000 0x1000>, | |
225 | <0xf9008000 0x1000>; | |
226 | }; | |
227 | ||
228 | acc2: clock-controller@f90a8000 { | |
229 | compatible = "qcom,kpss-acc-v2"; | |
230 | reg = <0xf90a8000 0x1000>, | |
231 | <0xf9008000 0x1000>; | |
232 | }; | |
233 | ||
234 | acc3: clock-controller@f90b8000 { | |
235 | compatible = "qcom,kpss-acc-v2"; | |
236 | reg = <0xf90b8000 0x1000>, | |
237 | <0xf9008000 0x1000>; | |
238 | }; | |
239 | ||
240 | restart@fc4ab000 { | |
241 | compatible = "qcom,pshold"; | |
242 | reg = <0xfc4ab000 0x4>; | |
243 | }; | |
98a29533 GD |
244 | |
245 | gcc: clock-controller@fc400000 { | |
246 | compatible = "qcom,gcc-apq8084"; | |
247 | #clock-cells = <1>; | |
248 | #reset-cells = <1>; | |
89c7e671 | 249 | #power-domain-cells = <1>; |
98a29533 GD |
250 | reg = <0xfc400000 0x4000>; |
251 | }; | |
252 | ||
64ab8863 AG |
253 | tcsr_mutex_regs: syscon@fd484000 { |
254 | compatible = "syscon"; | |
255 | reg = <0xfd484000 0x2000>; | |
256 | }; | |
257 | ||
258 | tcsr_mutex: hwlock { | |
259 | compatible = "qcom,tcsr-mutex"; | |
260 | syscon = <&tcsr_mutex_regs 0 0x80>; | |
261 | #hwlock-cells = <1>; | |
262 | }; | |
263 | ||
264 | rpm_msg_ram: memory@fc428000 { | |
265 | compatible = "qcom,rpm-msg-ram"; | |
266 | reg = <0xfc428000 0x4000>; | |
267 | }; | |
268 | ||
44980b28 GD |
269 | tlmm: pinctrl@fd510000 { |
270 | compatible = "qcom,apq8084-pinctrl"; | |
271 | reg = <0xfd510000 0x4000>; | |
272 | gpio-controller; | |
273 | #gpio-cells = <2>; | |
274 | interrupt-controller; | |
275 | #interrupt-cells = <2>; | |
276 | interrupts = <0 208 0>; | |
277 | }; | |
278 | ||
10bfcfea | 279 | blsp2_uart2: serial@f995e000 { |
14ff1c43 GD |
280 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
281 | reg = <0xf995e000 0x1000>; | |
282 | interrupts = <0 114 0x0>; | |
283 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
284 | clock-names = "core", "iface"; | |
285 | status = "disabled"; | |
286 | }; | |
66c04e30 GD |
287 | |
288 | sdhci@f9824900 { | |
289 | compatible = "qcom,sdhci-msm-v4"; | |
290 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
291 | reg-names = "hc_mem", "core_mem"; | |
292 | interrupts = <0 123 0>, <0 138 0>; | |
293 | interrupt-names = "hc_irq", "pwr_irq"; | |
294 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | |
295 | clock-names = "core", "iface"; | |
296 | status = "disabled"; | |
297 | }; | |
298 | ||
299 | sdhci@f98a4900 { | |
300 | compatible = "qcom,sdhci-msm-v4"; | |
301 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
302 | reg-names = "hc_mem", "core_mem"; | |
303 | interrupts = <0 125 0>, <0 221 0>; | |
304 | interrupt-names = "hc_irq", "pwr_irq"; | |
305 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | |
306 | clock-names = "core", "iface"; | |
307 | status = "disabled"; | |
308 | }; | |
af22e46d II |
309 | |
310 | spmi_bus: spmi@fc4cf000 { | |
311 | compatible = "qcom,spmi-pmic-arb"; | |
312 | reg-names = "core", "intr", "cnfg"; | |
313 | reg = <0xfc4cf000 0x1000>, | |
314 | <0xfc4cb000 0x1000>, | |
315 | <0xfc4ca000 0x1000>; | |
316 | interrupt-names = "periph_irq"; | |
317 | interrupts = <0 190 0>; | |
318 | qcom,ee = <0>; | |
319 | qcom,channel = <0>; | |
320 | #address-cells = <2>; | |
321 | #size-cells = <0>; | |
322 | interrupt-controller; | |
323 | #interrupt-cells = <4>; | |
324 | }; | |
975fd0f6 | 325 | }; |
53ced99d AG |
326 | |
327 | smd { | |
328 | compatible = "qcom,smd"; | |
329 | ||
330 | rpm { | |
331 | interrupts = <0 168 1>; | |
332 | qcom,ipc = <&apcs 8 0>; | |
333 | qcom,smd-edge = <15>; | |
334 | ||
335 | rpm_requests { | |
336 | compatible = "qcom,rpm-apq8084"; | |
337 | qcom,smd-channels = "rpm_requests"; | |
4add1074 AG |
338 | |
339 | pma8084-regulators { | |
340 | compatible = "qcom,rpm-pma8084-regulators"; | |
341 | ||
342 | pma8084_s1: s1 {}; | |
343 | pma8084_s2: s2 {}; | |
344 | pma8084_s3: s3 {}; | |
345 | pma8084_s4: s4 {}; | |
346 | pma8084_s5: s5 {}; | |
347 | pma8084_s6: s6 {}; | |
348 | pma8084_s7: s7 {}; | |
349 | pma8084_s8: s8 {}; | |
350 | pma8084_s9: s9 {}; | |
351 | pma8084_s10: s10 {}; | |
352 | pma8084_s11: s11 {}; | |
353 | pma8084_s12: s12 {}; | |
354 | ||
355 | pma8084_l1: l1 {}; | |
356 | pma8084_l2: l2 {}; | |
357 | pma8084_l3: l3 {}; | |
358 | pma8084_l4: l4 {}; | |
359 | pma8084_l5: l5 {}; | |
360 | pma8084_l6: l6 {}; | |
361 | pma8084_l7: l7 {}; | |
362 | pma8084_l8: l8 {}; | |
363 | pma8084_l9: l9 {}; | |
364 | pma8084_l10: l10 {}; | |
365 | pma8084_l11: l11 {}; | |
366 | pma8084_l12: l12 {}; | |
367 | pma8084_l13: l13 {}; | |
368 | pma8084_l14: l14 {}; | |
369 | pma8084_l15: l15 {}; | |
370 | pma8084_l16: l16 {}; | |
371 | pma8084_l17: l17 {}; | |
372 | pma8084_l18: l18 {}; | |
373 | pma8084_l19: l19 {}; | |
374 | pma8084_l20: l20 {}; | |
375 | pma8084_l21: l21 {}; | |
376 | pma8084_l22: l22 {}; | |
377 | pma8084_l23: l23 {}; | |
378 | pma8084_l24: l24 {}; | |
379 | pma8084_l25: l25 {}; | |
380 | pma8084_l26: l26 {}; | |
381 | pma8084_l27: l27 {}; | |
382 | ||
383 | pma8084_lvs1: lvs1 {}; | |
384 | pma8084_lvs2: lvs2 {}; | |
385 | pma8084_lvs3: lvs3 {}; | |
386 | pma8084_lvs4: lvs4 {}; | |
387 | ||
388 | pma8084_5vs1: 5vs1 {}; | |
389 | }; | |
53ced99d AG |
390 | }; |
391 | }; | |
392 | }; | |
975fd0f6 | 393 | }; |