[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8084.dtsi

/dts-v1/;

#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Qualcomm APQ 8084";
	compatible = "qcom,apq8084";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_mem: smem_region@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <0>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <1>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <2>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <3>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "qcom,arch-cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	clocks {
		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		memory-region = <&smem_mem>;

		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-apq8084";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_regs: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x80>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,apq8084-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp2_uart2: serial@f995e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf995e000 0x1000>;
			interrupts = <0 114 0x0>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-apq8084";
				qcom,smd-channels = "rpm_requests";

				pma8084-regulators {
					compatible = "qcom,rpm-pma8084-regulators";

					pma8084_s1: s1 {};
					pma8084_s2: s2 {};
					pma8084_s3: s3 {};
					pma8084_s4: s4 {};
					pma8084_s5: s5 {};
					pma8084_s6: s6 {};
					pma8084_s7: s7 {};
					pma8084_s8: s8 {};
					pma8084_s9: s9 {};
					pma8084_s10: s10 {};
					pma8084_s11: s11 {};
					pma8084_s12: s12 {};

					pma8084_l1: l1 {};
					pma8084_l2: l2 {};
					pma8084_l3: l3 {};
					pma8084_l4: l4 {};
					pma8084_l5: l5 {};
					pma8084_l6: l6 {};
					pma8084_l7: l7 {};
					pma8084_l8: l8 {};
					pma8084_l9: l9 {};
					pma8084_l10: l10 {};
					pma8084_l11: l11 {};
					pma8084_l12: l12 {};
					pma8084_l13: l13 {};
					pma8084_l14: l14 {};
					pma8084_l15: l15 {};
					pma8084_l16: l16 {};
					pma8084_l17: l17 {};
					pma8084_l18: l18 {};
					pma8084_l19: l19 {};
					pma8084_l20: l20 {};
					pma8084_l21: l21 {};
					pma8084_l22: l22 {};
					pma8084_l23: l23 {};
					pma8084_l24: l24 {};
					pma8084_l25: l25 {};
					pma8084_l26: l26 {};
					pma8084_l27: l27 {};

					pma8084_lvs1: lvs1 {};
					pma8084_lvs2: lvs2 {};
					pma8084_lvs3: lvs3 {};
					pma8084_lvs4: lvs4 {};

					pma8084_5vs1: 5vs1 {};
				};
			};
		};
	};
};
Commit	Line	Data
975fd0f6 GD	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4
98a29533	5	#include <dt-bindings/clock/qcom,gcc-apq8084.h>
66c04e30	6	#include <dt-bindings/gpio/gpio.h>
98a29533	7
975fd0f6 GD	8	/ {
	9	model = "Qualcomm APQ 8084";
	10	compatible = "qcom,apq8084";
	11	interrupt-parent = <&intc>;
	12
64ab8863 AG	13	reserved-memory {
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16	ranges;
	17
	18	smem_mem: smem_region@fa00000 {
	19	reg = <0xfa00000 0x200000>;
	20	no-map;
	21	};
	22	};
	23
975fd0f6 GD	24	cpus {
	25	#address-cells = <1>;
	26	#size-cells = <0>;
	27
	28	cpu@0 {
	29	device_type = "cpu";
	30	compatible = "qcom,krait";
	31	reg = <0>;
	32	enable-method = "qcom,kpss-acc-v2";
	33	next-level-cache = <&L2>;
	34	qcom,acc = <&acc0>;
030e27f6	35	qcom,saw = <&saw0>;
d8664979	36	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	37	};
	38
	39	cpu@1 {
	40	device_type = "cpu";
	41	compatible = "qcom,krait";
	42	reg = <1>;
	43	enable-method = "qcom,kpss-acc-v2";
	44	next-level-cache = <&L2>;
	45	qcom,acc = <&acc1>;
030e27f6	46	qcom,saw = <&saw1>;
d8664979	47	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	48	};
	49
	50	cpu@2 {
	51	device_type = "cpu";
	52	compatible = "qcom,krait";
	53	reg = <2>;
	54	enable-method = "qcom,kpss-acc-v2";
	55	next-level-cache = <&L2>;
	56	qcom,acc = <&acc2>;
030e27f6	57	qcom,saw = <&saw2>;
d8664979	58	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	59	};
	60
	61	cpu@3 {
	62	device_type = "cpu";
	63	compatible = "qcom,krait";
	64	reg = <3>;
	65	enable-method = "qcom,kpss-acc-v2";
	66	next-level-cache = <&L2>;
	67	qcom,acc = <&acc3>;
030e27f6	68	qcom,saw = <&saw3>;
d8664979	69	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	70	};
	71
	72	L2: l2-cache {
	73	compatible = "qcom,arch-cache";
	74	cache-level = <2>;
	75	qcom,saw = <&saw_l2>;
	76	};
d8664979 LI	77
	78	idle-states {
	79	CPU_SPC: spc {
	80	compatible = "qcom,idle-state-spc",
	81	"arm,idle-state";
	82	entry-latency-us = <150>;
	83	exit-latency-us = <200>;
	84	min-residency-us = <2000>;
	85	};
	86	};
975fd0f6 GD	87	};
	88
	89	cpu-pmu {
	90	compatible = "qcom,krait-pmu";
	91	interrupts = <1 7 0xf04>;
	92	};
	93
30fc4212 SB	94	clocks {
	95	xo_board {
	96	compatible = "fixed-clock";
	97	#clock-cells = <0>;
	98	clock-frequency = <19200000>;
	99	};
	100
	101	sleep_clk {
	102	compatible = "fixed-clock";
	103	#clock-cells = <0>;
	104	clock-frequency = <32768>;
	105	};
	106	};
	107
975fd0f6 GD	108	timer {
	109	compatible = "arm,armv7-timer";
	110	interrupts = <1 2 0xf08>,
	111	<1 3 0xf08>,
	112	<1 4 0xf08>,
	113	<1 1 0xf08>;
	114	clock-frequency = <19200000>;
	115	};
	116
64ab8863 AG	117	smem {
	118	compatible = "qcom,smem";
	119
	120	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	121	memory-region = <&smem_mem>;
	122
	123	hwlocks = <&tcsr_mutex 3>;
	124	};
	125
975fd0f6 GD	126	soc: soc {
	127	#address-cells = <1>;
	128	#size-cells = <1>;
	129	ranges;
	130	compatible = "simple-bus";
	131
	132	intc: interrupt-controller@f9000000 {
	133	compatible = "qcom,msm-qgic2";
	134	interrupt-controller;
	135	#interrupt-cells = <3>;
	136	reg = <0xf9000000 0x1000>,
	137	<0xf9002000 0x1000>;
	138	};
	139
53ced99d AG	140	apcs: syscon@f9011000 {
	141	compatible = "syscon";
	142	reg = <0xf9011000 0x1000>;
	143	};
	144
975fd0f6 GD	145	timer@f9020000 {
	146	#address-cells = <1>;
	147	#size-cells = <1>;
	148	ranges;
	149	compatible = "arm,armv7-timer-mem";
	150	reg = <0xf9020000 0x1000>;
	151	clock-frequency = <19200000>;
	152
	153	frame@f9021000 {
	154	frame-number = <0>;
	155	interrupts = <0 8 0x4>,
	156	<0 7 0x4>;
	157	reg = <0xf9021000 0x1000>,
	158	<0xf9022000 0x1000>;
	159	};
	160
	161	frame@f9023000 {
	162	frame-number = <1>;
	163	interrupts = <0 9 0x4>;
	164	reg = <0xf9023000 0x1000>;
	165	status = "disabled";
	166	};
	167
	168	frame@f9024000 {
	169	frame-number = <2>;
	170	interrupts = <0 10 0x4>;
	171	reg = <0xf9024000 0x1000>;
	172	status = "disabled";
	173	};
	174
	175	frame@f9025000 {
	176	frame-number = <3>;
	177	interrupts = <0 11 0x4>;
	178	reg = <0xf9025000 0x1000>;
	179	status = "disabled";
	180	};
	181
	182	frame@f9026000 {
	183	frame-number = <4>;
	184	interrupts = <0 12 0x4>;
	185	reg = <0xf9026000 0x1000>;
	186	status = "disabled";
	187	};
	188
	189	frame@f9027000 {
	190	frame-number = <5>;
	191	interrupts = <0 13 0x4>;
	192	reg = <0xf9027000 0x1000>;
	193	status = "disabled";
	194	};
	195
	196	frame@f9028000 {
	197	frame-number = <6>;
	198	interrupts = <0 14 0x4>;
	199	reg = <0xf9028000 0x1000>;
	200	status = "disabled";
	201	};
	202	};
	203
030e27f6 LI	204	saw0: power-controller@f9089000 {
	205	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	206	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	207	};
	208
	209	saw1: power-controller@f9099000 {
	210	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	211	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	212	};
	213
	214	saw2: power-controller@f90a9000 {
	215	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	216	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	217	};
	218
	219	saw3: power-controller@f90b9000 {
	220	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	221	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	222	};
	223
	224	saw_l2: power-controller@f9012000 {
975fd0f6 GD	225	compatible = "qcom,saw2";
	226	reg = <0xf9012000 0x1000>;
	227	regulator;
	228	};
	229
	230	acc0: clock-controller@f9088000 {
	231	compatible = "qcom,kpss-acc-v2";
	232	reg = <0xf9088000 0x1000>,
	233	<0xf9008000 0x1000>;
	234	};
	235
	236	acc1: clock-controller@f9098000 {
	237	compatible = "qcom,kpss-acc-v2";
	238	reg = <0xf9098000 0x1000>,
	239	<0xf9008000 0x1000>;
	240	};
	241
	242	acc2: clock-controller@f90a8000 {
	243	compatible = "qcom,kpss-acc-v2";
	244	reg = <0xf90a8000 0x1000>,
	245	<0xf9008000 0x1000>;
	246	};
	247
	248	acc3: clock-controller@f90b8000 {
	249	compatible = "qcom,kpss-acc-v2";
	250	reg = <0xf90b8000 0x1000>,
	251	<0xf9008000 0x1000>;
	252	};
	253
	254	restart@fc4ab000 {
	255	compatible = "qcom,pshold";
	256	reg = <0xfc4ab000 0x4>;
	257	};
98a29533 GD	258
	259	gcc: clock-controller@fc400000 {
	260	compatible = "qcom,gcc-apq8084";
	261	#clock-cells = <1>;
	262	#reset-cells = <1>;
89c7e671	263	#power-domain-cells = <1>;
98a29533 GD	264	reg = <0xfc400000 0x4000>;
	265	};
	266
64ab8863 AG	267	tcsr_mutex_regs: syscon@fd484000 {
	268	compatible = "syscon";
	269	reg = <0xfd484000 0x2000>;
	270	};
	271
	272	tcsr_mutex: hwlock {
	273	compatible = "qcom,tcsr-mutex";
	274	syscon = <&tcsr_mutex_regs 0 0x80>;
	275	#hwlock-cells = <1>;
	276	};
	277
	278	rpm_msg_ram: memory@fc428000 {
	279	compatible = "qcom,rpm-msg-ram";
	280	reg = <0xfc428000 0x4000>;
	281	};
	282
44980b28 GD	283	tlmm: pinctrl@fd510000 {
	284	compatible = "qcom,apq8084-pinctrl";
	285	reg = <0xfd510000 0x4000>;
	286	gpio-controller;
	287	#gpio-cells = <2>;
	288	interrupt-controller;
	289	#interrupt-cells = <2>;
	290	interrupts = <0 208 0>;
	291	};
	292
10bfcfea	293	blsp2_uart2: serial@f995e000 {
14ff1c43 GD	294	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	295	reg = <0xf995e000 0x1000>;
	296	interrupts = <0 114 0x0>;
	297	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	298	clock-names = "core", "iface";
	299	status = "disabled";
	300	};
66c04e30 GD	301
	302	sdhci@f9824900 {
	303	compatible = "qcom,sdhci-msm-v4";
	304	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	305	reg-names = "hc_mem", "core_mem";
	306	interrupts = <0 123 0>, <0 138 0>;
	307	interrupt-names = "hc_irq", "pwr_irq";
	308	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	309	clock-names = "core", "iface";
	310	status = "disabled";
	311	};
	312
	313	sdhci@f98a4900 {
	314	compatible = "qcom,sdhci-msm-v4";
	315	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	316	reg-names = "hc_mem", "core_mem";
	317	interrupts = <0 125 0>, <0 221 0>;
	318	interrupt-names = "hc_irq", "pwr_irq";
	319	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	320	clock-names = "core", "iface";
	321	status = "disabled";
	322	};
af22e46d II	323
	324	spmi_bus: spmi@fc4cf000 {
	325	compatible = "qcom,spmi-pmic-arb";
	326	reg-names = "core", "intr", "cnfg";
	327	reg = <0xfc4cf000 0x1000>,
	328	<0xfc4cb000 0x1000>,
	329	<0xfc4ca000 0x1000>;
	330	interrupt-names = "periph_irq";
	331	interrupts = <0 190 0>;
	332	qcom,ee = <0>;
	333	qcom,channel = <0>;
	334	#address-cells = <2>;
	335	#size-cells = <0>;
	336	interrupt-controller;
	337	#interrupt-cells = <4>;
	338	};
975fd0f6	339	};
53ced99d AG	340
	341	smd {
	342	compatible = "qcom,smd";
	343
	344	rpm {
	345	interrupts = <0 168 1>;
	346	qcom,ipc = <&apcs 8 0>;
	347	qcom,smd-edge = <15>;
	348
	349	rpm_requests {
	350	compatible = "qcom,rpm-apq8084";
	351	qcom,smd-channels = "rpm_requests";
4add1074 AG	352
	353	pma8084-regulators {
	354	compatible = "qcom,rpm-pma8084-regulators";
	355
	356	pma8084_s1: s1 {};
	357	pma8084_s2: s2 {};
	358	pma8084_s3: s3 {};
	359	pma8084_s4: s4 {};
	360	pma8084_s5: s5 {};
	361	pma8084_s6: s6 {};
	362	pma8084_s7: s7 {};
	363	pma8084_s8: s8 {};
	364	pma8084_s9: s9 {};
	365	pma8084_s10: s10 {};
	366	pma8084_s11: s11 {};
	367	pma8084_s12: s12 {};
	368
	369	pma8084_l1: l1 {};
	370	pma8084_l2: l2 {};
	371	pma8084_l3: l3 {};
	372	pma8084_l4: l4 {};
	373	pma8084_l5: l5 {};
	374	pma8084_l6: l6 {};
	375	pma8084_l7: l7 {};
	376	pma8084_l8: l8 {};
	377	pma8084_l9: l9 {};
	378	pma8084_l10: l10 {};
	379	pma8084_l11: l11 {};
	380	pma8084_l12: l12 {};
	381	pma8084_l13: l13 {};
	382	pma8084_l14: l14 {};
	383	pma8084_l15: l15 {};
	384	pma8084_l16: l16 {};
	385	pma8084_l17: l17 {};
	386	pma8084_l18: l18 {};
	387	pma8084_l19: l19 {};
	388	pma8084_l20: l20 {};
	389	pma8084_l21: l21 {};
	390	pma8084_l22: l22 {};
	391	pma8084_l23: l23 {};
	392	pma8084_l24: l24 {};
	393	pma8084_l25: l25 {};
	394	pma8084_l26: l26 {};
	395	pma8084_l27: l27 {};
	396
	397	pma8084_lvs1: lvs1 {};
	398	pma8084_lvs2: lvs2 {};
	399	pma8084_lvs3: lvs3 {};
	400	pma8084_lvs4: lvs4 {};
	401
	402	pma8084_5vs1: 5vs1 {};
	403	};
53ced99d AG	404	};
	405	};
	406	};
975fd0f6	407	};