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bec6ba4c MM |
1 | /* |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | /dts-v1/; | |
15 | ||
16 | #include "skeleton.dtsi" | |
17 | #include <dt-bindings/clock/qcom,gcc-ipq4019.h> | |
13ad4fd3 MM |
18 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
19 | #include <dt-bindings/interrupt-controller/irq.h> | |
bec6ba4c MM |
20 | |
21 | / { | |
22 | model = "Qualcomm Technologies, Inc. IPQ4019"; | |
23 | compatible = "qcom,ipq4019"; | |
24 | interrupt-parent = <&intc>; | |
25 | ||
13ad4fd3 MM |
26 | aliases { |
27 | spi0 = &spi_0; | |
e76b4284 | 28 | i2c0 = &i2c_0; |
13ad4fd3 MM |
29 | }; |
30 | ||
bec6ba4c MM |
31 | cpus { |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | cpu@0 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
37 | enable-method = "qcom,kpss-acc-v1"; |
38 | qcom,acc = <&acc0>; | |
39 | qcom,saw = <&saw0>; | |
bec6ba4c MM |
40 | reg = <0x0>; |
41 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 42 | clock-frequency = <0>; |
15689ec2 MM |
43 | operating-points = < |
44 | /* kHz uV (fixed) */ | |
45 | 48000 1100000 | |
46 | 200000 1100000 | |
47 | 500000 1100000 | |
48 | 666000 1100000 | |
49 | >; | |
50 | clock-latency = <256000>; | |
bec6ba4c MM |
51 | }; |
52 | ||
53 | cpu@1 { | |
54 | device_type = "cpu"; | |
55 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
56 | enable-method = "qcom,kpss-acc-v1"; |
57 | qcom,acc = <&acc1>; | |
58 | qcom,saw = <&saw1>; | |
bec6ba4c MM |
59 | reg = <0x1>; |
60 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 61 | clock-frequency = <0>; |
bec6ba4c MM |
62 | }; |
63 | ||
64 | cpu@2 { | |
65 | device_type = "cpu"; | |
66 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
67 | enable-method = "qcom,kpss-acc-v1"; |
68 | qcom,acc = <&acc2>; | |
69 | qcom,saw = <&saw2>; | |
bec6ba4c MM |
70 | reg = <0x2>; |
71 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 72 | clock-frequency = <0>; |
bec6ba4c MM |
73 | }; |
74 | ||
75 | cpu@3 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a7"; | |
595b30c7 MM |
78 | enable-method = "qcom,kpss-acc-v1"; |
79 | qcom,acc = <&acc3>; | |
80 | qcom,saw = <&saw3>; | |
bec6ba4c MM |
81 | reg = <0x3>; |
82 | clocks = <&gcc GCC_APPS_CLK_SRC>; | |
595b30c7 | 83 | clock-frequency = <0>; |
bec6ba4c MM |
84 | }; |
85 | }; | |
86 | ||
87 | clocks { | |
88 | sleep_clk: sleep_clk { | |
89 | compatible = "fixed-clock"; | |
90 | clock-frequency = <32768>; | |
91 | #clock-cells = <0>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | soc { | |
96 | #address-cells = <1>; | |
97 | #size-cells = <1>; | |
98 | ranges; | |
99 | compatible = "simple-bus"; | |
100 | ||
101 | intc: interrupt-controller@b000000 { | |
102 | compatible = "qcom,msm-qgic2"; | |
103 | interrupt-controller; | |
104 | #interrupt-cells = <3>; | |
105 | reg = <0x0b000000 0x1000>, | |
106 | <0x0b002000 0x1000>; | |
107 | }; | |
108 | ||
109 | gcc: clock-controller@1800000 { | |
110 | compatible = "qcom,gcc-ipq4019"; | |
111 | #clock-cells = <1>; | |
112 | #reset-cells = <1>; | |
113 | reg = <0x1800000 0x60000>; | |
114 | }; | |
115 | ||
116 | tlmm: pinctrl@0x01000000 { | |
117 | compatible = "qcom,ipq4019-pinctrl"; | |
118 | reg = <0x01000000 0x300000>; | |
119 | gpio-controller; | |
120 | #gpio-cells = <2>; | |
121 | interrupt-controller; | |
122 | #interrupt-cells = <2>; | |
123 | interrupts = <0 208 0>; | |
124 | }; | |
125 | ||
9ca595f0 MM |
126 | blsp_dma: dma@7884000 { |
127 | compatible = "qcom,bam-v1.7.0"; | |
128 | reg = <0x07884000 0x23000>; | |
129 | interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; | |
130 | clocks = <&gcc GCC_BLSP1_AHB_CLK>; | |
131 | clock-names = "bam_clk"; | |
132 | #dma-cells = <1>; | |
133 | qcom,ee = <0>; | |
134 | status = "disabled"; | |
135 | }; | |
136 | ||
13ad4fd3 MM |
137 | spi_0: spi@78b5000 { |
138 | compatible = "qcom,spi-qup-v2.2.1"; | |
139 | reg = <0x78b5000 0x600>; | |
140 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
141 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
142 | <&gcc GCC_BLSP1_AHB_CLK>; | |
143 | clock-names = "core", "iface"; | |
144 | #address-cells = <1>; | |
145 | #size-cells = <0>; | |
146 | status = "disabled"; | |
147 | }; | |
148 | ||
e76b4284 MM |
149 | i2c_0: i2c@78b7000 { |
150 | compatible = "qcom,i2c-qup-v2.2.1"; | |
151 | reg = <0x78b7000 0x6000>; | |
152 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
153 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
154 | <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; | |
155 | clock-names = "iface", "core"; | |
156 | #address-cells = <1>; | |
157 | #size-cells = <0>; | |
158 | status = "disabled"; | |
159 | }; | |
160 | ||
fd6fd386 MM |
161 | |
162 | cryptobam: dma@8e04000 { | |
163 | compatible = "qcom,bam-v1.7.0"; | |
164 | reg = <0x08e04000 0x20000>; | |
165 | interrupts = <GIC_SPI 207 0>; | |
166 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>; | |
167 | clock-names = "bam_clk"; | |
168 | #dma-cells = <1>; | |
169 | qcom,ee = <1>; | |
170 | qcom,controlled-remotely; | |
171 | status = "disabled"; | |
172 | }; | |
173 | ||
174 | crypto@8e3a000 { | |
175 | compatible = "qcom,crypto-v5.1"; | |
176 | reg = <0x08e3a000 0x6000>; | |
177 | clocks = <&gcc GCC_CRYPTO_AHB_CLK>, | |
178 | <&gcc GCC_CRYPTO_AXI_CLK>, | |
179 | <&gcc GCC_CRYPTO_CLK>; | |
180 | clock-names = "iface", "bus", "core"; | |
181 | dmas = <&cryptobam 2>, <&cryptobam 3>; | |
182 | dma-names = "rx", "tx"; | |
183 | status = "disabled"; | |
184 | }; | |
185 | ||
595b30c7 MM |
186 | acc0: clock-controller@b088000 { |
187 | compatible = "qcom,kpss-acc-v1"; | |
188 | reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; | |
189 | }; | |
190 | ||
191 | acc1: clock-controller@b098000 { | |
192 | compatible = "qcom,kpss-acc-v1"; | |
193 | reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; | |
194 | }; | |
195 | ||
196 | acc2: clock-controller@b0a8000 { | |
197 | compatible = "qcom,kpss-acc-v1"; | |
198 | reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; | |
199 | }; | |
200 | ||
201 | acc3: clock-controller@b0b8000 { | |
202 | compatible = "qcom,kpss-acc-v1"; | |
203 | reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; | |
204 | }; | |
205 | ||
206 | saw0: regulator@b089000 { | |
207 | compatible = "qcom,saw2"; | |
208 | reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; | |
209 | regulator; | |
210 | }; | |
211 | ||
212 | saw1: regulator@b099000 { | |
213 | compatible = "qcom,saw2"; | |
214 | reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; | |
215 | regulator; | |
216 | }; | |
217 | ||
218 | saw2: regulator@b0a9000 { | |
219 | compatible = "qcom,saw2"; | |
220 | reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; | |
221 | regulator; | |
222 | }; | |
223 | ||
224 | saw3: regulator@b0b9000 { | |
225 | compatible = "qcom,saw2"; | |
226 | reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; | |
227 | regulator; | |
228 | }; | |
229 | ||
bec6ba4c MM |
230 | serial@78af000 { |
231 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
232 | reg = <0x78af000 0x200>; | |
233 | interrupts = <0 107 0>; | |
234 | status = "disabled"; | |
235 | clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, | |
236 | <&gcc GCC_BLSP1_AHB_CLK>; | |
237 | clock-names = "core", "iface"; | |
9ca595f0 MM |
238 | dmas = <&blsp_dma 1>, <&blsp_dma 0>; |
239 | dma-names = "rx", "tx"; | |
bec6ba4c MM |
240 | }; |
241 | ||
242 | serial@78b0000 { | |
243 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
244 | reg = <0x78b0000 0x200>; | |
245 | interrupts = <0 108 0>; | |
246 | status = "disabled"; | |
247 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
248 | <&gcc GCC_BLSP1_AHB_CLK>; | |
249 | clock-names = "core", "iface"; | |
9ca595f0 MM |
250 | dmas = <&blsp_dma 3>, <&blsp_dma 2>; |
251 | dma-names = "rx", "tx"; | |
bec6ba4c | 252 | }; |
40057afd MM |
253 | |
254 | watchdog@b017000 { | |
255 | compatible = "qcom,kpss-standalone"; | |
256 | reg = <0xb017000 0x40>; | |
257 | clocks = <&sleep_clk>; | |
258 | timeout-sec = <10>; | |
259 | status = "disabled"; | |
260 | }; | |
8196dd5e MM |
261 | |
262 | restart@4ab000 { | |
263 | compatible = "qcom,pshold"; | |
264 | reg = <0x4ab000 0x4>; | |
265 | }; | |
bec6ba4c MM |
266 | }; |
267 | }; |