Commit | Line | Data |
---|---|---|
cc60a1a4 KG |
1 | /dts-v1/; |
2 | ||
3 | /include/ "skeleton.dtsi" | |
4 | ||
55602a09 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
cc60a1a4 | 6 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> |
66a6c317 | 7 | #include <dt-bindings/soc/qcom,gsbi.h> |
cc60a1a4 KG |
8 | |
9 | / { | |
10 | model = "Qualcomm MSM8660"; | |
11 | compatible = "qcom,msm8660"; | |
12 | interrupt-parent = <&intc>; | |
13 | ||
2ab27991 RV |
14 | cpus { |
15 | #address-cells = <1>; | |
16 | #size-cells = <0>; | |
2ab27991 RV |
17 | |
18 | cpu@0 { | |
66a6c317 KG |
19 | compatible = "qcom,scorpion"; |
20 | enable-method = "qcom,gcc-msm8660"; | |
2ab27991 RV |
21 | device_type = "cpu"; |
22 | reg = <0>; | |
23 | next-level-cache = <&L2>; | |
24 | }; | |
25 | ||
26 | cpu@1 { | |
66a6c317 KG |
27 | compatible = "qcom,scorpion"; |
28 | enable-method = "qcom,gcc-msm8660"; | |
2ab27991 RV |
29 | device_type = "cpu"; |
30 | reg = <1>; | |
31 | next-level-cache = <&L2>; | |
32 | }; | |
33 | ||
34 | L2: l2-cache { | |
35 | compatible = "cache"; | |
36 | cache-level = <2>; | |
37 | }; | |
38 | }; | |
39 | ||
b73b3157 SB |
40 | cpu-pmu { |
41 | compatible = "qcom,scorpion-mp-pmu"; | |
42 | interrupts = <1 9 0x304>; | |
43 | }; | |
44 | ||
30fc4212 SB |
45 | clocks { |
46 | cxo_board { | |
47 | compatible = "fixed-clock"; | |
48 | #clock-cells = <0>; | |
49 | clock-frequency = <19200000>; | |
50 | }; | |
51 | ||
52 | pxo_board { | |
53 | compatible = "fixed-clock"; | |
54 | #clock-cells = <0>; | |
55 | clock-frequency = <27000000>; | |
56 | }; | |
57 | ||
58 | sleep_clk { | |
59 | compatible = "fixed-clock"; | |
60 | #clock-cells = <0>; | |
61 | clock-frequency = <32768>; | |
62 | }; | |
63 | }; | |
64 | ||
66a6c317 KG |
65 | soc: soc { |
66 | #address-cells = <1>; | |
67 | #size-cells = <1>; | |
68 | ranges; | |
69 | compatible = "simple-bus"; | |
cc60a1a4 | 70 | |
66a6c317 KG |
71 | intc: interrupt-controller@2080000 { |
72 | compatible = "qcom,msm-8660-qgic"; | |
73 | interrupt-controller; | |
74 | #interrupt-cells = <3>; | |
75 | reg = < 0x02080000 0x1000 >, | |
76 | < 0x02081000 0x1000 >; | |
77 | }; | |
cc60a1a4 | 78 | |
66a6c317 KG |
79 | timer@2000000 { |
80 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | |
81 | interrupts = <1 0 0x301>, | |
82 | <1 1 0x301>, | |
83 | <1 2 0x301>; | |
84 | reg = <0x02000000 0x100>; | |
85 | clock-frequency = <27000000>, | |
86 | <32768>; | |
87 | cpu-offset = <0x40000>; | |
88 | }; | |
cc60a1a4 | 89 | |
8e140c8e BA |
90 | tlmm: pinctrl@800000 { |
91 | compatible = "qcom,msm8660-pinctrl"; | |
92 | reg = <0x800000 0x4000>; | |
93 | ||
66a6c317 KG |
94 | gpio-controller; |
95 | #gpio-cells = <2>; | |
66a6c317 KG |
96 | interrupts = <0 16 0x4>; |
97 | interrupt-controller; | |
98 | #interrupt-cells = <2>; | |
8e140c8e | 99 | |
66a6c317 | 100 | }; |
cc60a1a4 | 101 | |
66a6c317 KG |
102 | gcc: clock-controller@900000 { |
103 | compatible = "qcom,gcc-msm8660"; | |
104 | #clock-cells = <1>; | |
105 | #reset-cells = <1>; | |
106 | reg = <0x900000 0x4000>; | |
107 | }; | |
108 | ||
109 | gsbi12: gsbi@19c00000 { | |
110 | compatible = "qcom,gsbi-v1.0.0"; | |
da047acd | 111 | cell-index = <12>; |
66a6c317 KG |
112 | reg = <0x19c00000 0x100>; |
113 | clocks = <&gcc GSBI12_H_CLK>; | |
114 | clock-names = "iface"; | |
115 | #address-cells = <1>; | |
116 | #size-cells = <1>; | |
117 | ranges; | |
cc60a1a4 | 118 | |
da047acd AG |
119 | syscon-tcsr = <&tcsr>; |
120 | ||
10bfcfea | 121 | gsbi12_serial: serial@19c40000 { |
66a6c317 KG |
122 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
123 | reg = <0x19c40000 0x1000>, | |
124 | <0x19c00000 0x1000>; | |
125 | interrupts = <0 195 0x0>; | |
126 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | |
127 | clock-names = "core", "iface"; | |
128 | status = "disabled"; | |
129 | }; | |
130 | }; | |
131 | ||
132 | qcom,ssbi@500000 { | |
133 | compatible = "qcom,ssbi"; | |
134 | reg = <0x500000 0x1000>; | |
135 | qcom,controller-type = "pmic-arbiter"; | |
94ae991d SB |
136 | |
137 | pmicintc: pmic@0 { | |
138 | compatible = "qcom,pm8058"; | |
8e140c8e | 139 | interrupt-parent = <&tlmm>; |
94ae991d SB |
140 | interrupts = <88 8>; |
141 | #interrupt-cells = <2>; | |
142 | interrupt-controller; | |
143 | #address-cells = <1>; | |
144 | #size-cells = <0>; | |
145 | ||
0840ea9e LW |
146 | pm8058_gpio: gpio@150 { |
147 | compatible = "qcom,pm8058-gpio", | |
148 | "qcom,ssbi-gpio"; | |
149 | reg = <0x150>; | |
150 | interrupt-parent = <&pmicintc>; | |
151 | interrupts = <192 1>, <193 1>, <194 1>, | |
152 | <195 1>, <196 1>, <197 1>, | |
153 | <198 1>, <199 1>, <200 1>, | |
154 | <201 1>, <202 1>, <203 1>, | |
155 | <204 1>, <205 1>, <206 1>, | |
156 | <207 1>, <208 1>, <209 1>, | |
157 | <210 1>, <211 1>, <212 1>, | |
158 | <213 1>, <214 1>, <215 1>, | |
159 | <216 1>, <217 1>, <218 1>, | |
160 | <219 1>, <220 1>, <221 1>, | |
161 | <222 1>, <223 1>, <224 1>, | |
162 | <225 1>, <226 1>, <227 1>, | |
163 | <228 1>, <229 1>, <230 1>, | |
164 | <231 1>, <232 1>, <233 1>, | |
165 | <234 1>, <235 1>; | |
166 | gpio-controller; | |
167 | #gpio-cells = <2>; | |
168 | ||
169 | }; | |
170 | ||
171 | pm8058_mpps: mpps@50 { | |
172 | compatible = "qcom,pm8058-mpp", | |
173 | "qcom,ssbi-mpp"; | |
174 | reg = <0x50>; | |
175 | gpio-controller; | |
176 | #gpio-cells = <2>; | |
177 | interrupt-parent = <&pmicintc>; | |
178 | interrupts = | |
179 | <128 1>, <129 1>, <130 1>, <131 1>, | |
180 | <132 1>, <133 1>, <134 1>, <135 1>, | |
181 | <136 1>, <137 1>, <138 1>, <139 1>; | |
182 | }; | |
183 | ||
94ae991d SB |
184 | pwrkey@1c { |
185 | compatible = "qcom,pm8058-pwrkey"; | |
186 | reg = <0x1c>; | |
187 | interrupt-parent = <&pmicintc>; | |
188 | interrupts = <50 1>, <51 1>; | |
189 | debounce = <15625>; | |
190 | pull-up; | |
191 | }; | |
192 | ||
193 | keypad@148 { | |
194 | compatible = "qcom,pm8058-keypad"; | |
195 | reg = <0x148>; | |
196 | interrupt-parent = <&pmicintc>; | |
197 | interrupts = <74 1>, <75 1>; | |
198 | debounce = <15>; | |
199 | scan-delay = <32>; | |
200 | row-hold = <91500>; | |
201 | }; | |
202 | ||
203 | rtc@11d { | |
204 | compatible = "qcom,pm8058-rtc"; | |
205 | interrupt-parent = <&pmicintc>; | |
206 | interrupts = <39 1>; | |
207 | reg = <0x11d>; | |
208 | allow-set-time; | |
209 | }; | |
210 | ||
211 | vibrator@4a { | |
212 | compatible = "qcom,pm8058-vib"; | |
213 | reg = <0x4a>; | |
214 | }; | |
215 | }; | |
66a6c317 | 216 | }; |
55602a09 SB |
217 | |
218 | /* Temporary fixed regulator */ | |
219 | vsdcc_fixed: vsdcc-regulator { | |
220 | compatible = "regulator-fixed"; | |
221 | regulator-name = "SDCC Power"; | |
222 | regulator-min-microvolt = <2700000>; | |
223 | regulator-max-microvolt = <2700000>; | |
224 | regulator-always-on; | |
225 | }; | |
226 | ||
227 | amba { | |
2ef7d5f3 | 228 | compatible = "simple-bus"; |
55602a09 SB |
229 | #address-cells = <1>; |
230 | #size-cells = <1>; | |
231 | ranges; | |
232 | sdcc1: sdcc@12400000 { | |
233 | status = "disabled"; | |
234 | compatible = "arm,pl18x", "arm,primecell"; | |
235 | arm,primecell-periphid = <0x00051180>; | |
236 | reg = <0x12400000 0x8000>; | |
237 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
238 | interrupt-names = "cmd_irq"; | |
239 | clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; | |
240 | clock-names = "mclk", "apb_pclk"; | |
241 | bus-width = <8>; | |
242 | max-frequency = <48000000>; | |
243 | non-removable; | |
244 | cap-sd-highspeed; | |
245 | cap-mmc-highspeed; | |
246 | vmmc-supply = <&vsdcc_fixed>; | |
247 | }; | |
248 | ||
249 | sdcc3: sdcc@12180000 { | |
250 | compatible = "arm,pl18x", "arm,primecell"; | |
251 | arm,primecell-periphid = <0x00051180>; | |
252 | status = "disabled"; | |
253 | reg = <0x12180000 0x8000>; | |
254 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
255 | interrupt-names = "cmd_irq"; | |
256 | clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; | |
257 | clock-names = "mclk", "apb_pclk"; | |
258 | bus-width = <4>; | |
259 | cap-sd-highspeed; | |
260 | cap-mmc-highspeed; | |
261 | max-frequency = <48000000>; | |
262 | no-1-8-v; | |
263 | vmmc-supply = <&vsdcc_fixed>; | |
264 | }; | |
265 | }; | |
da047acd AG |
266 | |
267 | tcsr: syscon@1a400000 { | |
268 | compatible = "qcom,tcsr-msm8660", "syscon"; | |
269 | reg = <0x1a400000 0x100>; | |
270 | }; | |
cc60a1a4 | 271 | }; |
55602a09 | 272 | |
cc60a1a4 | 273 | }; |