[deliverable/linux.git] / arch / arm / boot / dts / qcom-msm8660.dtsi

/dts-v1/;

/include/ "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	model = "Qualcomm MSM8660";
	compatible = "qcom,msm8660";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu-pmu {
		compatible = "qcom,scorpion-mp-pmu";
		interrupts = <1 9 0x304>;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@2080000 {
			compatible = "qcom,msm-8660-qgic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = < 0x02080000 0x1000 >,
			      < 0x02081000 0x1000 >;
		};

		timer@2000000 {
			compatible = "qcom,scss-timer", "qcom,msm-timer";
			interrupts = <1 0 0x301>,
				     <1 1 0x301>,
				     <1 2 0x301>;
			reg = <0x02000000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x40000>;
		};

		tlmm: pinctrl@800000 {
			compatible = "qcom,msm8660-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 16 0x4>;
			interrupt-controller;
			#interrupt-cells = <2>;

		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-msm8660";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
		};

		gsbi12: gsbi@19c00000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x19c00000 0x100>;
			clocks = <&gcc GSBI12_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi12_serial: serial@19c40000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x19c40000 0x1000>,
				      <0x19c00000 0x1000>;
				interrupts = <0 195 0x0>;
				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8058";
				interrupt-parent = <&tlmm>;
				interrupts = <88 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8058_gpio: gpio@150 {
					compatible = "qcom,pm8058-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupt-parent = <&pmicintc>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;
					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8058_mpps: mpps@50 {
					compatible = "qcom,pm8058-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-parent = <&pmicintc>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

				pwrkey@1c {
					compatible = "qcom,pm8058-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};

				keypad@148 {
					compatible = "qcom,pm8058-keypad";
					reg = <0x148>;
					interrupt-parent = <&pmicintc>;
					interrupts = <74 1>, <75 1>;
					debounce = <15>;
					scan-delay = <32>;
					row-hold = <91500>;
				};

				rtc@11d {
					compatible = "qcom,pm8058-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};

				vibrator@4a {
					compatible = "qcom,pm8058-vib";
					reg = <0x4a>;
				};
			};
		};

		l2cc: clock-controller@2082000 {
			compatible	= "syscon";
			reg		= <0x02082000 0x1000>;
		};

		rpm: rpm@104000 {
			compatible	= "qcom,rpm-msm8660";
			reg		= <0x00104000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";
			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
			clock-names = "ram";

			rpmcc: clock-controller {
				compatible	= "qcom,rpmcc-apq8660", "qcom,rpmcc";
				#clock-cells = <1>;
			};

			pm8901-regulators {
				compatible = "qcom,rpm-pm8901-regulators";

				pm8901_l0: l0 {};
				pm8901_l1: l1 {};
				pm8901_l2: l2 {};
				pm8901_l3: l3 {};
				pm8901_l4: l4 {};
				pm8901_l5: l5 {};
				pm8901_l6: l6 {};

				/* S0 and S1 Handled as SAW regulators by SPM */
				pm8901_s2: s2 {};
				pm8901_s3: s3 {};
				pm8901_s4: s4 {};

				pm8901_lvs0: lvs0 {};
				pm8901_lvs1: lvs1 {};
				pm8901_lvs2: lvs2 {};
				pm8901_lvs3: lvs3 {};

				pm8901_mvs: mvs {};
			};

			pm8058-regulators {
				compatible = "qcom,rpm-pm8058-regulators";

				pm8058_l0: l0 {};
				pm8058_l1: l1 {};
				pm8058_l2: l2 {};
				pm8058_l3: l3 {};
				pm8058_l4: l4 {};
				pm8058_l5: l5 {};
				pm8058_l6: l6 {};
				pm8058_l7: l7 {};
				pm8058_l8: l8 {};
				pm8058_l9: l9 {};
				pm8058_l10: l10 {};
				pm8058_l11: l11 {};
				pm8058_l12: l12 {};
				pm8058_l13: l13 {};
				pm8058_l14: l14 {};
				pm8058_l15: l15 {};
				pm8058_l16: l16 {};
				pm8058_l17: l17 {};
				pm8058_l18: l18 {};
				pm8058_l19: l19 {};
				pm8058_l20: l20 {};
				pm8058_l21: l21 {};
				pm8058_l22: l22 {};
				pm8058_l23: l23 {};
				pm8058_l24: l24 {};
				pm8058_l25: l25 {};

				pm8058_s0: s0 {};
				pm8058_s1: s1 {};
				pm8058_s2: s2 {};
				pm8058_s3: s3 {};
				pm8058_s4: s4 {};

				pm8058_lvs0: lvs0 {};
				pm8058_lvs1: lvs1 {};

				pm8058_ncp: ncp {};
			};
		};

		/* Temporary fixed regulator */
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x8000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <48000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x8000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				no-1-8-v;
				vmmc-supply = <&vsdcc_fixed>;
			};

			sdcc5: sdcc@12200000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12200000 0x8000>;
				interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				vmmc-supply = <&vsdcc_fixed>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-msm8660", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};

};
Commit	Line	Data
cc60a1a4 KG	1	/dts-v1/;
	2
	3	/include/ "skeleton.dtsi"
	4
55602a09	5	#include <dt-bindings/interrupt-controller/arm-gic.h>
cc60a1a4	6	#include <dt-bindings/clock/qcom,gcc-msm8660.h>
66a6c317	7	#include <dt-bindings/soc/qcom,gsbi.h>
cc60a1a4 KG	8
	9	/ {
	10	model = "Qualcomm MSM8660";
	11	compatible = "qcom,msm8660";
	12	interrupt-parent = <&intc>;
	13
2ab27991 RV	14	cpus {
	15	#address-cells = <1>;
	16	#size-cells = <0>;
2ab27991 RV	17
2ab27991 RV	18	cpu@0 {
66a6c317 KG	19	compatible = "qcom,scorpion";
66a6c317 KG	20	enable-method = "qcom,gcc-msm8660";
2ab27991 RV	21	device_type = "cpu";
	22	reg = <0>;
	23	next-level-cache = <&L2>;
	24	};
	25
	26	cpu@1 {
66a6c317 KG	27	compatible = "qcom,scorpion";
66a6c317 KG	28	enable-method = "qcom,gcc-msm8660";
2ab27991 RV	29	device_type = "cpu";
	30	reg = <1>;
	31	next-level-cache = <&L2>;
	32	};
	33
	34	L2: l2-cache {
	35	compatible = "cache";
	36	cache-level = <2>;
	37	};
	38	};
	39
b73b3157 SB	40	cpu-pmu {
	41	compatible = "qcom,scorpion-mp-pmu";
	42	interrupts = <1 9 0x304>;
	43	};
	44
30fc4212 SB	45	clocks {
	46	cxo_board {
	47	compatible = "fixed-clock";
	48	#clock-cells = <0>;
	49	clock-frequency = <19200000>;
	50	};
	51
	52	pxo_board {
	53	compatible = "fixed-clock";
	54	#clock-cells = <0>;
	55	clock-frequency = <27000000>;
	56	};
	57
	58	sleep_clk {
	59	compatible = "fixed-clock";
	60	#clock-cells = <0>;
	61	clock-frequency = <32768>;
	62	};
	63	};
	64
66a6c317 KG	65	soc: soc {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	ranges;
	69	compatible = "simple-bus";
cc60a1a4	70
66a6c317 KG	71	intc: interrupt-controller@2080000 {
	72	compatible = "qcom,msm-8660-qgic";
	73	interrupt-controller;
	74	#interrupt-cells = <3>;
	75	reg = < 0x02080000 0x1000 >,
	76	< 0x02081000 0x1000 >;
	77	};
cc60a1a4	78
66a6c317 KG	79	timer@2000000 {
	80	compatible = "qcom,scss-timer", "qcom,msm-timer";
	81	interrupts = <1 0 0x301>,
	82	<1 1 0x301>,
	83	<1 2 0x301>;
	84	reg = <0x02000000 0x100>;
	85	clock-frequency = <27000000>,
	86	<32768>;
	87	cpu-offset = <0x40000>;
	88	};
cc60a1a4	89
8e140c8e BA	90	tlmm: pinctrl@800000 {
	91	compatible = "qcom,msm8660-pinctrl";
	92	reg = <0x800000 0x4000>;
	93
66a6c317 KG	94	gpio-controller;
66a6c317 KG	95	#gpio-cells = <2>;
66a6c317 KG	96	interrupts = <0 16 0x4>;
	97	interrupt-controller;
	98	#interrupt-cells = <2>;
8e140c8e	99
66a6c317	100	};
cc60a1a4	101
66a6c317 KG	102	gcc: clock-controller@900000 {
	103	compatible = "qcom,gcc-msm8660";
	104	#clock-cells = <1>;
	105	#reset-cells = <1>;
	106	reg = <0x900000 0x4000>;
	107	};
	108
	109	gsbi12: gsbi@19c00000 {
	110	compatible = "qcom,gsbi-v1.0.0";
da047acd	111	cell-index = <12>;
66a6c317 KG	112	reg = <0x19c00000 0x100>;
	113	clocks = <&gcc GSBI12_H_CLK>;
	114	clock-names = "iface";
	115	#address-cells = <1>;
	116	#size-cells = <1>;
	117	ranges;
cc60a1a4	118
da047acd AG	119	syscon-tcsr = <&tcsr>;
da047acd AG	120
10bfcfea	121	gsbi12_serial: serial@19c40000 {
66a6c317 KG	122	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	123	reg = <0x19c40000 0x1000>,
	124	<0x19c00000 0x1000>;
	125	interrupts = <0 195 0x0>;
	126	clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
	127	clock-names = "core", "iface";
	128	status = "disabled";
	129	};
	130	};
	131
	132	qcom,ssbi@500000 {
	133	compatible = "qcom,ssbi";
	134	reg = <0x500000 0x1000>;
	135	qcom,controller-type = "pmic-arbiter";
94ae991d SB	136
	137	pmicintc: pmic@0 {
	138	compatible = "qcom,pm8058";
8e140c8e	139	interrupt-parent = <&tlmm>;
94ae991d SB	140	interrupts = <88 8>;
	141	#interrupt-cells = <2>;
	142	interrupt-controller;
	143	#address-cells = <1>;
	144	#size-cells = <0>;
	145
0840ea9e LW	146	pm8058_gpio: gpio@150 {
	147	compatible = "qcom,pm8058-gpio",
	148	"qcom,ssbi-gpio";
	149	reg = <0x150>;
	150	interrupt-parent = <&pmicintc>;
	151	interrupts = <192 1>, <193 1>, <194 1>,
	152	<195 1>, <196 1>, <197 1>,
	153	<198 1>, <199 1>, <200 1>,
	154	<201 1>, <202 1>, <203 1>,
	155	<204 1>, <205 1>, <206 1>,
	156	<207 1>, <208 1>, <209 1>,
	157	<210 1>, <211 1>, <212 1>,
	158	<213 1>, <214 1>, <215 1>,
	159	<216 1>, <217 1>, <218 1>,
	160	<219 1>, <220 1>, <221 1>,
	161	<222 1>, <223 1>, <224 1>,
	162	<225 1>, <226 1>, <227 1>,
	163	<228 1>, <229 1>, <230 1>,
	164	<231 1>, <232 1>, <233 1>,
	165	<234 1>, <235 1>;
	166	gpio-controller;
	167	#gpio-cells = <2>;
	168
	169	};
	170
	171	pm8058_mpps: mpps@50 {
	172	compatible = "qcom,pm8058-mpp",
	173	"qcom,ssbi-mpp";
	174	reg = <0x50>;
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	interrupt-parent = <&pmicintc>;
	178	interrupts =
	179	<128 1>, <129 1>, <130 1>, <131 1>,
	180	<132 1>, <133 1>, <134 1>, <135 1>,
	181	<136 1>, <137 1>, <138 1>, <139 1>;
	182	};
	183
94ae991d SB	184	pwrkey@1c {
	185	compatible = "qcom,pm8058-pwrkey";
	186	reg = <0x1c>;
	187	interrupt-parent = <&pmicintc>;
	188	interrupts = <50 1>, <51 1>;
	189	debounce = <15625>;
	190	pull-up;
	191	};
	192
	193	keypad@148 {
	194	compatible = "qcom,pm8058-keypad";
	195	reg = <0x148>;
	196	interrupt-parent = <&pmicintc>;
	197	interrupts = <74 1>, <75 1>;
	198	debounce = <15>;
	199	scan-delay = <32>;
	200	row-hold = <91500>;
	201	};
	202
	203	rtc@11d {
	204	compatible = "qcom,pm8058-rtc";
	205	interrupt-parent = <&pmicintc>;
	206	interrupts = <39 1>;
	207	reg = <0x11d>;
	208	allow-set-time;
	209	};
	210
	211	vibrator@4a {
	212	compatible = "qcom,pm8058-vib";
	213	reg = <0x4a>;
	214	};
	215	};
66a6c317	216	};
55602a09	217
30b4fb1c LW	218	l2cc: clock-controller@2082000 {
	219	compatible = "syscon";
	220	reg = <0x02082000 0x1000>;
	221	};
	222
	223	rpm: rpm@104000 {
	224	compatible = "qcom,rpm-msm8660";
	225	reg = <0x00104000 0x1000>;
	226	qcom,ipc = <&l2cc 0x8 2>;
	227
	228	interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
	229	<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
	230	<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
	231	interrupt-names = "ack", "err", "wakeup";
	232	clocks = <&gcc RPM_MSG_RAM_H_CLK>;
	233	clock-names = "ram";
	234
	235	rpmcc: clock-controller {
	236	compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
	237	#clock-cells = <1>;
	238	};
	239
	240	pm8901-regulators {
	241	compatible = "qcom,rpm-pm8901-regulators";
	242
	243	pm8901_l0: l0 {};
	244	pm8901_l1: l1 {};
	245	pm8901_l2: l2 {};
	246	pm8901_l3: l3 {};
	247	pm8901_l4: l4 {};
	248	pm8901_l5: l5 {};
	249	pm8901_l6: l6 {};
	250
	251	/* S0 and S1 Handled as SAW regulators by SPM */
	252	pm8901_s2: s2 {};
	253	pm8901_s3: s3 {};
	254	pm8901_s4: s4 {};
	255
	256	pm8901_lvs0: lvs0 {};
	257	pm8901_lvs1: lvs1 {};
	258	pm8901_lvs2: lvs2 {};
	259	pm8901_lvs3: lvs3 {};
	260
	261	pm8901_mvs: mvs {};
	262	};
	263
	264	pm8058-regulators {
	265	compatible = "qcom,rpm-pm8058-regulators";
	266
	267	pm8058_l0: l0 {};
	268	pm8058_l1: l1 {};
	269	pm8058_l2: l2 {};
	270	pm8058_l3: l3 {};
	271	pm8058_l4: l4 {};
	272	pm8058_l5: l5 {};
	273	pm8058_l6: l6 {};
	274	pm8058_l7: l7 {};
	275	pm8058_l8: l8 {};
	276	pm8058_l9: l9 {};
	277	pm8058_l10: l10 {};
	278	pm8058_l11: l11 {};
	279	pm8058_l12: l12 {};
	280	pm8058_l13: l13 {};
	281	pm8058_l14: l14 {};
282	pm8058_l15: l15 {};
283	pm8058_l16: l16 {};
284	pm8058_l17: l17 {};
285	pm8058_l18: l18 {};
286	pm8058_l19: l19 {};
287	pm8058_l20: l20 {};
288	pm8058_l21: l21 {};
289	pm8058_l22: l22 {};
290	pm8058_l23: l23 {};
291	pm8058_l24: l24 {};
292	pm8058_l25: l25 {};
293
294	pm8058_s0: s0 {};
295	pm8058_s1: s1 {};
296	pm8058_s2: s2 {};
297	pm8058_s3: s3 {};
298	pm8058_s4: s4 {};
299
300	pm8058_lvs0: lvs0 {};
301	pm8058_lvs1: lvs1 {};
302
303	pm8058_ncp: ncp {};
304	};
305	};
306
55602a09 SB	307	/* Temporary fixed regulator */
	308	vsdcc_fixed: vsdcc-regulator {
	309	compatible = "regulator-fixed";
	310	regulator-name = "SDCC Power";
	311	regulator-min-microvolt = <2700000>;
	312	regulator-max-microvolt = <2700000>;
	313	regulator-always-on;
	314	};
	315
	316	amba {
2ef7d5f3	317	compatible = "simple-bus";
55602a09 SB	318	#address-cells = <1>;
	319	#size-cells = <1>;
	320	ranges;
	321	sdcc1: sdcc@12400000 {
	322	status = "disabled";
	323	compatible = "arm,pl18x", "arm,primecell";
	324	arm,primecell-periphid = <0x00051180>;
	325	reg = <0x12400000 0x8000>;
	326	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	327	interrupt-names = "cmd_irq";
	328	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	329	clock-names = "mclk", "apb_pclk";
	330	bus-width = <8>;
	331	max-frequency = <48000000>;
	332	non-removable;
	333	cap-sd-highspeed;
	334	cap-mmc-highspeed;
	335	vmmc-supply = <&vsdcc_fixed>;
	336	};
	337
	338	sdcc3: sdcc@12180000 {
	339	compatible = "arm,pl18x", "arm,primecell";
	340	arm,primecell-periphid = <0x00051180>;
	341	status = "disabled";
	342	reg = <0x12180000 0x8000>;
	343	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	344	interrupt-names = "cmd_irq";
	345	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	346	clock-names = "mclk", "apb_pclk";
	347	bus-width = <4>;
	348	cap-sd-highspeed;
	349	cap-mmc-highspeed;
	350	max-frequency = <48000000>;
	351	no-1-8-v;
	352	vmmc-supply = <&vsdcc_fixed>;
	353	};
5f761007 LW	354
	355	sdcc5: sdcc@12200000 {
	356	compatible = "arm,pl18x", "arm,primecell";
	357	arm,primecell-periphid = <0x00051180>;
	358	status = "disabled";
	359	reg = <0x12200000 0x8000>;
	360	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	361	interrupt-names = "cmd_irq";
	362	clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
	363	clock-names = "mclk", "apb_pclk";
	364	bus-width = <4>;
	365	cap-sd-highspeed;
	366	cap-mmc-highspeed;
	367	max-frequency = <48000000>;
	368	vmmc-supply = <&vsdcc_fixed>;
	369	};
55602a09	370	};
da047acd AG	371
	372	tcsr: syscon@1a400000 {
	373	compatible = "qcom,tcsr-msm8660", "syscon";
	374	reg = <0x1a400000 0x100>;
	375	};
cc60a1a4	376	};
55602a09	377
cc60a1a4	378	};