projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cc60a1a4 KG |
1 | /dts-v1/; |
| 2 | ||
| 3 | /include/ "skeleton.dtsi" | |
| 4 | ||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
| 6 | ||
| 7 | / { | |
| 8 | model = "Qualcomm MSM8960"; | |
| 9 | compatible = "qcom,msm8960"; | |
| 10 | interrupt-parent = <&intc>; | |
| 11 | ||
| 2ab27991 RV |
12 | cpus { |
| 13 | #address-cells = <1>; | |
| 14 | #size-cells = <0>; | |
| 15 | interrupts = <1 14 0x304>; | |
| 16 | compatible = "qcom,krait"; | |
| 17 | enable-method = "qcom,kpss-acc-v1"; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | device_type = "cpu"; | |
| 21 | reg = <0>; | |
| 22 | next-level-cache = <&L2>; | |
| 23 | qcom,acc = <&acc0>; | |
| 24 | qcom,saw = <&saw0>; | |
| 25 | }; | |
| 26 | ||
| 27 | cpu@1 { | |
| 28 | device_type = "cpu"; | |
| 29 | reg = <1>; | |
| 30 | next-level-cache = <&L2>; | |
| 31 | qcom,acc = <&acc1>; | |
| 32 | qcom,saw = <&saw1>; | |
| 33 | }; | |
| 34 | ||
| 35 | L2: l2-cache { | |
| 36 | compatible = "cache"; | |
| 37 | cache-level = <2>; | |
| 38 | interrupts = <0 2 0x4>; | |
| 39 | }; | |
| 40 | }; | |
| 41 | ||
| cc60a1a4 KG |
42 | intc: interrupt-controller@2000000 { |
| 43 | compatible = "qcom,msm-qgic2"; | |
| 44 | interrupt-controller; | |
| 45 | #interrupt-cells = <3>; | |
| 46 | reg = < 0x02000000 0x1000 >, | |
| 47 | < 0x02002000 0x1000 >; | |
| 48 | }; | |
| 49 | ||
| 50 | timer@200a000 { | |
| 51 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
| 52 | interrupts = <1 1 0x301>, | |
| 53 | <1 2 0x301>, | |
| 54 | <1 3 0x301>; | |
| 55 | reg = <0x0200a000 0x100>; | |
| 56 | clock-frequency = <27000000>, | |
| 57 | <32768>; | |
| 58 | cpu-offset = <0x80000>; | |
| 59 | }; | |
| 60 | ||
| 61 | msmgpio: gpio@800000 { | |
| 62 | compatible = "qcom,msm-gpio"; | |
| 63 | gpio-controller; | |
| 64 | #gpio-cells = <2>; | |
| 65 | ngpio = <150>; | |
| 66 | interrupts = <0 16 0x4>; | |
| 67 | interrupt-controller; | |
| 68 | #interrupt-cells = <2>; | |
| 69 | reg = <0x800000 0x4000>; | |
| 70 | }; | |
| 71 | ||
| 72 | gcc: clock-controller@900000 { | |
| 73 | compatible = "qcom,gcc-msm8960"; | |
| 74 | #clock-cells = <1>; | |
| 75 | #reset-cells = <1>; | |
| 76 | reg = <0x900000 0x4000>; | |
| 77 | }; | |
| 78 | ||
| 79 | clock-controller@4000000 { | |
| 80 | compatible = "qcom,mmcc-msm8960"; | |
| 81 | reg = <0x4000000 0x1000>; | |
| 82 | #clock-cells = <1>; | |
| 83 | #reset-cells = <1>; | |
| 84 | }; | |
| 85 | ||
| 2ab27991 RV |
86 | acc0: clock-controller@2088000 { |
| 87 | compatible = "qcom,kpss-acc-v1"; | |
| 88 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
| 89 | }; | |
| 90 | ||
| 91 | acc1: clock-controller@2098000 { | |
| 92 | compatible = "qcom,kpss-acc-v1"; | |
| 93 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
| 94 | }; | |
| 95 | ||
| 96 | saw0: regulator@2089000 { | |
| 97 | compatible = "qcom,saw2"; | |
| 98 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | |
| 99 | regulator; | |
| 100 | }; | |
| 101 | ||
| 102 | saw1: regulator@2099000 { | |
| 103 | compatible = "qcom,saw2"; | |
| 104 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | |
| 105 | regulator; | |
| 106 | }; | |
| 107 | ||
| cc60a1a4 KG |
108 | serial@16440000 { |
| 109 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 110 | reg = <0x16440000 0x1000>, | |
| 111 | <0x16400000 0x1000>; | |
| 112 | interrupts = <0 154 0x0>; | |
| 113 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
| 114 | clock-names = "core", "iface"; | |
| 115 | }; | |
| 116 | ||
| 117 | qcom,ssbi@500000 { | |
| 118 | compatible = "qcom,ssbi"; | |
| 119 | reg = <0x500000 0x1000>; | |
| 120 | qcom,controller-type = "pmic-arbiter"; | |
| 121 | }; | |
| 122 | }; |