Commit | Line | Data |
---|---|---|
2aec37c6 RV |
1 | /dts-v1/; |
2 | ||
338d5188 | 3 | #include <dt-bindings/interrupt-controller/irq.h> |
3933d267 | 4 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> |
bf7f6b04 | 5 | #include "skeleton.dtsi" |
3933d267 | 6 | |
2aec37c6 RV |
7 | / { |
8 | model = "Qualcomm MSM8974"; | |
9 | compatible = "qcom,msm8974"; | |
10 | interrupt-parent = <&intc>; | |
11 | ||
6297c4b2 BA |
12 | reserved-memory { |
13 | #address-cells = <1>; | |
14 | #size-cells = <1>; | |
15 | ranges; | |
16 | ||
ca3971cf BA |
17 | mpss@08000000 { |
18 | reg = <0x08000000 0x5100000>; | |
19 | no-map; | |
20 | }; | |
21 | ||
22 | mba@00d100000 { | |
23 | reg = <0x0d100000 0x100000>; | |
24 | no-map; | |
25 | }; | |
26 | ||
27 | reserved@0d200000 { | |
28 | reg = <0x0d200000 0xa00000>; | |
29 | no-map; | |
30 | }; | |
31 | ||
32 | adsp@0dc00000 { | |
33 | reg = <0x0dc00000 0x1900000>; | |
34 | no-map; | |
35 | }; | |
36 | ||
37 | venus@0f500000 { | |
38 | reg = <0x0f500000 0x500000>; | |
39 | no-map; | |
40 | }; | |
41 | ||
6297c4b2 BA |
42 | smem_region: smem@fa00000 { |
43 | reg = <0xfa00000 0x200000>; | |
44 | no-map; | |
45 | }; | |
ca3971cf BA |
46 | |
47 | tz@0fc00000 { | |
48 | reg = <0x0fc00000 0x160000>; | |
49 | no-map; | |
50 | }; | |
51 | ||
97311198 BA |
52 | rfsa@0fd60000 { |
53 | reg = <0x0fd60000 0x20000>; | |
54 | no-map; | |
55 | }; | |
56 | ||
57 | rmtfs@0fd80000 { | |
58 | reg = <0x0fd80000 0x180000>; | |
ca3971cf BA |
59 | no-map; |
60 | }; | |
61 | ||
62 | unused@0ff00000 { | |
63 | reg = <0x0ff00000 0x10100000>; | |
64 | no-map; | |
65 | }; | |
6297c4b2 BA |
66 | }; |
67 | ||
2ab27991 RV |
68 | cpus { |
69 | #address-cells = <1>; | |
70 | #size-cells = <0>; | |
71 | interrupts = <1 9 0xf04>; | |
2ab27991 RV |
72 | |
73 | cpu@0 { | |
ba08220a KG |
74 | compatible = "qcom,krait"; |
75 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
76 | device_type = "cpu"; |
77 | reg = <0>; | |
78 | next-level-cache = <&L2>; | |
79 | qcom,acc = <&acc0>; | |
8c76a638 | 80 | qcom,saw = <&saw0>; |
d596d620 | 81 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
82 | }; |
83 | ||
84 | cpu@1 { | |
ba08220a KG |
85 | compatible = "qcom,krait"; |
86 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
87 | device_type = "cpu"; |
88 | reg = <1>; | |
89 | next-level-cache = <&L2>; | |
90 | qcom,acc = <&acc1>; | |
8c76a638 | 91 | qcom,saw = <&saw1>; |
d596d620 | 92 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
93 | }; |
94 | ||
95 | cpu@2 { | |
ba08220a KG |
96 | compatible = "qcom,krait"; |
97 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
98 | device_type = "cpu"; |
99 | reg = <2>; | |
100 | next-level-cache = <&L2>; | |
101 | qcom,acc = <&acc2>; | |
8c76a638 | 102 | qcom,saw = <&saw2>; |
d596d620 | 103 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
104 | }; |
105 | ||
106 | cpu@3 { | |
ba08220a KG |
107 | compatible = "qcom,krait"; |
108 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
109 | device_type = "cpu"; |
110 | reg = <3>; | |
111 | next-level-cache = <&L2>; | |
112 | qcom,acc = <&acc3>; | |
8c76a638 | 113 | qcom,saw = <&saw3>; |
d596d620 | 114 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
115 | }; |
116 | ||
117 | L2: l2-cache { | |
118 | compatible = "cache"; | |
119 | cache-level = <2>; | |
2ab27991 RV |
120 | qcom,saw = <&saw_l2>; |
121 | }; | |
d596d620 LI |
122 | |
123 | idle-states { | |
124 | CPU_SPC: spc { | |
125 | compatible = "qcom,idle-state-spc", | |
126 | "arm,idle-state"; | |
127 | entry-latency-us = <150>; | |
128 | exit-latency-us = <200>; | |
129 | min-residency-us = <2000>; | |
130 | }; | |
131 | }; | |
2ab27991 RV |
132 | }; |
133 | ||
3bff5474 SB |
134 | cpu-pmu { |
135 | compatible = "qcom,krait-pmu"; | |
136 | interrupts = <1 7 0xf04>; | |
137 | }; | |
138 | ||
30fc4212 SB |
139 | clocks { |
140 | xo_board { | |
141 | compatible = "fixed-clock"; | |
142 | #clock-cells = <0>; | |
143 | clock-frequency = <19200000>; | |
144 | }; | |
145 | ||
146 | sleep_clk { | |
147 | compatible = "fixed-clock"; | |
148 | #clock-cells = <0>; | |
149 | clock-frequency = <32768>; | |
150 | }; | |
151 | }; | |
152 | ||
ba08220a KG |
153 | timer { |
154 | compatible = "arm,armv7-timer"; | |
155 | interrupts = <1 2 0xf08>, | |
156 | <1 3 0xf08>, | |
157 | <1 4 0xf08>, | |
158 | <1 1 0xf08>; | |
159 | clock-frequency = <19200000>; | |
160 | }; | |
161 | ||
d0bfd7c9 SB |
162 | smem { |
163 | compatible = "qcom,smem"; | |
164 | ||
165 | memory-region = <&smem_region>; | |
166 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
167 | ||
168 | hwlocks = <&tcsr_mutex 3>; | |
169 | }; | |
170 | ||
5d3178c8 BA |
171 | smp2p-modem { |
172 | compatible = "qcom,smp2p"; | |
173 | qcom,smem = <435>, <428>; | |
174 | ||
175 | interrupt-parent = <&intc>; | |
176 | interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; | |
177 | ||
178 | qcom,ipc = <&apcs 8 14>; | |
179 | ||
180 | qcom,local-pid = <0>; | |
181 | qcom,remote-pid = <1>; | |
182 | ||
183 | modem_smp2p_out: master-kernel { | |
184 | qcom,entry-name = "master-kernel"; | |
185 | #qcom,state-cells = <1>; | |
186 | }; | |
187 | ||
188 | modem_smp2p_in: slave-kernel { | |
189 | qcom,entry-name = "slave-kernel"; | |
190 | ||
191 | interrupt-controller; | |
192 | #interrupt-cells = <2>; | |
193 | }; | |
194 | }; | |
195 | ||
7ccb11e7 BA |
196 | smp2p-wcnss { |
197 | compatible = "qcom,smp2p"; | |
198 | qcom,smem = <451>, <431>; | |
199 | ||
200 | interrupt-parent = <&intc>; | |
201 | interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; | |
202 | ||
203 | qcom,ipc = <&apcs 8 18>; | |
204 | ||
205 | qcom,local-pid = <0>; | |
206 | qcom,remote-pid = <4>; | |
207 | ||
208 | wcnss_smp2p_out: master-kernel { | |
209 | qcom,entry-name = "master-kernel"; | |
210 | ||
211 | #qcom,state-cells = <1>; | |
212 | }; | |
213 | ||
214 | wcnss_smp2p_in: slave-kernel { | |
215 | qcom,entry-name = "slave-kernel"; | |
216 | ||
217 | interrupt-controller; | |
218 | #interrupt-cells = <2>; | |
219 | }; | |
220 | }; | |
221 | ||
9af88b2d BA |
222 | smsm { |
223 | compatible = "qcom,smsm"; | |
224 | ||
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | ||
228 | qcom,ipc-1 = <&apcs 8 13>; | |
229 | qcom,ipc-2 = <&apcs 8 9>; | |
230 | qcom,ipc-3 = <&apcs 8 19>; | |
231 | ||
232 | apps_smsm: apps@0 { | |
233 | reg = <0>; | |
234 | ||
235 | #qcom,state-cells = <1>; | |
236 | }; | |
237 | ||
238 | modem_smsm: modem@1 { | |
239 | reg = <1>; | |
240 | interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; | |
241 | ||
242 | interrupt-controller; | |
243 | #interrupt-cells = <2>; | |
244 | }; | |
245 | ||
246 | adsp_smsm: adsp@2 { | |
247 | reg = <2>; | |
248 | interrupts = <0 157 IRQ_TYPE_EDGE_RISING>; | |
249 | ||
250 | interrupt-controller; | |
251 | #interrupt-cells = <2>; | |
252 | }; | |
253 | ||
254 | wcnss_smsm: wcnss@7 { | |
255 | reg = <7>; | |
256 | interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; | |
257 | ||
258 | interrupt-controller; | |
259 | #interrupt-cells = <2>; | |
260 | }; | |
261 | }; | |
262 | ||
2aec37c6 RV |
263 | soc: soc { |
264 | #address-cells = <1>; | |
265 | #size-cells = <1>; | |
266 | ranges; | |
267 | compatible = "simple-bus"; | |
268 | ||
269 | intc: interrupt-controller@f9000000 { | |
270 | compatible = "qcom,msm-qgic2"; | |
271 | interrupt-controller; | |
272 | #interrupt-cells = <3>; | |
273 | reg = <0xf9000000 0x1000>, | |
274 | <0xf9002000 0x1000>; | |
275 | }; | |
276 | ||
45b0ef05 BA |
277 | apcs: syscon@f9011000 { |
278 | compatible = "syscon"; | |
279 | reg = <0xf9011000 0x1000>; | |
280 | }; | |
281 | ||
47c5a5d6 SB |
282 | timer@f9020000 { |
283 | #address-cells = <1>; | |
284 | #size-cells = <1>; | |
285 | ranges; | |
286 | compatible = "arm,armv7-timer-mem"; | |
287 | reg = <0xf9020000 0x1000>; | |
288 | clock-frequency = <19200000>; | |
289 | ||
290 | frame@f9021000 { | |
291 | frame-number = <0>; | |
292 | interrupts = <0 8 0x4>, | |
293 | <0 7 0x4>; | |
294 | reg = <0xf9021000 0x1000>, | |
295 | <0xf9022000 0x1000>; | |
296 | }; | |
297 | ||
298 | frame@f9023000 { | |
299 | frame-number = <1>; | |
300 | interrupts = <0 9 0x4>; | |
301 | reg = <0xf9023000 0x1000>; | |
302 | status = "disabled"; | |
303 | }; | |
304 | ||
305 | frame@f9024000 { | |
306 | frame-number = <2>; | |
307 | interrupts = <0 10 0x4>; | |
308 | reg = <0xf9024000 0x1000>; | |
309 | status = "disabled"; | |
310 | }; | |
311 | ||
312 | frame@f9025000 { | |
313 | frame-number = <3>; | |
314 | interrupts = <0 11 0x4>; | |
315 | reg = <0xf9025000 0x1000>; | |
316 | status = "disabled"; | |
317 | }; | |
318 | ||
319 | frame@f9026000 { | |
320 | frame-number = <4>; | |
321 | interrupts = <0 12 0x4>; | |
322 | reg = <0xf9026000 0x1000>; | |
323 | status = "disabled"; | |
324 | }; | |
325 | ||
326 | frame@f9027000 { | |
327 | frame-number = <5>; | |
328 | interrupts = <0 13 0x4>; | |
329 | reg = <0xf9027000 0x1000>; | |
330 | status = "disabled"; | |
331 | }; | |
332 | ||
333 | frame@f9028000 { | |
334 | frame-number = <6>; | |
335 | interrupts = <0 14 0x4>; | |
336 | reg = <0xf9028000 0x1000>; | |
337 | status = "disabled"; | |
338 | }; | |
339 | }; | |
340 | ||
8c76a638 LI |
341 | saw0: power-controller@f9089000 { |
342 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
343 | reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; | |
344 | }; | |
345 | ||
346 | saw1: power-controller@f9099000 { | |
347 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
348 | reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; | |
349 | }; | |
350 | ||
351 | saw2: power-controller@f90a9000 { | |
352 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
353 | reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; | |
354 | }; | |
355 | ||
356 | saw3: power-controller@f90b9000 { | |
357 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
358 | reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; | |
359 | }; | |
360 | ||
361 | saw_l2: power-controller@f9012000 { | |
2ab27991 RV |
362 | compatible = "qcom,saw2"; |
363 | reg = <0xf9012000 0x1000>; | |
364 | regulator; | |
365 | }; | |
366 | ||
367 | acc0: clock-controller@f9088000 { | |
368 | compatible = "qcom,kpss-acc-v2"; | |
369 | reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; | |
370 | }; | |
371 | ||
372 | acc1: clock-controller@f9098000 { | |
373 | compatible = "qcom,kpss-acc-v2"; | |
374 | reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; | |
375 | }; | |
376 | ||
377 | acc2: clock-controller@f90a8000 { | |
378 | compatible = "qcom,kpss-acc-v2"; | |
379 | reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; | |
380 | }; | |
381 | ||
382 | acc3: clock-controller@f90b8000 { | |
383 | compatible = "qcom,kpss-acc-v2"; | |
384 | reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; | |
385 | }; | |
386 | ||
74e848f6 SB |
387 | restart@fc4ab000 { |
388 | compatible = "qcom,pshold"; | |
389 | reg = <0xfc4ab000 0x4>; | |
390 | }; | |
3933d267 SB |
391 | |
392 | gcc: clock-controller@fc400000 { | |
393 | compatible = "qcom,gcc-msm8974"; | |
394 | #clock-cells = <1>; | |
395 | #reset-cells = <1>; | |
89c7e671 | 396 | #power-domain-cells = <1>; |
3933d267 SB |
397 | reg = <0xfc400000 0x4000>; |
398 | }; | |
399 | ||
b4e745e1 BA |
400 | tcsr_mutex_block: syscon@fd484000 { |
401 | compatible = "syscon"; | |
402 | reg = <0xfd484000 0x2000>; | |
403 | }; | |
404 | ||
3933d267 SB |
405 | mmcc: clock-controller@fd8c0000 { |
406 | compatible = "qcom,mmcc-msm8974"; | |
407 | #clock-cells = <1>; | |
408 | #reset-cells = <1>; | |
89c7e671 | 409 | #power-domain-cells = <1>; |
3933d267 SB |
410 | reg = <0xfd8c0000 0x6000>; |
411 | }; | |
412 | ||
b4e745e1 BA |
413 | tcsr_mutex: tcsr-mutex { |
414 | compatible = "qcom,tcsr-mutex"; | |
415 | syscon = <&tcsr_mutex_block 0 0x80>; | |
416 | ||
417 | #hwlock-cells = <1>; | |
418 | }; | |
419 | ||
d0bfd7c9 SB |
420 | rpm_msg_ram: memory@fc428000 { |
421 | compatible = "qcom,rpm-msg-ram"; | |
6297c4b2 | 422 | reg = <0xfc428000 0x4000>; |
6297c4b2 BA |
423 | }; |
424 | ||
10bfcfea | 425 | blsp1_uart2: serial@f991e000 { |
3933d267 SB |
426 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
427 | reg = <0xf991e000 0x1000>; | |
428 | interrupts = <0 108 0x0>; | |
429 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
430 | clock-names = "core", "iface"; | |
ba08220a | 431 | status = "disabled"; |
3933d267 | 432 | }; |
19f4f8c1 | 433 | |
3e944c76 GD |
434 | sdhci@f9824900 { |
435 | compatible = "qcom,sdhci-msm-v4"; | |
436 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
437 | reg-names = "hc_mem", "core_mem"; | |
438 | interrupts = <0 123 0>, <0 138 0>; | |
439 | interrupt-names = "hc_irq", "pwr_irq"; | |
440 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | |
441 | clock-names = "core", "iface"; | |
442 | status = "disabled"; | |
443 | }; | |
444 | ||
445 | sdhci@f98a4900 { | |
446 | compatible = "qcom,sdhci-msm-v4"; | |
447 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
448 | reg-names = "hc_mem", "core_mem"; | |
449 | interrupts = <0 125 0>, <0 221 0>; | |
450 | interrupt-names = "hc_irq", "pwr_irq"; | |
451 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | |
452 | clock-names = "core", "iface"; | |
453 | status = "disabled"; | |
454 | }; | |
455 | ||
19f4f8c1 SV |
456 | rng@f9bff000 { |
457 | compatible = "qcom,prng"; | |
458 | reg = <0xf9bff000 0x200>; | |
459 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
460 | clock-names = "core"; | |
461 | }; | |
7d7db8db II |
462 | |
463 | msmgpio: pinctrl@fd510000 { | |
464 | compatible = "qcom,msm8974-pinctrl"; | |
465 | reg = <0xfd510000 0x4000>; | |
466 | gpio-controller; | |
467 | #gpio-cells = <2>; | |
468 | interrupt-controller; | |
469 | #interrupt-cells = <2>; | |
470 | interrupts = <0 208 0>; | |
7d7db8db | 471 | }; |
bf7f6b04 | 472 | |
89af1c2d BA |
473 | i2c@f9924000 { |
474 | status = "disabled"; | |
475 | compatible = "qcom,i2c-qup-v2.1.1"; | |
476 | reg = <0xf9924000 0x1000>; | |
477 | interrupts = <0 96 IRQ_TYPE_NONE>; | |
478 | clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
479 | clock-names = "core", "iface"; | |
480 | #address-cells = <1>; | |
481 | #size-cells = <0>; | |
482 | }; | |
483 | ||
580df59f BA |
484 | blsp_i2c8: i2c@f9964000 { |
485 | status = "disabled"; | |
486 | compatible = "qcom,i2c-qup-v2.1.1"; | |
487 | reg = <0xf9964000 0x1000>; | |
488 | interrupts = <0 102 IRQ_TYPE_NONE>; | |
489 | clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
490 | clock-names = "core", "iface"; | |
491 | #address-cells = <1>; | |
492 | #size-cells = <0>; | |
493 | }; | |
494 | ||
bf7f6b04 | 495 | blsp_i2c11: i2c@f9967000 { |
04edde25 | 496 | status = "disabled"; |
bf7f6b04 | 497 | compatible = "qcom,i2c-qup-v2.1.1"; |
498 | reg = <0xf9967000 0x1000>; | |
499 | interrupts = <0 105 IRQ_TYPE_NONE>; | |
500 | clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
501 | clock-names = "core", "iface"; | |
502 | #address-cells = <1>; | |
503 | #size-cells = <0>; | |
504 | }; | |
af22e46d II |
505 | |
506 | spmi_bus: spmi@fc4cf000 { | |
507 | compatible = "qcom,spmi-pmic-arb"; | |
508 | reg-names = "core", "intr", "cnfg"; | |
509 | reg = <0xfc4cf000 0x1000>, | |
510 | <0xfc4cb000 0x1000>, | |
511 | <0xfc4ca000 0x1000>; | |
512 | interrupt-names = "periph_irq"; | |
513 | interrupts = <0 190 0>; | |
514 | qcom,ee = <0>; | |
515 | qcom,channel = <0>; | |
516 | #address-cells = <2>; | |
517 | #size-cells = <0>; | |
518 | interrupt-controller; | |
519 | #interrupt-cells = <4>; | |
520 | }; | |
2aec37c6 | 521 | }; |
45b0ef05 BA |
522 | |
523 | smd { | |
524 | compatible = "qcom,smd"; | |
525 | ||
5d3178c8 BA |
526 | modem { |
527 | interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; | |
528 | ||
529 | qcom,ipc = <&apcs 8 12>; | |
530 | qcom,smd-edge = <0>; | |
531 | }; | |
532 | ||
45b0ef05 BA |
533 | rpm { |
534 | interrupts = <0 168 1>; | |
535 | qcom,ipc = <&apcs 8 0>; | |
536 | qcom,smd-edge = <15>; | |
537 | ||
538 | rpm_requests { | |
539 | compatible = "qcom,rpm-msm8974"; | |
540 | qcom,smd-channels = "rpm_requests"; | |
541 | ||
542 | pm8841-regulators { | |
543 | compatible = "qcom,rpm-pm8841-regulators"; | |
544 | ||
545 | pm8841_s1: s1 {}; | |
546 | pm8841_s2: s2 {}; | |
547 | pm8841_s3: s3 {}; | |
548 | pm8841_s4: s4 {}; | |
549 | pm8841_s5: s5 {}; | |
550 | pm8841_s6: s6 {}; | |
551 | pm8841_s7: s7 {}; | |
552 | pm8841_s8: s8 {}; | |
553 | }; | |
554 | ||
555 | pm8941-regulators { | |
556 | compatible = "qcom,rpm-pm8941-regulators"; | |
557 | ||
558 | pm8941_s1: s1 {}; | |
559 | pm8941_s2: s2 {}; | |
560 | pm8941_s3: s3 {}; | |
561 | pm8941_5v: s4 {}; | |
562 | ||
563 | pm8941_l1: l1 {}; | |
564 | pm8941_l2: l2 {}; | |
565 | pm8941_l3: l3 {}; | |
566 | pm8941_l4: l4 {}; | |
567 | pm8941_l5: l5 {}; | |
568 | pm8941_l6: l6 {}; | |
569 | pm8941_l7: l7 {}; | |
570 | pm8941_l8: l8 {}; | |
571 | pm8941_l9: l9 {}; | |
572 | pm8941_l10: l10 {}; | |
573 | pm8941_l11: l11 {}; | |
574 | pm8941_l12: l12 {}; | |
575 | pm8941_l13: l13 {}; | |
576 | pm8941_l14: l14 {}; | |
577 | pm8941_l15: l15 {}; | |
578 | pm8941_l16: l16 {}; | |
579 | pm8941_l17: l17 {}; | |
580 | pm8941_l18: l18 {}; | |
581 | pm8941_l19: l19 {}; | |
582 | pm8941_l20: l20 {}; | |
583 | pm8941_l21: l21 {}; | |
584 | pm8941_l22: l22 {}; | |
585 | pm8941_l23: l23 {}; | |
586 | pm8941_l24: l24 {}; | |
587 | ||
588 | pm8941_lvs1: lvs1 {}; | |
589 | pm8941_lvs2: lvs2 {}; | |
590 | pm8941_lvs3: lvs3 {}; | |
591 | ||
592 | pm8941_5vs1: 5vs1 {}; | |
593 | pm8941_5vs2: 5vs2 {}; | |
594 | }; | |
595 | }; | |
596 | }; | |
597 | }; | |
2aec37c6 | 598 | }; |