Commit | Line | Data |
---|---|---|
e3da5b36 MD |
1 | /* |
2 | * Device Tree Source for the r7s72100 SoC | |
3 | * | |
b6face40 WS |
4 | * Copyright (C) 2013-14 Renesas Solutions Corp. |
5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> | |
e3da5b36 MD |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
b6face40 | 12 | #include <dt-bindings/clock/r7s72100-clock.h> |
16af4e97 | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
4b18e83f GU |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | ||
e3da5b36 MD |
16 | / { |
17 | compatible = "renesas,r7s72100"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <1>; | |
20 | #size-cells = <1>; | |
21 | ||
4b18e83f | 22 | aliases { |
c81a4d3d WS |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
4b18e83f GU |
27 | spi0 = &spi0; |
28 | spi1 = &spi1; | |
29 | spi2 = &spi2; | |
30 | spi3 = &spi3; | |
31 | spi4 = &spi4; | |
32 | }; | |
33 | ||
b6face40 WS |
34 | clocks { |
35 | ranges; | |
36 | #address-cells = <1>; | |
37 | #size-cells = <1>; | |
38 | ||
39 | /* External clocks */ | |
40 | extal_clk: extal_clk { | |
41 | #clock-cells = <0>; | |
42 | compatible = "fixed-clock"; | |
43 | /* If clk present, value must be set by board */ | |
44 | clock-frequency = <0>; | |
45 | clock-output-names = "extal"; | |
46 | }; | |
47 | ||
48 | usb_x1_clk: usb_x1_clk { | |
49 | #clock-cells = <0>; | |
50 | compatible = "fixed-clock"; | |
51 | /* If clk present, value must be set by board */ | |
52 | clock-frequency = <0>; | |
53 | clock-output-names = "usb_x1"; | |
54 | }; | |
55 | ||
b6face40 WS |
56 | /* Fixed factor clocks */ |
57 | b_clk: b_clk { | |
58 | #clock-cells = <0>; | |
59 | compatible = "fixed-factor-clock"; | |
60 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
61 | clock-mult = <1>; | |
62 | clock-div = <3>; | |
63 | clock-output-names = "b"; | |
64 | }; | |
65 | p1_clk: p1_clk { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-factor-clock"; | |
68 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
69 | clock-mult = <1>; | |
70 | clock-div = <6>; | |
71 | clock-output-names = "p1"; | |
72 | }; | |
73 | p0_clk: p0_clk { | |
74 | #clock-cells = <0>; | |
75 | compatible = "fixed-factor-clock"; | |
76 | clocks = <&cpg_clocks R7S72100_CLK_PLL>; | |
77 | clock-mult = <1>; | |
78 | clock-div = <12>; | |
79 | clock-output-names = "p0"; | |
80 | }; | |
81 | ||
005980c0 UH |
82 | /* Special CPG clocks */ |
83 | cpg_clocks: cpg_clocks@fcfe0000 { | |
84 | #clock-cells = <1>; | |
85 | compatible = "renesas,r7s72100-cpg-clocks", | |
86 | "renesas,rz-cpg-clocks"; | |
87 | reg = <0xfcfe0000 0x18>; | |
88 | clocks = <&extal_clk>, <&usb_x1_clk>; | |
89 | clock-output-names = "pll", "i", "g"; | |
cbe1f838 | 90 | #power-domain-cells = <0>; |
005980c0 UH |
91 | }; |
92 | ||
b6face40 WS |
93 | /* MSTP clocks */ |
94 | mstp3_clks: mstp3_clks@fcfe0420 { | |
95 | #clock-cells = <1>; | |
96 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
97 | reg = <0xfcfe0420 4>; | |
98 | clocks = <&p0_clk>; | |
99 | clock-indices = <R7S72100_CLK_MTU2>; | |
100 | clock-output-names = "mtu2"; | |
101 | }; | |
102 | ||
103 | mstp4_clks: mstp4_clks@fcfe0424 { | |
104 | #clock-cells = <1>; | |
105 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
106 | reg = <0xfcfe0424 4>; | |
107 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | |
108 | <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; | |
109 | clock-indices = < | |
110 | R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3 | |
111 | R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7 | |
112 | >; | |
113 | clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; | |
114 | }; | |
d165566b WS |
115 | |
116 | mstp9_clks: mstp9_clks@fcfe0438 { | |
117 | #clock-cells = <1>; | |
118 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
119 | reg = <0xfcfe0438 4>; | |
120 | clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; | |
121 | clock-indices = < | |
122 | R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 | |
123 | >; | |
124 | clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; | |
125 | }; | |
52eed4f5 WS |
126 | |
127 | mstp10_clks: mstp10_clks@fcfe043c { | |
128 | #clock-cells = <1>; | |
129 | compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
130 | reg = <0xfcfe043c 4>; | |
131 | clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>, | |
132 | <&p1_clk>; | |
133 | clock-indices = < | |
134 | R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3 | |
135 | R7S72100_CLK_SPI4 | |
136 | >; | |
137 | clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4"; | |
138 | }; | |
b6face40 WS |
139 | }; |
140 | ||
e3da5b36 MD |
141 | cpus { |
142 | #address-cells = <1>; | |
143 | #size-cells = <0>; | |
144 | ||
145 | cpu@0 { | |
146 | device_type = "cpu"; | |
147 | compatible = "arm,cortex-a9"; | |
148 | reg = <0>; | |
005407fd | 149 | clock-frequency = <400000000>; |
e3da5b36 MD |
150 | }; |
151 | }; | |
152 | ||
4c84c1b3 WS |
153 | scif0: serial@e8007000 { |
154 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
155 | reg = <0xe8007000 64>; | |
16af4e97 SH |
156 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
157 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 160 | clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; |
92489120 | 161 | clock-names = "fck"; |
cbe1f838 | 162 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
163 | status = "disabled"; |
164 | }; | |
165 | ||
166 | scif1: serial@e8007800 { | |
167 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
168 | reg = <0xe8007800 64>; | |
16af4e97 SH |
169 | interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, |
170 | <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, | |
171 | <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
172 | <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 173 | clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; |
92489120 | 174 | clock-names = "fck"; |
cbe1f838 | 175 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
176 | status = "disabled"; |
177 | }; | |
178 | ||
179 | scif2: serial@e8008000 { | |
180 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
181 | reg = <0xe8008000 64>; | |
16af4e97 SH |
182 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
183 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 186 | clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; |
92489120 | 187 | clock-names = "fck"; |
cbe1f838 | 188 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
189 | status = "disabled"; |
190 | }; | |
191 | ||
192 | scif3: serial@e8008800 { | |
193 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
194 | reg = <0xe8008800 64>; | |
16af4e97 SH |
195 | interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, |
196 | <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 199 | clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; |
92489120 | 200 | clock-names = "fck"; |
cbe1f838 | 201 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
202 | status = "disabled"; |
203 | }; | |
204 | ||
205 | scif4: serial@e8009000 { | |
206 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
207 | reg = <0xe8009000 64>; | |
16af4e97 SH |
208 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
209 | <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 212 | clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; |
92489120 | 213 | clock-names = "fck"; |
cbe1f838 | 214 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
215 | status = "disabled"; |
216 | }; | |
217 | ||
218 | scif5: serial@e8009800 { | |
219 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
220 | reg = <0xe8009800 64>; | |
16af4e97 SH |
221 | interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
222 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
223 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
224 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 225 | clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; |
92489120 | 226 | clock-names = "fck"; |
cbe1f838 | 227 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
228 | status = "disabled"; |
229 | }; | |
230 | ||
231 | scif6: serial@e800a000 { | |
232 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
233 | reg = <0xe800a000 64>; | |
16af4e97 SH |
234 | interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
235 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, | |
236 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, | |
237 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 238 | clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; |
92489120 | 239 | clock-names = "fck"; |
cbe1f838 | 240 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
241 | status = "disabled"; |
242 | }; | |
243 | ||
244 | scif7: serial@e800a800 { | |
245 | compatible = "renesas,scif-r7s72100", "renesas,scif"; | |
246 | reg = <0xe800a800 64>; | |
16af4e97 SH |
247 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, |
248 | <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, | |
249 | <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, | |
250 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
4c84c1b3 | 251 | clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; |
92489120 | 252 | clock-names = "fck"; |
cbe1f838 | 253 | power-domains = <&cpg_clocks>; |
4c84c1b3 WS |
254 | status = "disabled"; |
255 | }; | |
256 | ||
4b18e83f GU |
257 | spi0: spi@e800c800 { |
258 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
259 | reg = <0xe800c800 0x24>; | |
16af4e97 SH |
260 | interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
261 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
262 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 263 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 264 | clocks = <&mstp10_clks R7S72100_CLK_SPI0>; |
cbe1f838 | 265 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
266 | num-cs = <1>; |
267 | #address-cells = <1>; | |
268 | #size-cells = <0>; | |
269 | status = "disabled"; | |
270 | }; | |
271 | ||
272 | spi1: spi@e800d000 { | |
273 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
274 | reg = <0xe800d000 0x24>; | |
16af4e97 SH |
275 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
276 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
277 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 278 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 279 | clocks = <&mstp10_clks R7S72100_CLK_SPI1>; |
cbe1f838 | 280 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
281 | num-cs = <1>; |
282 | #address-cells = <1>; | |
283 | #size-cells = <0>; | |
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | spi2: spi@e800d800 { | |
288 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
289 | reg = <0xe800d800 0x24>; | |
16af4e97 SH |
290 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
291 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
292 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 293 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 294 | clocks = <&mstp10_clks R7S72100_CLK_SPI2>; |
cbe1f838 | 295 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
296 | num-cs = <1>; |
297 | #address-cells = <1>; | |
298 | #size-cells = <0>; | |
299 | status = "disabled"; | |
300 | }; | |
301 | ||
302 | spi3: spi@e800e000 { | |
303 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
304 | reg = <0xe800e000 0x24>; | |
16af4e97 SH |
305 | interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
306 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 308 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 309 | clocks = <&mstp10_clks R7S72100_CLK_SPI3>; |
cbe1f838 | 310 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
311 | num-cs = <1>; |
312 | #address-cells = <1>; | |
313 | #size-cells = <0>; | |
314 | status = "disabled"; | |
315 | }; | |
316 | ||
317 | spi4: spi@e800e800 { | |
318 | compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; | |
319 | reg = <0xe800e800 0x24>; | |
16af4e97 SH |
320 | interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
321 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
322 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
4b18e83f | 323 | interrupt-names = "error", "rx", "tx"; |
52eed4f5 | 324 | clocks = <&mstp10_clks R7S72100_CLK_SPI4>; |
cbe1f838 | 325 | power-domains = <&cpg_clocks>; |
4b18e83f GU |
326 | num-cs = <1>; |
327 | #address-cells = <1>; | |
328 | #size-cells = <0>; | |
329 | status = "disabled"; | |
330 | }; | |
005980c0 UH |
331 | |
332 | gic: interrupt-controller@e8201000 { | |
d9e1a0ef | 333 | compatible = "arm,pl390"; |
005980c0 UH |
334 | #interrupt-cells = <3>; |
335 | #address-cells = <0>; | |
336 | interrupt-controller; | |
337 | reg = <0xe8201000 0x1000>, | |
338 | <0xe8202000 0x1000>; | |
339 | }; | |
340 | ||
341 | i2c0: i2c@fcfee000 { | |
342 | #address-cells = <1>; | |
343 | #size-cells = <0>; | |
344 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
345 | reg = <0xfcfee000 0x44>; | |
16af4e97 SH |
346 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
347 | <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, | |
348 | <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, | |
349 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, | |
350 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
351 | <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, | |
352 | <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, | |
353 | <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
354 | clocks = <&mstp9_clks R7S72100_CLK_I2C0>; |
355 | clock-frequency = <100000>; | |
cbe1f838 | 356 | power-domains = <&cpg_clocks>; |
005980c0 UH |
357 | status = "disabled"; |
358 | }; | |
359 | ||
360 | i2c1: i2c@fcfee400 { | |
361 | #address-cells = <1>; | |
362 | #size-cells = <0>; | |
363 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
364 | reg = <0xfcfee400 0x44>; | |
16af4e97 SH |
365 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
366 | <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, | |
367 | <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, | |
368 | <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, | |
369 | <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, | |
370 | <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, | |
371 | <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, | |
372 | <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
373 | clocks = <&mstp9_clks R7S72100_CLK_I2C1>; |
374 | clock-frequency = <100000>; | |
cbe1f838 | 375 | power-domains = <&cpg_clocks>; |
005980c0 UH |
376 | status = "disabled"; |
377 | }; | |
378 | ||
379 | i2c2: i2c@fcfee800 { | |
380 | #address-cells = <1>; | |
381 | #size-cells = <0>; | |
382 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
383 | reg = <0xfcfee800 0x44>; | |
16af4e97 SH |
384 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
385 | <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, | |
386 | <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, | |
387 | <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, | |
388 | <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, | |
389 | <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, | |
390 | <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, | |
391 | <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
392 | clocks = <&mstp9_clks R7S72100_CLK_I2C2>; |
393 | clock-frequency = <100000>; | |
cbe1f838 | 394 | power-domains = <&cpg_clocks>; |
005980c0 UH |
395 | status = "disabled"; |
396 | }; | |
397 | ||
398 | i2c3: i2c@fcfeec00 { | |
399 | #address-cells = <1>; | |
400 | #size-cells = <0>; | |
401 | compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; | |
402 | reg = <0xfcfeec00 0x44>; | |
16af4e97 SH |
403 | interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
404 | <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, | |
405 | <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, | |
406 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
407 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
408 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
409 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
410 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
005980c0 UH |
411 | clocks = <&mstp9_clks R7S72100_CLK_I2C3>; |
412 | clock-frequency = <100000>; | |
cbe1f838 | 413 | power-domains = <&cpg_clocks>; |
005980c0 UH |
414 | status = "disabled"; |
415 | }; | |
416 | ||
417 | mtu2: timer@fcff0000 { | |
418 | compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; | |
419 | reg = <0xfcff0000 0x400>; | |
16af4e97 | 420 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
005980c0 UH |
421 | interrupt-names = "tgi0a"; |
422 | clocks = <&mstp3_clks R7S72100_CLK_MTU2>; | |
423 | clock-names = "fck"; | |
cbe1f838 | 424 | power-domains = <&cpg_clocks>; |
005980c0 UH |
425 | status = "disabled"; |
426 | }; | |
e3da5b36 | 427 | }; |