[deliverable/linux.git] / arch / arm / boot / dts / r7s72100.dtsi

/*
 * Device Tree Source for the r7s72100 SoC
 *
 * Copyright (C) 2013-14 Renesas Solutions Corp.
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r7s72100";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
	};

	clocks {
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		/* External clocks */
		extal_clk: extal {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			/* If clk present, value must be set by board */
			clock-frequency = <0>;
		};

		usb_x1_clk: usb_x1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			/* If clk present, value must be set by board */
			clock-frequency = <0>;
		};

		/* Fixed factor clocks */
		b_clk: b {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <3>;
		};
		p1_clk: p1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <6>;
		};
		p0_clk: p0 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R7S72100_CLK_PLL>;
			clock-mult = <1>;
			clock-div = <12>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@fcfe0000 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-cpg-clocks",
				     "renesas,rz-cpg-clocks";
			reg = <0xfcfe0000 0x18>;
			clocks = <&extal_clk>, <&usb_x1_clk>;
			clock-output-names = "pll", "i", "g";
			#power-domain-cells = <0>;
		};

		/* MSTP clocks */
		mstp3_clks: mstp3_clks@fcfe0420 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0420 4>;
			clocks = <&p0_clk>;
			clock-indices = <R7S72100_CLK_MTU2>;
			clock-output-names = "mtu2";
		};

		mstp4_clks: mstp4_clks@fcfe0424 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0424 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
			>;
			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
		};

		mstp9_clks: mstp9_clks@fcfe0438 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0438 4>;
			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
			clock-indices = <
				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
			>;
			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
		};

		mstp10_clks: mstp10_clks@fcfe043c {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe043c 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
				R7S72100_CLK_SPI4
			>;
			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <400000000>;
		};
	};

	scif0: serial@e8007000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8007000 64>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@e8007800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8007800 64>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@e8008000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8008000 64>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@e8008800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8008800 64>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@e8009000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8009000 64>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@e8009800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe8009800 64>;
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif6: serial@e800a000 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe800a000 64>;
		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif7: serial@e800a800 {
		compatible = "renesas,scif-r7s72100", "renesas,scif";
		reg = <0xe800a800 64>;
		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	spi0: spi@e800c800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800c800 0x24>;
		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@e800d000 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800d000 0x24>;
		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi2: spi@e800d800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800d800 0x24>;
		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi3: spi@e800e000 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800e000 0x24>;
		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi4: spi@e800e800 {
		compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
		reg = <0xe800e800 0x24>;
		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error", "rx", "tx";
		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
		power-domains = <&cpg_clocks>;
		num-cs = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gic: interrupt-controller@e8201000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0xe8201000 0x1000>,
			<0xe8202000 0x1000>;
	};

	i2c0: i2c@fcfee000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee000 0x44>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c1: i2c@fcfee400 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee400 0x44>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c2: i2c@fcfee800 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfee800 0x44>;
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c3: i2c@fcfeec00 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
		reg = <0xfcfeec00 0x44>;
		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
		clock-frequency = <100000>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	mtu2: timer@fcff0000 {
		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
		reg = <0xfcff0000 0x400>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tgi0a";
		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};
};
Commit	Line	Data
e3da5b36 MD	1	/*
	2	* Device Tree Source for the r7s72100 SoC
	3	*
b6face40 WS	4	* Copyright (C) 2013-14 Renesas Solutions Corp.
b6face40 WS	5	* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
e3da5b36 MD	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
b6face40	12	#include <dt-bindings/clock/r7s72100-clock.h>
16af4e97	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
4b18e83f GU	14	#include <dt-bindings/interrupt-controller/irq.h>
4b18e83f GU	15
e3da5b36 MD	16	/ {
	17	compatible = "renesas,r7s72100";
	18	interrupt-parent = <&gic>;
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
4b18e83f	22	aliases {
c81a4d3d WS	23	i2c0 = &i2c0;
	24	i2c1 = &i2c1;
	25	i2c2 = &i2c2;
	26	i2c3 = &i2c3;
4b18e83f GU	27	spi0 = &spi0;
	28	spi1 = &spi1;
	29	spi2 = &spi2;
	30	spi3 = &spi3;
	31	spi4 = &spi4;
	32	};
	33
b6face40 WS	34	clocks {
	35	ranges;
	36	#address-cells = <1>;
	37	#size-cells = <1>;
	38
	39	/* External clocks */
21f18970	40	extal_clk: extal {
b6face40 WS	41	#clock-cells = <0>;
	42	compatible = "fixed-clock";
	43	/* If clk present, value must be set by board */
	44	clock-frequency = <0>;
b6face40 WS	45	};
b6face40 WS	46
21f18970	47	usb_x1_clk: usb_x1 {
b6face40 WS	48	#clock-cells = <0>;
	49	compatible = "fixed-clock";
	50	/* If clk present, value must be set by board */
	51	clock-frequency = <0>;
b6face40 WS	52	};
b6face40 WS	53
b6face40	54	/* Fixed factor clocks */
21f18970	55	b_clk: b {
b6face40 WS	56	#clock-cells = <0>;
	57	compatible = "fixed-factor-clock";
	58	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	59	clock-mult = <1>;
	60	clock-div = <3>;
b6face40	61	};
21f18970	62	p1_clk: p1 {
b6face40 WS	63	#clock-cells = <0>;
	64	compatible = "fixed-factor-clock";
	65	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	66	clock-mult = <1>;
	67	clock-div = <6>;
b6face40	68	};
21f18970	69	p0_clk: p0 {
b6face40 WS	70	#clock-cells = <0>;
	71	compatible = "fixed-factor-clock";
	72	clocks = <&cpg_clocks R7S72100_CLK_PLL>;
	73	clock-mult = <1>;
	74	clock-div = <12>;
b6face40 WS	75	};
b6face40 WS	76
005980c0 UH	77	/* Special CPG clocks */
	78	cpg_clocks: cpg_clocks@fcfe0000 {
	79	#clock-cells = <1>;
	80	compatible = "renesas,r7s72100-cpg-clocks",
	81	"renesas,rz-cpg-clocks";
	82	reg = <0xfcfe0000 0x18>;
	83	clocks = <&extal_clk>, <&usb_x1_clk>;
	84	clock-output-names = "pll", "i", "g";
cbe1f838	85	#power-domain-cells = <0>;
005980c0 UH	86	};
005980c0 UH	87
b6face40 WS	88	/* MSTP clocks */
	89	mstp3_clks: mstp3_clks@fcfe0420 {
	90	#clock-cells = <1>;
	91	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	92	reg = <0xfcfe0420 4>;
	93	clocks = <&p0_clk>;
	94	clock-indices = <R7S72100_CLK_MTU2>;
	95	clock-output-names = "mtu2";
	96	};
	97
	98	mstp4_clks: mstp4_clks@fcfe0424 {
	99	#clock-cells = <1>;
	100	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	101	reg = <0xfcfe0424 4>;
	102	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	103	<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
	104	clock-indices = <
	105	R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
	106	R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
	107	>;
	108	clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
	109	};
d165566b WS	110
	111	mstp9_clks: mstp9_clks@fcfe0438 {
	112	#clock-cells = <1>;
	113	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	114	reg = <0xfcfe0438 4>;
	115	clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
	116	clock-indices = <
	117	R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
	118	>;
	119	clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
	120	};
52eed4f5 WS	121
	122	mstp10_clks: mstp10_clks@fcfe043c {
	123	#clock-cells = <1>;
	124	compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
	125	reg = <0xfcfe043c 4>;
	126	clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
	127	<&p1_clk>;
	128	clock-indices = <
	129	R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
	130	R7S72100_CLK_SPI4
	131	>;
	132	clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
	133	};
b6face40 WS	134	};
b6face40 WS	135
e3da5b36 MD	136	cpus {
	137	#address-cells = <1>;
	138	#size-cells = <0>;
	139
	140	cpu@0 {
	141	device_type = "cpu";
	142	compatible = "arm,cortex-a9";
	143	reg = <0>;
005407fd	144	clock-frequency = <400000000>;
e3da5b36 MD	145	};
	146	};
	147
4c84c1b3 WS	148	scif0: serial@e8007000 {
	149	compatible = "renesas,scif-r7s72100", "renesas,scif";
	150	reg = <0xe8007000 64>;
16af4e97 SH	151	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	152	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	153	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	155	clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
92489120	156	clock-names = "fck";
cbe1f838	157	power-domains = <&cpg_clocks>;
4c84c1b3 WS	158	status = "disabled";
	159	};
	160
	161	scif1: serial@e8007800 {
	162	compatible = "renesas,scif-r7s72100", "renesas,scif";
	163	reg = <0xe8007800 64>;
16af4e97 SH	164	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	165	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	166	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	167	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	168	clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
92489120	169	clock-names = "fck";
cbe1f838	170	power-domains = <&cpg_clocks>;
4c84c1b3 WS	171	status = "disabled";
	172	};
	173
	174	scif2: serial@e8008000 {
	175	compatible = "renesas,scif-r7s72100", "renesas,scif";
	176	reg = <0xe8008000 64>;
16af4e97 SH	177	interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	180	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	181	clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
92489120	182	clock-names = "fck";
cbe1f838	183	power-domains = <&cpg_clocks>;
4c84c1b3 WS	184	status = "disabled";
	185	};
	186
	187	scif3: serial@e8008800 {
	188	compatible = "renesas,scif-r7s72100", "renesas,scif";
	189	reg = <0xe8008800 64>;
16af4e97 SH	190	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	194	clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
92489120	195	clock-names = "fck";
cbe1f838	196	power-domains = <&cpg_clocks>;
4c84c1b3 WS	197	status = "disabled";
	198	};
	199
	200	scif4: serial@e8009000 {
	201	compatible = "renesas,scif-r7s72100", "renesas,scif";
	202	reg = <0xe8009000 64>;
16af4e97 SH	203	interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	206	<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	207	clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
92489120	208	clock-names = "fck";
cbe1f838	209	power-domains = <&cpg_clocks>;
4c84c1b3 WS	210	status = "disabled";
	211	};
	212
	213	scif5: serial@e8009800 {
	214	compatible = "renesas,scif-r7s72100", "renesas,scif";
	215	reg = <0xe8009800 64>;
16af4e97 SH	216	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	220	clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
92489120	221	clock-names = "fck";
cbe1f838	222	power-domains = <&cpg_clocks>;
4c84c1b3 WS	223	status = "disabled";
	224	};
	225
	226	scif6: serial@e800a000 {
	227	compatible = "renesas,scif-r7s72100", "renesas,scif";
	228	reg = <0xe800a000 64>;
16af4e97 SH	229	interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	233	clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
92489120	234	clock-names = "fck";
cbe1f838	235	power-domains = <&cpg_clocks>;
4c84c1b3 WS	236	status = "disabled";
	237	};
	238
	239	scif7: serial@e800a800 {
	240	compatible = "renesas,scif-r7s72100", "renesas,scif";
	241	reg = <0xe800a800 64>;
16af4e97 SH	242	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
	243	<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
	244	<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
	245	<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
4c84c1b3	246	clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
92489120	247	clock-names = "fck";
cbe1f838	248	power-domains = <&cpg_clocks>;
4c84c1b3 WS	249	status = "disabled";
	250	};
	251
4b18e83f GU	252	spi0: spi@e800c800 {
	253	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	254	reg = <0xe800c800 0x24>;
16af4e97 SH	255	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	258	interrupt-names = "error", "rx", "tx";
52eed4f5	259	clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
cbe1f838	260	power-domains = <&cpg_clocks>;
4b18e83f GU	261	num-cs = <1>;
	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264	status = "disabled";
	265	};
	266
	267	spi1: spi@e800d000 {
	268	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	269	reg = <0xe800d000 0x24>;
16af4e97 SH	270	interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	271	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	272	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	273	interrupt-names = "error", "rx", "tx";
52eed4f5	274	clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
cbe1f838	275	power-domains = <&cpg_clocks>;
4b18e83f GU	276	num-cs = <1>;
	277	#address-cells = <1>;
	278	#size-cells = <0>;
	279	status = "disabled";
	280	};
	281
	282	spi2: spi@e800d800 {
	283	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	284	reg = <0xe800d800 0x24>;
16af4e97 SH	285	interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	286	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	287	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	288	interrupt-names = "error", "rx", "tx";
52eed4f5	289	clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
cbe1f838	290	power-domains = <&cpg_clocks>;
4b18e83f GU	291	num-cs = <1>;
	292	#address-cells = <1>;
	293	#size-cells = <0>;
	294	status = "disabled";
	295	};
	296
	297	spi3: spi@e800e000 {
	298	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	299	reg = <0xe800e000 0x24>;
16af4e97 SH	300	interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	301	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	302	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	303	interrupt-names = "error", "rx", "tx";
52eed4f5	304	clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
cbe1f838	305	power-domains = <&cpg_clocks>;
4b18e83f GU	306	num-cs = <1>;
	307	#address-cells = <1>;
	308	#size-cells = <0>;
	309	status = "disabled";
	310	};
	311
	312	spi4: spi@e800e800 {
	313	compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
	314	reg = <0xe800e800 0x24>;
16af4e97 SH	315	interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	316	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	317	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
4b18e83f	318	interrupt-names = "error", "rx", "tx";
52eed4f5	319	clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
cbe1f838	320	power-domains = <&cpg_clocks>;
4b18e83f GU	321	num-cs = <1>;
	322	#address-cells = <1>;
	323	#size-cells = <0>;
	324	status = "disabled";
	325	};
005980c0 UH	326
005980c0 UH	327	gic: interrupt-controller@e8201000 {
d9e1a0ef	328	compatible = "arm,pl390";
005980c0 UH	329	#interrupt-cells = <3>;
	330	#address-cells = <0>;
	331	interrupt-controller;
	332	reg = <0xe8201000 0x1000>,
	333	<0xe8202000 0x1000>;
	334	};
	335
	336	i2c0: i2c@fcfee000 {
	337	#address-cells = <1>;
	338	#size-cells = <0>;
	339	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	340	reg = <0xfcfee000 0x44>;
16af4e97 SH	341	interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	342	<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
	343	<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
	344	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	345	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	346	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	347	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	348	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	349	clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
005980c0 UH	350	clock-frequency = <100000>;
cbe1f838	351	power-domains = <&cpg_clocks>;
005980c0 UH	352	status = "disabled";
	353	};
	354
	355	i2c1: i2c@fcfee400 {
	356	#address-cells = <1>;
	357	#size-cells = <0>;
	358	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	359	reg = <0xfcfee400 0x44>;
16af4e97 SH	360	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	361	<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
	362	<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
	363	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	364	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	365	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	366	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	367	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	368	clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
005980c0 UH	369	clock-frequency = <100000>;
cbe1f838	370	power-domains = <&cpg_clocks>;
005980c0 UH	371	status = "disabled";
	372	};
	373
	374	i2c2: i2c@fcfee800 {
	375	#address-cells = <1>;
	376	#size-cells = <0>;
	377	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	378	reg = <0xfcfee800 0x44>;
16af4e97 SH	379	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	380	<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
	381	<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
	382	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
	383	<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	384	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
	385	<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	386	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	387	clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
005980c0 UH	388	clock-frequency = <100000>;
cbe1f838	389	power-domains = <&cpg_clocks>;
005980c0 UH	390	status = "disabled";
	391	};
	392
	393	i2c3: i2c@fcfeec00 {
	394	#address-cells = <1>;
	395	#size-cells = <0>;
	396	compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
	397	reg = <0xfcfeec00 0x44>;
16af4e97 SH	398	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	399	<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
	400	<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
	401	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	402	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	403	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	404	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	405	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	406	clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
005980c0 UH	407	clock-frequency = <100000>;
cbe1f838	408	power-domains = <&cpg_clocks>;
005980c0 UH	409	status = "disabled";
	410	};
	411
	412	mtu2: timer@fcff0000 {
	413	compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
	414	reg = <0xfcff0000 0x400>;
16af4e97	415	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
005980c0 UH	416	interrupt-names = "tgi0a";
	417	clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
	418	clock-names = "fck";
cbe1f838	419	power-domains = <&cpg_clocks>;
005980c0 UH	420	status = "disabled";
005980c0 UH	421	};
e3da5b36	422	};