projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| eccf0607 MD |
1 | /* |
| 2 | * Device Tree Source for the r8a73a4 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
| 5 | * Copyright (C) 2013 Magnus Damm | |
| 6 | * | |
| 7 | * This file is licensed under the terms of the GNU General Public License | |
| 8 | * version 2. This program is licensed "as is" without any warranty of any | |
| 9 | * kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| eccf0607 MD |
12 | / { |
| 13 | compatible = "renesas,r8a73a4"; | |
| 14 | interrupt-parent = <&gic>; | |
| 26a0d2d4 TY |
15 | #address-cells = <2>; |
| 16 | #size-cells = <2>; | |
| eccf0607 MD |
17 | |
| 18 | cpus { | |
| 19 | #address-cells = <1>; | |
| 20 | #size-cells = <0>; | |
| 21 | ||
| 22 | cpu0: cpu@0 { | |
| 23 | device_type = "cpu"; | |
| 24 | compatible = "arm,cortex-a15"; | |
| 25 | reg = <0>; | |
| 26 | clock-frequency = <1500000000>; | |
| 27 | }; | |
| 28 | }; | |
| 29 | ||
| 30 | gic: interrupt-controller@f1001000 { | |
| 31 | compatible = "arm,cortex-a15-gic"; | |
| 32 | #interrupt-cells = <3>; | |
| 33 | #address-cells = <0>; | |
| 34 | interrupt-controller; | |
| 26a0d2d4 TY |
35 | reg = <0 0xf1001000 0 0x1000>, |
| 36 | <0 0xf1002000 0 0x1000>, | |
| 37 | <0 0xf1004000 0 0x2000>, | |
| 38 | <0 0xf1006000 0 0x2000>; | |
| eccf0607 MD |
39 | interrupts = <1 9 0xf04>; |
| 40 | ||
| 41 | gic-cpuif@4 { | |
| 42 | compatible = "arm,gic-cpuif"; | |
| 43 | cpuif-id = <4>; | |
| 44 | cpu = <&cpu0>; | |
| 45 | }; | |
| 46 | }; | |
| 47 | ||
| 48 | timer { | |
| 49 | compatible = "arm,armv7-timer"; | |
| 50 | interrupts = <1 13 0xf08>, | |
| 51 | <1 14 0xf08>, | |
| 52 | <1 11 0xf08>, | |
| 53 | <1 10 0xf08>; | |
| 54 | }; | |
| 984ca295 MD |
55 | |
| 56 | irqc0: interrupt-controller@e61c0000 { | |
| 57 | compatible = "renesas,irqc"; | |
| 58 | #interrupt-cells = <2>; | |
| 59 | interrupt-controller; | |
| 26a0d2d4 | 60 | reg = <0 0xe61c0000 0 0x200>; |
| 984ca295 MD |
61 | interrupt-parent = <&gic>; |
| 62 | interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, | |
| 63 | <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, | |
| 64 | <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, | |
| 65 | <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, | |
| 66 | <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, | |
| 67 | <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, | |
| 68 | <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, | |
| 69 | <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; | |
| 70 | }; | |
| 71 | ||
| 72 | irqc1: interrupt-controller@e61c0200 { | |
| 73 | compatible = "renesas,irqc"; | |
| 74 | #interrupt-cells = <2>; | |
| 75 | interrupt-controller; | |
| 26a0d2d4 | 76 | reg = <0 0xe61c0200 0 0x200>; |
| 984ca295 MD |
77 | interrupt-parent = <&gic>; |
| 78 | interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, | |
| 79 | <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, | |
| 80 | <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, | |
| 81 | <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, | |
| 82 | <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, | |
| 83 | <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, | |
| 84 | <0 56 4>, <0 57 4>; | |
| 85 | }; | |
| 86 | ||
| c91cf2fa KM |
87 | thermal@e61f0000 { |
| 88 | compatible = "renesas,rcar-thermal"; | |
| 26a0d2d4 TY |
89 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
| 90 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; | |
| c91cf2fa KM |
91 | interrupt-parent = <&gic>; |
| 92 | interrupts = <0 69 4>; | |
| 93 | }; | |
| eccf0607 | 94 | }; |