Commit | Line | Data |
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eccf0607 MD |
1 | /* |
2 | * Device Tree Source for the r8a73a4 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
a76809a3 | 12 | #include <dt-bindings/clock/r8a73a4-clock.h> |
5f75e73c LP |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
eccf0607 MD |
16 | / { |
17 | compatible = "renesas,r8a73a4"; | |
18 | interrupt-parent = <&gic>; | |
26a0d2d4 TY |
19 | #address-cells = <2>; |
20 | #size-cells = <2>; | |
eccf0607 MD |
21 | |
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu0: cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a15"; | |
29 | reg = <0>; | |
30 | clock-frequency = <1500000000>; | |
7b9ad9a0 | 31 | power-domains = <&pd_a2sl>; |
eccf0607 MD |
32 | }; |
33 | }; | |
34 | ||
7b9ad9a0 GU |
35 | ptm { |
36 | compatible = "arm,coresight-etm3x"; | |
37 | power-domains = <&pd_d4>; | |
38 | }; | |
39 | ||
eccf0607 MD |
40 | timer { |
41 | compatible = "arm,armv7-timer"; | |
5f75e73c LP |
42 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
43 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
44 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
45 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
eccf0607 | 46 | }; |
984ca295 | 47 | |
35dd549c GU |
48 | dbsc1: memory-controller@e6790000 { |
49 | compatible = "renesas,dbsc-r8a73a4"; | |
50 | reg = <0 0xe6790000 0 0x10000>; | |
7b9ad9a0 | 51 | power-domains = <&pd_a3bc>; |
35dd549c GU |
52 | }; |
53 | ||
54 | dbsc2: memory-controller@e67a0000 { | |
55 | compatible = "renesas,dbsc-r8a73a4"; | |
56 | reg = <0 0xe67a0000 0 0x10000>; | |
7b9ad9a0 | 57 | power-domains = <&pd_a3bc>; |
35dd549c GU |
58 | }; |
59 | ||
7300505a UH |
60 | dmac: dma-multiplexer { |
61 | compatible = "renesas,shdma-mux"; | |
62 | #dma-cells = <1>; | |
63 | dma-channels = <20>; | |
64 | dma-requests = <256>; | |
65 | #address-cells = <2>; | |
66 | #size-cells = <2>; | |
67 | ranges; | |
68 | ||
69 | dma0: dma-controller@e6700020 { | |
70 | compatible = "renesas,shdma-r8a73a4"; | |
71 | reg = <0 0xe6700020 0 0x89e0>; | |
72 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
73 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
74 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
75 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
76 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
77 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
78 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
79 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
80 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
81 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
82 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
83 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
84 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
85 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
86 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
87 | 0 214 IRQ_TYPE_LEVEL_HIGH | |
88 | 0 215 IRQ_TYPE_LEVEL_HIGH | |
89 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
90 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
91 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
92 | 0 219 IRQ_TYPE_LEVEL_HIGH>; | |
93 | interrupt-names = "error", | |
94 | "ch0", "ch1", "ch2", "ch3", | |
95 | "ch4", "ch5", "ch6", "ch7", | |
96 | "ch8", "ch9", "ch10", "ch11", | |
97 | "ch12", "ch13", "ch14", "ch15", | |
98 | "ch16", "ch17", "ch18", "ch19"; | |
662dd64f | 99 | clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; |
7b9ad9a0 | 100 | power-domains = <&pd_a3sp>; |
7300505a UH |
101 | }; |
102 | }; | |
103 | ||
7300505a UH |
104 | i2c5: i2c@e60b0000 { |
105 | #address-cells = <1>; | |
106 | #size-cells = <0>; | |
7e9ad4d0 | 107 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
7300505a UH |
108 | reg = <0 0xe60b0000 0 0x428>; |
109 | interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f | 110 | clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; |
7b9ad9a0 | 111 | power-domains = <&pd_a3sp>; |
f7b65230 SH |
112 | |
113 | status = "disabled"; | |
114 | }; | |
115 | ||
116 | cmt1: timer@e6130000 { | |
2cd823fc | 117 | compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; |
f7b65230 SH |
118 | reg = <0 0xe6130000 0 0x1004>; |
119 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
120 | clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; |
121 | clock-names = "fck"; | |
7b9ad9a0 | 122 | power-domains = <&pd_c5>; |
f7b65230 SH |
123 | |
124 | renesas,channels-mask = <0xff>; | |
125 | ||
7300505a UH |
126 | status = "disabled"; |
127 | }; | |
128 | ||
984ca295 | 129 | irqc0: interrupt-controller@e61c0000 { |
34abee39 | 130 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
984ca295 MD |
131 | #interrupt-cells = <2>; |
132 | interrupt-controller; | |
26a0d2d4 | 133 | reg = <0 0xe61c0000 0 0x200>; |
5f75e73c LP |
134 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
135 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
136 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
137 | <0 3 IRQ_TYPE_LEVEL_HIGH>, | |
138 | <0 4 IRQ_TYPE_LEVEL_HIGH>, | |
139 | <0 5 IRQ_TYPE_LEVEL_HIGH>, | |
140 | <0 6 IRQ_TYPE_LEVEL_HIGH>, | |
141 | <0 7 IRQ_TYPE_LEVEL_HIGH>, | |
142 | <0 8 IRQ_TYPE_LEVEL_HIGH>, | |
143 | <0 9 IRQ_TYPE_LEVEL_HIGH>, | |
144 | <0 10 IRQ_TYPE_LEVEL_HIGH>, | |
145 | <0 11 IRQ_TYPE_LEVEL_HIGH>, | |
146 | <0 12 IRQ_TYPE_LEVEL_HIGH>, | |
147 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
148 | <0 14 IRQ_TYPE_LEVEL_HIGH>, | |
149 | <0 15 IRQ_TYPE_LEVEL_HIGH>, | |
150 | <0 16 IRQ_TYPE_LEVEL_HIGH>, | |
151 | <0 17 IRQ_TYPE_LEVEL_HIGH>, | |
152 | <0 18 IRQ_TYPE_LEVEL_HIGH>, | |
153 | <0 19 IRQ_TYPE_LEVEL_HIGH>, | |
154 | <0 20 IRQ_TYPE_LEVEL_HIGH>, | |
155 | <0 21 IRQ_TYPE_LEVEL_HIGH>, | |
156 | <0 22 IRQ_TYPE_LEVEL_HIGH>, | |
157 | <0 23 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <0 24 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <0 25 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <0 26 IRQ_TYPE_LEVEL_HIGH>, | |
161 | <0 27 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <0 28 IRQ_TYPE_LEVEL_HIGH>, | |
163 | <0 29 IRQ_TYPE_LEVEL_HIGH>, | |
164 | <0 30 IRQ_TYPE_LEVEL_HIGH>, | |
165 | <0 31 IRQ_TYPE_LEVEL_HIGH>; | |
1c2a7eb7 | 166 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
7b9ad9a0 | 167 | power-domains = <&pd_c4>; |
984ca295 MD |
168 | }; |
169 | ||
170 | irqc1: interrupt-controller@e61c0200 { | |
34abee39 | 171 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
984ca295 MD |
172 | #interrupt-cells = <2>; |
173 | interrupt-controller; | |
26a0d2d4 | 174 | reg = <0 0xe61c0200 0 0x200>; |
5f75e73c LP |
175 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, |
176 | <0 33 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <0 34 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <0 35 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <0 36 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <0 37 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <0 38 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <0 39 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <0 40 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <0 41 IRQ_TYPE_LEVEL_HIGH>, | |
185 | <0 42 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <0 43 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <0 44 IRQ_TYPE_LEVEL_HIGH>, | |
188 | <0 45 IRQ_TYPE_LEVEL_HIGH>, | |
189 | <0 46 IRQ_TYPE_LEVEL_HIGH>, | |
190 | <0 47 IRQ_TYPE_LEVEL_HIGH>, | |
191 | <0 48 IRQ_TYPE_LEVEL_HIGH>, | |
192 | <0 49 IRQ_TYPE_LEVEL_HIGH>, | |
193 | <0 50 IRQ_TYPE_LEVEL_HIGH>, | |
194 | <0 51 IRQ_TYPE_LEVEL_HIGH>, | |
195 | <0 52 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <0 53 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <0 55 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <0 56 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <0 57 IRQ_TYPE_LEVEL_HIGH>; | |
1c2a7eb7 | 201 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
7b9ad9a0 | 202 | power-domains = <&pd_c4>; |
984ca295 MD |
203 | }; |
204 | ||
e4ba0a9b GU |
205 | pfc: pfc@e6050000 { |
206 | compatible = "renesas,pfc-r8a73a4"; | |
207 | reg = <0 0xe6050000 0 0x9000>; | |
208 | gpio-controller; | |
209 | #gpio-cells = <2>; | |
210 | interrupts-extended = | |
211 | <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, | |
212 | <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, | |
213 | <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, | |
214 | <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, | |
215 | <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, | |
216 | <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, | |
217 | <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, | |
218 | <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, | |
219 | <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, | |
220 | <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, | |
221 | <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, | |
222 | <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, | |
223 | <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, | |
224 | <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, | |
225 | <&irqc1 24 0>, <&irqc1 25 0>; | |
7b9ad9a0 | 226 | power-domains = <&pd_c5>; |
e4ba0a9b GU |
227 | }; |
228 | ||
c91cf2fa | 229 | thermal@e61f0000 { |
a2cfaa74 | 230 | compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; |
26a0d2d4 TY |
231 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
232 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; | |
5f75e73c | 233 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 234 | clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; |
7b9ad9a0 | 235 | power-domains = <&pd_c5>; |
c91cf2fa | 236 | }; |
f98c1069 GL |
237 | |
238 | i2c0: i2c@e6500000 { | |
239 | #address-cells = <1>; | |
240 | #size-cells = <0>; | |
7e9ad4d0 | 241 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 242 | reg = <0 0xe6500000 0 0x428>; |
d6dd1313 | 243 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 244 | clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; |
7b9ad9a0 | 245 | power-domains = <&pd_a3sp>; |
eda3a4fa | 246 | status = "disabled"; |
f98c1069 GL |
247 | }; |
248 | ||
249 | i2c1: i2c@e6510000 { | |
250 | #address-cells = <1>; | |
251 | #size-cells = <0>; | |
7e9ad4d0 | 252 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 253 | reg = <0 0xe6510000 0 0x428>; |
d6dd1313 | 254 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 255 | clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; |
7b9ad9a0 | 256 | power-domains = <&pd_a3sp>; |
eda3a4fa | 257 | status = "disabled"; |
f98c1069 GL |
258 | }; |
259 | ||
260 | i2c2: i2c@e6520000 { | |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
7e9ad4d0 | 263 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 264 | reg = <0 0xe6520000 0 0x428>; |
d6dd1313 | 265 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 266 | clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; |
7b9ad9a0 | 267 | power-domains = <&pd_a3sp>; |
eda3a4fa | 268 | status = "disabled"; |
f98c1069 GL |
269 | }; |
270 | ||
271 | i2c3: i2c@e6530000 { | |
272 | #address-cells = <1>; | |
273 | #size-cells = <0>; | |
7e9ad4d0 | 274 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 275 | reg = <0 0xe6530000 0 0x428>; |
d6dd1313 | 276 | interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 277 | clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; |
7b9ad9a0 | 278 | power-domains = <&pd_a3sp>; |
eda3a4fa | 279 | status = "disabled"; |
f98c1069 GL |
280 | }; |
281 | ||
282 | i2c4: i2c@e6540000 { | |
283 | #address-cells = <1>; | |
284 | #size-cells = <0>; | |
7e9ad4d0 | 285 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 286 | reg = <0 0xe6540000 0 0x428>; |
5f75e73c | 287 | interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 288 | clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; |
7b9ad9a0 | 289 | power-domains = <&pd_a3sp>; |
eda3a4fa | 290 | status = "disabled"; |
f98c1069 GL |
291 | }; |
292 | ||
f98c1069 GL |
293 | i2c6: i2c@e6550000 { |
294 | #address-cells = <1>; | |
295 | #size-cells = <0>; | |
7e9ad4d0 | 296 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 297 | reg = <0 0xe6550000 0 0x428>; |
5f75e73c | 298 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 299 | clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; |
7b9ad9a0 | 300 | power-domains = <&pd_a3sp>; |
eda3a4fa | 301 | status = "disabled"; |
f98c1069 GL |
302 | }; |
303 | ||
304 | i2c7: i2c@e6560000 { | |
305 | #address-cells = <1>; | |
306 | #size-cells = <0>; | |
7e9ad4d0 | 307 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 308 | reg = <0 0xe6560000 0 0x428>; |
5f75e73c | 309 | interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 310 | clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; |
7b9ad9a0 | 311 | power-domains = <&pd_a3sp>; |
eda3a4fa | 312 | status = "disabled"; |
f98c1069 GL |
313 | }; |
314 | ||
315 | i2c8: i2c@e6570000 { | |
316 | #address-cells = <1>; | |
317 | #size-cells = <0>; | |
7e9ad4d0 | 318 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 319 | reg = <0 0xe6570000 0 0x428>; |
5f75e73c | 320 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 321 | clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; |
7b9ad9a0 | 322 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
323 | status = "disabled"; |
324 | }; | |
325 | ||
0b3a0ef6 | 326 | scifb0: serial@e6c20000 { |
94f1a03d SH |
327 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
328 | reg = <0 0xe6c20000 0 0x100>; | |
329 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
330 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; |
331 | clock-names = "sci_ick"; | |
7b9ad9a0 | 332 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
333 | status = "disabled"; |
334 | }; | |
335 | ||
0b3a0ef6 | 336 | scifb1: serial@e6c30000 { |
94f1a03d SH |
337 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
338 | reg = <0 0xe6c30000 0 0x100>; | |
339 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
340 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; |
341 | clock-names = "sci_ick"; | |
7b9ad9a0 | 342 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
343 | status = "disabled"; |
344 | }; | |
345 | ||
7300505a UH |
346 | scifa0: serial@e6c40000 { |
347 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; | |
348 | reg = <0 0xe6c40000 0 0x100>; | |
349 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
350 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; |
351 | clock-names = "sci_ick"; | |
7b9ad9a0 | 352 | power-domains = <&pd_a3sp>; |
7300505a UH |
353 | status = "disabled"; |
354 | }; | |
355 | ||
356 | scifa1: serial@e6c50000 { | |
357 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; | |
358 | reg = <0 0xe6c50000 0 0x100>; | |
359 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
360 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; |
361 | clock-names = "sci_ick"; | |
7b9ad9a0 | 362 | power-domains = <&pd_a3sp>; |
7300505a UH |
363 | status = "disabled"; |
364 | }; | |
365 | ||
0b3a0ef6 | 366 | scifb2: serial@e6ce0000 { |
94f1a03d SH |
367 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
368 | reg = <0 0xe6ce0000 0 0x100>; | |
369 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
370 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; |
371 | clock-names = "sci_ick"; | |
7b9ad9a0 | 372 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
373 | status = "disabled"; |
374 | }; | |
375 | ||
0b3a0ef6 | 376 | scifb3: serial@e6cf0000 { |
94f1a03d SH |
377 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
378 | reg = <0 0xe6cf0000 0 0x100>; | |
379 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f UH |
380 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; |
381 | clock-names = "sci_ick"; | |
7b9ad9a0 | 382 | power-domains = <&pd_c4>; |
eda3a4fa | 383 | status = "disabled"; |
f98c1069 | 384 | }; |
369ee2db | 385 | |
43304a5f | 386 | sdhi0: sd@ee100000 { |
df1d0584 | 387 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 388 | reg = <0 0xee100000 0 0x100>; |
5f75e73c | 389 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 390 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; |
7b9ad9a0 | 391 | power-domains = <&pd_a3sp>; |
369ee2db GL |
392 | cap-sd-highspeed; |
393 | status = "disabled"; | |
394 | }; | |
395 | ||
43304a5f | 396 | sdhi1: sd@ee120000 { |
df1d0584 | 397 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 398 | reg = <0 0xee120000 0 0x100>; |
5f75e73c | 399 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 400 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; |
7b9ad9a0 | 401 | power-domains = <&pd_a3sp>; |
369ee2db GL |
402 | cap-sd-highspeed; |
403 | status = "disabled"; | |
404 | }; | |
405 | ||
43304a5f | 406 | sdhi2: sd@ee140000 { |
df1d0584 | 407 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 408 | reg = <0 0xee140000 0 0x100>; |
5f75e73c | 409 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 410 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; |
7b9ad9a0 | 411 | power-domains = <&pd_a3sp>; |
369ee2db GL |
412 | cap-sd-highspeed; |
413 | status = "disabled"; | |
414 | }; | |
7300505a UH |
415 | |
416 | mmcif0: mmc@ee200000 { | |
417 | compatible = "renesas,sh-mmcif"; | |
418 | reg = <0 0xee200000 0 0x80>; | |
419 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f | 420 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; |
7b9ad9a0 | 421 | power-domains = <&pd_a3sp>; |
7300505a UH |
422 | reg-io-width = <4>; |
423 | status = "disabled"; | |
424 | }; | |
425 | ||
426 | mmcif1: mmc@ee220000 { | |
427 | compatible = "renesas,sh-mmcif"; | |
428 | reg = <0 0xee220000 0 0x80>; | |
429 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; | |
662dd64f | 430 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; |
7b9ad9a0 | 431 | power-domains = <&pd_a3sp>; |
7300505a UH |
432 | reg-io-width = <4>; |
433 | status = "disabled"; | |
434 | }; | |
435 | ||
436 | gic: interrupt-controller@f1001000 { | |
eaec1d67 | 437 | compatible = "arm,gic-400"; |
7300505a UH |
438 | #interrupt-cells = <3>; |
439 | #address-cells = <0>; | |
440 | interrupt-controller; | |
441 | reg = <0 0xf1001000 0 0x1000>, | |
442 | <0 0xf1002000 0 0x1000>, | |
443 | <0 0xf1004000 0 0x2000>, | |
444 | <0 0xf1006000 0 0x2000>; | |
445 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
446 | }; | |
a76809a3 | 447 | |
271b3ad2 GU |
448 | bsc: bus@fec10000 { |
449 | compatible = "renesas,bsc-r8a73a4", "renesas,bsc", | |
450 | "simple-pm-bus"; | |
451 | #address-cells = <1>; | |
452 | #size-cells = <1>; | |
453 | ranges = <0 0 0 0x20000000>; | |
454 | reg = <0 0xfec10000 0 0x400>; | |
455 | clocks = <&zb_clk>; | |
7b9ad9a0 | 456 | power-domains = <&pd_c4>; |
271b3ad2 GU |
457 | }; |
458 | ||
a76809a3 UH |
459 | clocks { |
460 | #address-cells = <2>; | |
461 | #size-cells = <2>; | |
462 | ranges; | |
463 | ||
464 | /* External root clocks */ | |
465 | extalr_clk: extalr_clk { | |
466 | compatible = "fixed-clock"; | |
467 | #clock-cells = <0>; | |
468 | clock-frequency = <32768>; | |
469 | clock-output-names = "extalr"; | |
470 | }; | |
471 | extal1_clk: extal1_clk { | |
472 | compatible = "fixed-clock"; | |
473 | #clock-cells = <0>; | |
474 | clock-frequency = <25000000>; | |
475 | clock-output-names = "extal1"; | |
476 | }; | |
477 | extal2_clk: extal2_clk { | |
478 | compatible = "fixed-clock"; | |
479 | #clock-cells = <0>; | |
480 | clock-frequency = <48000000>; | |
481 | clock-output-names = "extal2"; | |
482 | }; | |
483 | fsiack_clk: fsiack_clk { | |
484 | compatible = "fixed-clock"; | |
485 | #clock-cells = <0>; | |
486 | /* This value must be overridden by the board. */ | |
487 | clock-frequency = <0>; | |
488 | clock-output-names = "fsiack"; | |
489 | }; | |
490 | fsibck_clk: fsibck_clk { | |
491 | compatible = "fixed-clock"; | |
492 | #clock-cells = <0>; | |
493 | /* This value must be overridden by the board. */ | |
494 | clock-frequency = <0>; | |
495 | clock-output-names = "fsibck"; | |
496 | }; | |
497 | ||
498 | /* Special CPG clocks */ | |
499 | cpg_clocks: cpg_clocks@e6150000 { | |
500 | compatible = "renesas,r8a73a4-cpg-clocks"; | |
501 | reg = <0 0xe6150000 0 0x10000>; | |
502 | clocks = <&extal1_clk>, <&extal2_clk>; | |
503 | #clock-cells = <1>; | |
504 | clock-output-names = "main", "pll0", "pll1", "pll2", | |
505 | "pll2s", "pll2h", "z", "z2", | |
506 | "i", "m3", "b", "m1", "m2", | |
507 | "zx", "zs", "hp"; | |
508 | }; | |
509 | ||
510 | /* Variable factor clocks (DIV6) */ | |
511 | zb_clk: zb_clk@e6150010 { | |
512 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
513 | reg = <0 0xe6150010 0 4>; | |
514 | clocks = <&pll1_div2_clk>, <0>, | |
515 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; | |
516 | #clock-cells = <0>; | |
517 | clock-output-names = "zb"; | |
518 | }; | |
519 | sdhi0_clk: sdhi0_clk@e6150074 { | |
520 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
521 | reg = <0 0xe6150074 0 4>; | |
522 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
523 | <0>, <&extal2_clk>; | |
524 | #clock-cells = <0>; | |
525 | clock-output-names = "sdhi0ck"; | |
526 | }; | |
527 | sdhi1_clk: sdhi1_clk@e6150078 { | |
528 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
529 | reg = <0 0xe6150078 0 4>; | |
530 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
531 | <0>, <&extal2_clk>; | |
532 | #clock-cells = <0>; | |
533 | clock-output-names = "sdhi1ck"; | |
534 | }; | |
535 | sdhi2_clk: sdhi2_clk@e615007c { | |
536 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
537 | reg = <0 0xe615007c 0 4>; | |
538 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
539 | <0>, <&extal2_clk>; | |
540 | #clock-cells = <0>; | |
541 | clock-output-names = "sdhi2ck"; | |
542 | }; | |
543 | mmc0_clk: mmc0_clk@e6150240 { | |
544 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
545 | reg = <0 0xe6150240 0 4>; | |
546 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
547 | <0>, <&extal2_clk>; | |
548 | #clock-cells = <0>; | |
549 | clock-output-names = "mmc0"; | |
550 | }; | |
551 | mmc1_clk: mmc1_clk@e6150244 { | |
552 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
553 | reg = <0 0xe6150244 0 4>; | |
554 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
555 | <0>, <&extal2_clk>; | |
556 | #clock-cells = <0>; | |
557 | clock-output-names = "mmc1"; | |
558 | }; | |
559 | vclk1_clk: vclk1_clk@e6150008 { | |
560 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
561 | reg = <0 0xe6150008 0 4>; | |
562 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
563 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
564 | <&extalr_clk>, <0>, <0>; | |
565 | #clock-cells = <0>; | |
566 | clock-output-names = "vclk1"; | |
567 | }; | |
568 | vclk2_clk: vclk2_clk@e615000c { | |
569 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
570 | reg = <0 0xe615000c 0 4>; | |
571 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
572 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
573 | <&extalr_clk>, <0>, <0>; | |
574 | #clock-cells = <0>; | |
575 | clock-output-names = "vclk2"; | |
576 | }; | |
577 | vclk3_clk: vclk3_clk@e615001c { | |
578 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
579 | reg = <0 0xe615001c 0 4>; | |
580 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
581 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
582 | <&extalr_clk>, <0>, <0>; | |
583 | #clock-cells = <0>; | |
584 | clock-output-names = "vclk3"; | |
585 | }; | |
586 | vclk4_clk: vclk4_clk@e6150014 { | |
587 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
588 | reg = <0 0xe6150014 0 4>; | |
589 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
590 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
591 | <&extalr_clk>, <0>, <0>; | |
592 | #clock-cells = <0>; | |
593 | clock-output-names = "vclk4"; | |
594 | }; | |
595 | vclk5_clk: vclk5_clk@e6150034 { | |
596 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
597 | reg = <0 0xe6150034 0 4>; | |
598 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
599 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
600 | <&extalr_clk>, <0>, <0>; | |
601 | #clock-cells = <0>; | |
602 | clock-output-names = "vclk5"; | |
603 | }; | |
604 | fsia_clk: fsia_clk@e6150018 { | |
605 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
606 | reg = <0 0xe6150018 0 4>; | |
607 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
608 | <&fsiack_clk>, <0>; | |
609 | #clock-cells = <0>; | |
610 | clock-output-names = "fsia"; | |
611 | }; | |
612 | fsib_clk: fsib_clk@e6150090 { | |
613 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
614 | reg = <0 0xe6150090 0 4>; | |
615 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
616 | <&fsibck_clk>, <0>; | |
617 | #clock-cells = <0>; | |
618 | clock-output-names = "fsib"; | |
619 | }; | |
620 | mp_clk: mp_clk@e6150080 { | |
621 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
622 | reg = <0 0xe6150080 0 4>; | |
623 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
624 | <&extal2_clk>, <&extal2_clk>; | |
625 | #clock-cells = <0>; | |
626 | clock-output-names = "mp"; | |
627 | }; | |
628 | m4_clk: m4_clk@e6150098 { | |
629 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
630 | reg = <0 0xe6150098 0 4>; | |
631 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; | |
632 | #clock-cells = <0>; | |
633 | clock-output-names = "m4"; | |
634 | }; | |
635 | hsi_clk: hsi_clk@e615026c { | |
636 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
637 | reg = <0 0xe615026c 0 4>; | |
638 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, | |
639 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; | |
640 | #clock-cells = <0>; | |
641 | clock-output-names = "hsi"; | |
642 | }; | |
643 | spuv_clk: spuv_clk@e6150094 { | |
644 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
645 | reg = <0 0xe6150094 0 4>; | |
646 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
647 | <&extal2_clk>, <&extal2_clk>; | |
648 | #clock-cells = <0>; | |
649 | clock-output-names = "spuv"; | |
650 | }; | |
651 | ||
652 | /* Fixed factor clocks */ | |
653 | main_div2_clk: main_div2_clk { | |
654 | compatible = "fixed-factor-clock"; | |
655 | clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; | |
656 | #clock-cells = <0>; | |
657 | clock-div = <2>; | |
658 | clock-mult = <1>; | |
659 | clock-output-names = "main_div2"; | |
660 | }; | |
661 | pll0_div2_clk: pll0_div2_clk { | |
662 | compatible = "fixed-factor-clock"; | |
663 | clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; | |
664 | #clock-cells = <0>; | |
665 | clock-div = <2>; | |
666 | clock-mult = <1>; | |
667 | clock-output-names = "pll0_div2"; | |
668 | }; | |
669 | pll1_div2_clk: pll1_div2_clk { | |
670 | compatible = "fixed-factor-clock"; | |
671 | clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; | |
672 | #clock-cells = <0>; | |
673 | clock-div = <2>; | |
674 | clock-mult = <1>; | |
675 | clock-output-names = "pll1_div2"; | |
676 | }; | |
677 | extal1_div2_clk: extal1_div2_clk { | |
678 | compatible = "fixed-factor-clock"; | |
679 | clocks = <&extal1_clk>; | |
680 | #clock-cells = <0>; | |
681 | clock-div = <2>; | |
682 | clock-mult = <1>; | |
683 | clock-output-names = "extal1_div2"; | |
684 | }; | |
685 | ||
686 | /* Gate clocks */ | |
687 | mstp2_clks: mstp2_clks@e6150138 { | |
688 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
689 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
690 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
691 | <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; | |
692 | #clock-cells = <1>; | |
693 | clock-indices = < | |
694 | R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 | |
695 | R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 | |
696 | R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 | |
697 | R8A73A4_CLK_DMAC | |
698 | >; | |
699 | clock-output-names = | |
700 | "scifa0", "scifa1", "scifb0", "scifb1", | |
701 | "scifb2", "scifb3", "dmac"; | |
702 | }; | |
703 | mstp3_clks: mstp3_clks@e615013c { | |
704 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
705 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
706 | clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, | |
707 | <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, | |
708 | <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, | |
709 | <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks | |
710 | R8A73A4_CLK_HP>, <&cpg_clocks | |
711 | R8A73A4_CLK_HP>, <&extalr_clk>; | |
712 | #clock-cells = <1>; | |
713 | clock-indices = < | |
714 | R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 | |
715 | R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 | |
716 | R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 | |
717 | R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 | |
718 | R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 | |
719 | R8A73A4_CLK_CMT1 | |
720 | >; | |
721 | clock-output-names = | |
722 | "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", | |
723 | "mmcif0", "iic6", "iic7", "iic0", "iic1", | |
724 | "cmt1"; | |
725 | }; | |
726 | mstp4_clks: mstp4_clks@e6150140 { | |
727 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
728 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1c2a7eb7 GU |
729 | clocks = <&main_div2_clk>, <&main_div2_clk>, |
730 | <&cpg_clocks R8A73A4_CLK_HP>, | |
a76809a3 UH |
731 | <&cpg_clocks R8A73A4_CLK_HP>; |
732 | #clock-cells = <1>; | |
733 | clock-indices = < | |
1c2a7eb7 GU |
734 | R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 |
735 | R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 | |
a76809a3 UH |
736 | >; |
737 | clock-output-names = | |
1c2a7eb7 | 738 | "irqc", "iic5", "iic4", "iic3"; |
a76809a3 UH |
739 | }; |
740 | mstp5_clks: mstp5_clks@e6150144 { | |
741 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
742 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
743 | clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; | |
744 | #clock-cells = <1>; | |
745 | clock-indices = < | |
746 | R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 | |
747 | >; | |
748 | clock-output-names = | |
749 | "thermal", "iic8"; | |
750 | }; | |
751 | }; | |
7b9ad9a0 GU |
752 | |
753 | sysc: system-controller@e6180000 { | |
754 | compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; | |
755 | reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; | |
756 | ||
757 | pm-domains { | |
758 | pd_c5: c5 { | |
759 | #address-cells = <1>; | |
760 | #size-cells = <0>; | |
761 | #power-domain-cells = <0>; | |
762 | ||
763 | pd_c4: c4@0 { | |
764 | reg = <0>; | |
765 | #address-cells = <1>; | |
766 | #size-cells = <0>; | |
767 | #power-domain-cells = <0>; | |
768 | ||
769 | pd_a3sg: a3sg@16 { | |
770 | reg = <16>; | |
771 | #power-domain-cells = <0>; | |
772 | }; | |
773 | ||
774 | pd_a3ex: a3ex@17 { | |
775 | reg = <17>; | |
776 | #power-domain-cells = <0>; | |
777 | }; | |
778 | ||
779 | pd_a3sp: a3sp@18 { | |
780 | reg = <18>; | |
781 | #address-cells = <1>; | |
782 | #size-cells = <0>; | |
783 | #power-domain-cells = <0>; | |
784 | ||
785 | pd_a2us: a2us@19 { | |
786 | reg = <19>; | |
787 | #power-domain-cells = <0>; | |
788 | }; | |
789 | }; | |
790 | ||
791 | pd_a3sm: a3sm@20 { | |
792 | reg = <20>; | |
793 | #address-cells = <1>; | |
794 | #size-cells = <0>; | |
795 | #power-domain-cells = <0>; | |
796 | ||
797 | pd_a2sl: a2sl@21 { | |
798 | reg = <21>; | |
799 | #power-domain-cells = <0>; | |
800 | }; | |
801 | }; | |
802 | ||
803 | pd_a3km: a3km@22 { | |
804 | reg = <22>; | |
805 | #address-cells = <1>; | |
806 | #size-cells = <0>; | |
807 | #power-domain-cells = <0>; | |
808 | ||
809 | pd_a2kl: a2kl@23 { | |
810 | reg = <23>; | |
811 | #power-domain-cells = <0>; | |
812 | }; | |
813 | }; | |
814 | }; | |
815 | ||
816 | pd_c4ma: c4ma@1 { | |
817 | reg = <1>; | |
818 | #power-domain-cells = <0>; | |
819 | }; | |
820 | ||
821 | pd_c4cl: c4cl@2 { | |
822 | reg = <2>; | |
823 | #power-domain-cells = <0>; | |
824 | }; | |
825 | ||
826 | pd_d4: d4@3 { | |
827 | reg = <3>; | |
828 | #power-domain-cells = <0>; | |
829 | }; | |
830 | ||
831 | pd_a4bc: a4bc@4 { | |
832 | reg = <4>; | |
833 | #address-cells = <1>; | |
834 | #size-cells = <0>; | |
835 | #power-domain-cells = <0>; | |
836 | ||
837 | pd_a3bc: a3bc@5 { | |
838 | reg = <5>; | |
839 | #power-domain-cells = <0>; | |
840 | }; | |
841 | }; | |
842 | ||
843 | pd_a4l: a4l@6 { | |
844 | reg = <6>; | |
845 | #power-domain-cells = <0>; | |
846 | }; | |
847 | ||
848 | pd_a4lc: a4lc@7 { | |
849 | reg = <7>; | |
850 | #power-domain-cells = <0>; | |
851 | }; | |
852 | ||
853 | pd_a4mp: a4mp@8 { | |
854 | reg = <8>; | |
855 | #address-cells = <1>; | |
856 | #size-cells = <0>; | |
857 | #power-domain-cells = <0>; | |
858 | ||
859 | pd_a3mp: a3mp@9 { | |
860 | reg = <9>; | |
861 | #power-domain-cells = <0>; | |
862 | }; | |
863 | ||
864 | pd_a3vc: a3vc@10 { | |
865 | reg = <10>; | |
866 | #power-domain-cells = <0>; | |
867 | }; | |
868 | }; | |
869 | ||
870 | pd_a4sf: a4sf@11 { | |
871 | reg = <11>; | |
872 | #power-domain-cells = <0>; | |
873 | }; | |
874 | ||
875 | pd_a3r: a3r@12 { | |
876 | reg = <12>; | |
877 | #address-cells = <1>; | |
878 | #size-cells = <0>; | |
879 | #power-domain-cells = <0>; | |
880 | ||
881 | pd_a2rv: a2rv@13 { | |
882 | reg = <13>; | |
883 | #power-domain-cells = <0>; | |
884 | }; | |
885 | ||
886 | pd_a2is: a2is@14 { | |
887 | reg = <14>; | |
888 | #power-domain-cells = <0>; | |
889 | }; | |
890 | }; | |
891 | }; | |
892 | }; | |
893 | }; | |
eccf0607 | 894 | }; |