projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 755d57b2 MD |
1 | /* |
| 2 | * Device Tree Source for the r8a7740 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | /include/ "skeleton.dtsi" | |
| 12 | ||
| d9ffd583 | 13 | #include <dt-bindings/clock/r8a7740-clock.h> |
| 5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | ||
| 755d57b2 MD |
16 | / { |
| 17 | compatible = "renesas,r8a7740"; | |
| 9ff254ad | 18 | interrupt-parent = <&gic>; |
| 755d57b2 MD |
19 | |
| 20 | cpus { | |
| b4032013 LP |
21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; | |
| 755d57b2 MD |
23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a9"; | |
| b4032013 LP |
25 | device_type = "cpu"; |
| 26 | reg = <0x0>; | |
| 63575d8c | 27 | clock-frequency = <800000000>; |
| aba07789 | 28 | power-domains = <&pd_a3sm>; |
| 755d57b2 MD |
29 | }; |
| 30 | }; | |
| 744fdc8d BH |
31 | |
| 32 | gic: interrupt-controller@c2800000 { | |
| 33 | compatible = "arm,cortex-a9-gic"; | |
| 34 | #interrupt-cells = <3>; | |
| 744fdc8d BH |
35 | interrupt-controller; |
| 36 | reg = <0xc2800000 0x1000>, | |
| 37 | <0xc2000000 0x1000>; | |
| 38 | }; | |
| 39 | ||
| f4c6d004 GU |
40 | dbsc3: memory-controller@fe400000 { |
| 41 | compatible = "renesas,dbsc3-r8a7740"; | |
| 42 | reg = <0xfe400000 0x400>; | |
| 43 | power-domains = <&pd_a4s>; | |
| 44 | }; | |
| 45 | ||
| b21ed4eb MD |
46 | pmu { |
| 47 | compatible = "arm,cortex-a9-pmu"; | |
| 5f75e73c | 48 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| b21ed4eb MD |
49 | }; |
| 50 | ||
| aba07789 GU |
51 | ptm { |
| 52 | compatible = "arm,coresight-etm3x"; | |
| 53 | power-domains = <&pd_d4>; | |
| 54 | }; | |
| 55 | ||
| c10df265 | 56 | cmt1: timer@e6138000 { |
| a2ffcf87 | 57 | compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; |
| c10df265 SH |
58 | reg = <0xe6138000 0x170>; |
| 59 | interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; | |
| 60 | clocks = <&mstp3_clks R8A7740_CLK_CMT1>; | |
| 61 | clock-names = "fck"; | |
| aba07789 | 62 | power-domains = <&pd_c5>; |
| c10df265 SH |
63 | |
| 64 | renesas,channels-mask = <0x3f>; | |
| 65 | ||
| 66 | status = "disabled"; | |
| 67 | }; | |
| 68 | ||
| 744fdc8d BH |
69 | /* irqpin0: IRQ0 - IRQ7 */ |
| 70 | irqpin0: irqpin@e6900000 { | |
| 96327999 | 71 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
| 744fdc8d BH |
72 | #interrupt-cells = <2>; |
| 73 | interrupt-controller; | |
| 74 | reg = <0xe6900000 4>, | |
| 75 | <0xe6900010 4>, | |
| 76 | <0xe6900020 1>, | |
| 77 | <0xe6900040 1>, | |
| 78 | <0xe6900060 1>; | |
| 5f75e73c LP |
79 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 80 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 81 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 82 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 83 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 84 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 85 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 86 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 3ab84ee9 | 87 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
| aba07789 | 88 | power-domains = <&pd_a4s>; |
| 744fdc8d BH |
89 | }; |
| 90 | ||
| 91 | /* irqpin1: IRQ8 - IRQ15 */ | |
| 92 | irqpin1: irqpin@e6900004 { | |
| 96327999 | 93 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
| 744fdc8d BH |
94 | #interrupt-cells = <2>; |
| 95 | interrupt-controller; | |
| 96 | reg = <0xe6900004 4>, | |
| 97 | <0xe6900014 4>, | |
| 98 | <0xe6900024 1>, | |
| 99 | <0xe6900044 1>, | |
| 100 | <0xe6900064 1>; | |
| 5f75e73c LP |
101 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 102 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 103 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 104 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 105 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 106 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 107 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 108 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 3ab84ee9 | 109 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
| aba07789 | 110 | power-domains = <&pd_a4s>; |
| 744fdc8d BH |
111 | }; |
| 112 | ||
| 113 | /* irqpin2: IRQ16 - IRQ23 */ | |
| 114 | irqpin2: irqpin@e6900008 { | |
| 96327999 | 115 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
| 744fdc8d BH |
116 | #interrupt-cells = <2>; |
| 117 | interrupt-controller; | |
| 118 | reg = <0xe6900008 4>, | |
| 119 | <0xe6900018 4>, | |
| 120 | <0xe6900028 1>, | |
| 121 | <0xe6900048 1>, | |
| 122 | <0xe6900068 1>; | |
| 5f75e73c LP |
123 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 124 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 125 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 126 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 127 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 128 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 129 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 130 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 3ab84ee9 | 131 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
| aba07789 | 132 | power-domains = <&pd_a4s>; |
| 744fdc8d BH |
133 | }; |
| 134 | ||
| 135 | /* irqpin3: IRQ24 - IRQ31 */ | |
| 136 | irqpin3: irqpin@e690000c { | |
| 96327999 | 137 | compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; |
| 744fdc8d BH |
138 | #interrupt-cells = <2>; |
| 139 | interrupt-controller; | |
| 140 | reg = <0xe690000c 4>, | |
| 141 | <0xe690001c 4>, | |
| 142 | <0xe690002c 1>, | |
| 143 | <0xe690004c 1>, | |
| 144 | <0xe690006c 1>; | |
| 5f75e73c LP |
145 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH |
| 146 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 147 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 148 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 149 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 150 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 151 | 0 149 IRQ_TYPE_LEVEL_HIGH | |
| 152 | 0 149 IRQ_TYPE_LEVEL_HIGH>; | |
| 3ab84ee9 | 153 | clocks = <&mstp2_clks R8A7740_CLK_INTCA>; |
| aba07789 | 154 | power-domains = <&pd_a4s>; |
| 744fdc8d BH |
155 | }; |
| 156 | ||
| 08ec67b5 GU |
157 | ether: ethernet@e9a00000 { |
| 158 | compatible = "renesas,gether-r8a7740"; | |
| 159 | reg = <0xe9a00000 0x800>, | |
| 160 | <0xe9a01800 0x800>; | |
| 08ec67b5 | 161 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 4a7ae2e2 | 162 | clocks = <&mstp3_clks R8A7740_CLK_GETHER>; |
| aba07789 | 163 | power-domains = <&pd_a4s>; |
| 08ec67b5 GU |
164 | phy-mode = "mii"; |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <0>; | |
| 167 | status = "disabled"; | |
| 168 | }; | |
| 169 | ||
| 744fdc8d BH |
170 | i2c0: i2c@fff20000 { |
| 171 | #address-cells = <1>; | |
| 172 | #size-cells = <0>; | |
| 5c53f50c | 173 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
| 744fdc8d | 174 | reg = <0xfff20000 0x425>; |
| 5f75e73c LP |
175 | interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH |
| 176 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
| 177 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
| 178 | 0 204 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 179 | clocks = <&mstp1_clks R8A7740_CLK_IIC0>; |
| aba07789 | 180 | power-domains = <&pd_a4r>; |
| eda3a4fa | 181 | status = "disabled"; |
| 744fdc8d BH |
182 | }; |
| 183 | ||
| 184 | i2c1: i2c@e6c20000 { | |
| 185 | #address-cells = <1>; | |
| 186 | #size-cells = <0>; | |
| 5c53f50c | 187 | compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; |
| 744fdc8d | 188 | reg = <0xe6c20000 0x425>; |
| 5f75e73c LP |
189 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH |
| 190 | 0 71 IRQ_TYPE_LEVEL_HIGH | |
| 191 | 0 72 IRQ_TYPE_LEVEL_HIGH | |
| 192 | 0 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 193 | clocks = <&mstp3_clks R8A7740_CLK_IIC1>; |
| aba07789 | 194 | power-domains = <&pd_a3sp>; |
| eda3a4fa | 195 | status = "disabled"; |
| 744fdc8d | 196 | }; |
| f36218d2 | 197 | |
| fa12355b SH |
198 | scifa0: serial@e6c40000 { |
| 199 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 200 | reg = <0xe6c40000 0x100>; | |
| 201 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
202 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; |
| 203 | clock-names = "sci_ick"; | |
| aba07789 | 204 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
205 | status = "disabled"; |
| 206 | }; | |
| 207 | ||
| 208 | scifa1: serial@e6c50000 { | |
| 209 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 210 | reg = <0xe6c50000 0x100>; | |
| 211 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
212 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; |
| 213 | clock-names = "sci_ick"; | |
| aba07789 | 214 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
215 | status = "disabled"; |
| 216 | }; | |
| 217 | ||
| 218 | scifa2: serial@e6c60000 { | |
| 219 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 220 | reg = <0xe6c60000 0x100>; | |
| 221 | interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; | |
| b345aee4 | 222 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; |
| 4a7ae2e2 | 223 | clock-names = "sci_ick"; |
| aba07789 | 224 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
225 | status = "disabled"; |
| 226 | }; | |
| 227 | ||
| 228 | scifa3: serial@e6c70000 { | |
| 229 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 230 | reg = <0xe6c70000 0x100>; | |
| 231 | interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
232 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; |
| 233 | clock-names = "sci_ick"; | |
| aba07789 | 234 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
235 | status = "disabled"; |
| 236 | }; | |
| 237 | ||
| 238 | scifa4: serial@e6c80000 { | |
| 239 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 240 | reg = <0xe6c80000 0x100>; | |
| 241 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
242 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; |
| 243 | clock-names = "sci_ick"; | |
| aba07789 | 244 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
245 | status = "disabled"; |
| 246 | }; | |
| 247 | ||
| 248 | scifa5: serial@e6cb0000 { | |
| 249 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 250 | reg = <0xe6cb0000 0x100>; | |
| 251 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
252 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; |
| 253 | clock-names = "sci_ick"; | |
| aba07789 | 254 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
255 | status = "disabled"; |
| 256 | }; | |
| 257 | ||
| 258 | scifa6: serial@e6cc0000 { | |
| 259 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 260 | reg = <0xe6cc0000 0x100>; | |
| 261 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
262 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; |
| 263 | clock-names = "sci_ick"; | |
| aba07789 | 264 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
265 | status = "disabled"; |
| 266 | }; | |
| 267 | ||
| 268 | scifa7: serial@e6cd0000 { | |
| 269 | compatible = "renesas,scifa-r8a7740", "renesas,scifa"; | |
| 270 | reg = <0xe6cd0000 0x100>; | |
| 271 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
272 | clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; |
| 273 | clock-names = "sci_ick"; | |
| aba07789 | 274 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
275 | status = "disabled"; |
| 276 | }; | |
| 277 | ||
| 50663822 | 278 | scifb: serial@e6c30000 { |
| fa12355b SH |
279 | compatible = "renesas,scifb-r8a7740", "renesas,scifb"; |
| 280 | reg = <0xe6c30000 0x100>; | |
| 281 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 UH |
282 | clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; |
| 283 | clock-names = "sci_ick"; | |
| aba07789 | 284 | power-domains = <&pd_a3sp>; |
| fa12355b SH |
285 | status = "disabled"; |
| 286 | }; | |
| 287 | ||
| f36218d2 LP |
288 | pfc: pfc@e6050000 { |
| 289 | compatible = "renesas,pfc-r8a7740"; | |
| 290 | reg = <0xe6050000 0x8000>, | |
| 291 | <0xe605800c 0x20>; | |
| 292 | gpio-controller; | |
| 293 | #gpio-cells = <2>; | |
| 778de006 LP |
294 | interrupts-extended = |
| 295 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
| 296 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
| 297 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
| 298 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
| 299 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
| 300 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
| 301 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
| 302 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
| aba07789 | 303 | power-domains = <&pd_c5>; |
| f36218d2 | 304 | }; |
| fa91515c | 305 | |
| 8b3e32c1 LP |
306 | tpu: pwm@e6600000 { |
| 307 | compatible = "renesas,tpu-r8a7740", "renesas,tpu"; | |
| 308 | reg = <0xe6600000 0x100>; | |
| 4a7ae2e2 | 309 | clocks = <&mstp3_clks R8A7740_CLK_TPU0>; |
| aba07789 | 310 | power-domains = <&pd_a3sp>; |
| 8b3e32c1 LP |
311 | status = "disabled"; |
| 312 | #pwm-cells = <3>; | |
| 313 | }; | |
| e99d7963 | 314 | |
| 7d907894 | 315 | mmcif0: mmc@e6bd0000 { |
| 5c53f50c | 316 | compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; |
| e99d7963 | 317 | reg = <0xe6bd0000 0x100>; |
| 5f75e73c LP |
318 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH |
| 319 | 0 57 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 320 | clocks = <&mstp3_clks R8A7740_CLK_MMC>; |
| aba07789 | 321 | power-domains = <&pd_a3sp>; |
| e99d7963 GL |
322 | status = "disabled"; |
| 323 | }; | |
| 324 | ||
| 7d907894 | 325 | sdhi0: sd@e6850000 { |
| e99d7963 GL |
326 | compatible = "renesas,sdhi-r8a7740"; |
| 327 | reg = <0xe6850000 0x100>; | |
| 5f75e73c LP |
328 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH |
| 329 | 0 118 IRQ_TYPE_LEVEL_HIGH | |
| 330 | 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 331 | clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; |
| aba07789 | 332 | power-domains = <&pd_a3sp>; |
| e99d7963 GL |
333 | cap-sd-highspeed; |
| 334 | cap-sdio-irq; | |
| 335 | status = "disabled"; | |
| 336 | }; | |
| 337 | ||
| 7d907894 | 338 | sdhi1: sd@e6860000 { |
| e99d7963 GL |
339 | compatible = "renesas,sdhi-r8a7740"; |
| 340 | reg = <0xe6860000 0x100>; | |
| 5f75e73c LP |
341 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH |
| 342 | 0 122 IRQ_TYPE_LEVEL_HIGH | |
| 343 | 0 123 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 344 | clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; |
| aba07789 | 345 | power-domains = <&pd_a3sp>; |
| e99d7963 GL |
346 | cap-sd-highspeed; |
| 347 | cap-sdio-irq; | |
| 348 | status = "disabled"; | |
| 349 | }; | |
| 7d907894 KM |
350 | |
| 351 | sdhi2: sd@e6870000 { | |
| 352 | compatible = "renesas,sdhi-r8a7740"; | |
| 353 | reg = <0xe6870000 0x100>; | |
| 5f75e73c LP |
354 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH |
| 355 | 0 126 IRQ_TYPE_LEVEL_HIGH | |
| 356 | 0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| 4a7ae2e2 | 357 | clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; |
| aba07789 | 358 | power-domains = <&pd_a3sp>; |
| 7d907894 KM |
359 | cap-sd-highspeed; |
| 360 | cap-sdio-irq; | |
| 361 | status = "disabled"; | |
| 362 | }; | |
| efcd869b KM |
363 | |
| 364 | sh_fsi2: sound@fe1f0000 { | |
| 365 | #sound-dai-cells = <1>; | |
| 5c53f50c | 366 | compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; |
| efcd869b | 367 | reg = <0xfe1f0000 0x400>; |
| efcd869b | 368 | interrupts = <0 9 0x4>; |
| 4a7ae2e2 | 369 | clocks = <&mstp3_clks R8A7740_CLK_FSI>; |
| aba07789 | 370 | power-domains = <&pd_a4mp>; |
| efcd869b KM |
371 | status = "disabled"; |
| 372 | }; | |
| d9ffd583 | 373 | |
| 60036333 GU |
374 | tmu0: timer@fff80000 { |
| 375 | compatible = "renesas,tmu-r8a7740", "renesas,tmu"; | |
| 376 | reg = <0xfff80000 0x2c>; | |
| 377 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
| 378 | <0 199 IRQ_TYPE_LEVEL_HIGH>, | |
| 379 | <0 200 IRQ_TYPE_LEVEL_HIGH>; | |
| 380 | clocks = <&mstp1_clks R8A7740_CLK_TMU0>; | |
| 381 | clock-names = "fck"; | |
| aba07789 | 382 | power-domains = <&pd_a4r>; |
| 60036333 GU |
383 | |
| 384 | #renesas,channels = <3>; | |
| 385 | ||
| 386 | status = "disabled"; | |
| 387 | }; | |
| 388 | ||
| 389 | tmu1: timer@fff90000 { | |
| 390 | compatible = "renesas,tmu-r8a7740", "renesas,tmu"; | |
| 391 | reg = <0xfff90000 0x2c>; | |
| 392 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, | |
| 393 | <0 171 IRQ_TYPE_LEVEL_HIGH>, | |
| 394 | <0 172 IRQ_TYPE_LEVEL_HIGH>; | |
| 395 | clocks = <&mstp1_clks R8A7740_CLK_TMU1>; | |
| 396 | clock-names = "fck"; | |
| aba07789 | 397 | power-domains = <&pd_a4r>; |
| 60036333 GU |
398 | |
| 399 | #renesas,channels = <3>; | |
| 400 | ||
| 401 | status = "disabled"; | |
| 402 | }; | |
| 403 | ||
| d9ffd583 UH |
404 | clocks { |
| 405 | #address-cells = <1>; | |
| 406 | #size-cells = <1>; | |
| 407 | ranges; | |
| 408 | ||
| 409 | /* External root clock */ | |
| 410 | extalr_clk: extalr_clk { | |
| 411 | compatible = "fixed-clock"; | |
| 412 | #clock-cells = <0>; | |
| 413 | clock-frequency = <32768>; | |
| 414 | clock-output-names = "extalr"; | |
| 415 | }; | |
| 416 | extal1_clk: extal1_clk { | |
| 417 | compatible = "fixed-clock"; | |
| 418 | #clock-cells = <0>; | |
| 419 | clock-frequency = <0>; | |
| 420 | clock-output-names = "extal1"; | |
| 421 | }; | |
| 422 | extal2_clk: extal2_clk { | |
| 423 | compatible = "fixed-clock"; | |
| 424 | #clock-cells = <0>; | |
| 425 | clock-frequency = <0>; | |
| 426 | clock-output-names = "extal2"; | |
| 427 | }; | |
| 428 | dv_clk: dv_clk { | |
| 429 | compatible = "fixed-clock"; | |
| 430 | #clock-cells = <0>; | |
| 431 | clock-frequency = <27000000>; | |
| 432 | clock-output-names = "dv"; | |
| 433 | }; | |
| fe7c20fa UH |
434 | fmsick_clk: fmsick_clk { |
| 435 | compatible = "fixed-clock"; | |
| 436 | #clock-cells = <0>; | |
| 437 | clock-frequency = <0>; | |
| 438 | clock-output-names = "fmsick"; | |
| 439 | }; | |
| 440 | fmsock_clk: fmsock_clk { | |
| 441 | compatible = "fixed-clock"; | |
| 442 | #clock-cells = <0>; | |
| 443 | clock-frequency = <0>; | |
| 444 | clock-output-names = "fmsock"; | |
| 445 | }; | |
| d9ffd583 UH |
446 | fsiack_clk: fsiack_clk { |
| 447 | compatible = "fixed-clock"; | |
| 448 | #clock-cells = <0>; | |
| 449 | clock-frequency = <0>; | |
| 450 | clock-output-names = "fsiack"; | |
| 451 | }; | |
| 452 | fsibck_clk: fsibck_clk { | |
| 453 | compatible = "fixed-clock"; | |
| 454 | #clock-cells = <0>; | |
| 455 | clock-frequency = <0>; | |
| 456 | clock-output-names = "fsibck"; | |
| 457 | }; | |
| 458 | ||
| 459 | /* Special CPG clocks */ | |
| 460 | cpg_clocks: cpg_clocks@e6150000 { | |
| 461 | compatible = "renesas,r8a7740-cpg-clocks"; | |
| 462 | reg = <0xe6150000 0x10000>; | |
| 463 | clocks = <&extal1_clk>, <&extalr_clk>; | |
| 464 | #clock-cells = <1>; | |
| 465 | clock-output-names = "system", "pllc0", "pllc1", | |
| 466 | "pllc2", "r", | |
| 467 | "usb24s", | |
| 468 | "i", "zg", "b", "m1", "hp", | |
| 469 | "hpp", "usbp", "s", "zb", "m3", | |
| 470 | "cp"; | |
| 471 | }; | |
| 472 | ||
| 473 | /* Variable factor clocks (DIV6) */ | |
| fe7c20fa UH |
474 | vclk1_clk: vclk1_clk@e6150008 { |
| 475 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 476 | reg = <0xe6150008 4>; | |
| 477 | clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, | |
| 478 | <&cpg_clocks R8A7740_CLK_USB24S>, | |
| 479 | <&extal1_div2_clk>, <&extalr_clk>, <0>, | |
| 480 | <0>; | |
| 481 | #clock-cells = <0>; | |
| 482 | clock-output-names = "vclk1"; | |
| 483 | }; | |
| 484 | vclk2_clk: vclk2_clk@e615000c { | |
| 485 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 486 | reg = <0xe615000c 4>; | |
| 487 | clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, | |
| 488 | <&cpg_clocks R8A7740_CLK_USB24S>, | |
| 489 | <&extal1_div2_clk>, <&extalr_clk>, <0>, | |
| 490 | <0>; | |
| 491 | #clock-cells = <0>; | |
| 492 | clock-output-names = "vclk2"; | |
| 493 | }; | |
| 494 | fmsi_clk: fmsi_clk@e6150010 { | |
| 495 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 496 | reg = <0xe6150010 4>; | |
| 497 | clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; | |
| 498 | #clock-cells = <0>; | |
| 499 | clock-output-names = "fmsi"; | |
| 500 | }; | |
| 501 | fmso_clk: fmso_clk@e6150014 { | |
| 502 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 503 | reg = <0xe6150014 4>; | |
| 504 | clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; | |
| 505 | #clock-cells = <0>; | |
| 506 | clock-output-names = "fmso"; | |
| 507 | }; | |
| 508 | fsia_clk: fsia_clk@e6150018 { | |
| 509 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 510 | reg = <0xe6150018 4>; | |
| 511 | clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; | |
| 512 | #clock-cells = <0>; | |
| 513 | clock-output-names = "fsia"; | |
| 514 | }; | |
| d9ffd583 UH |
515 | sub_clk: sub_clk@e6150080 { |
| 516 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 517 | reg = <0xe6150080 4>; | |
| fe7c20fa UH |
518 | clocks = <&pllc1_div2_clk>, |
| 519 | <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; | |
| d9ffd583 UH |
520 | #clock-cells = <0>; |
| 521 | clock-output-names = "sub"; | |
| 522 | }; | |
| fe7c20fa UH |
523 | spu_clk: spu_clk@e6150084 { |
| 524 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 525 | reg = <0xe6150084 4>; | |
| 526 | clocks = <&pllc1_div2_clk>, | |
| 527 | <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; | |
| 528 | #clock-cells = <0>; | |
| 529 | clock-output-names = "spu"; | |
| 530 | }; | |
| 531 | vou_clk: vou_clk@e6150088 { | |
| 532 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 533 | reg = <0xe6150088 4>; | |
| 534 | clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, | |
| 535 | <0>; | |
| 536 | #clock-cells = <0>; | |
| 537 | clock-output-names = "vou"; | |
| 538 | }; | |
| 539 | stpro_clk: stpro_clk@e615009c { | |
| 540 | compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; | |
| 541 | reg = <0xe615009c 4>; | |
| 542 | clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; | |
| 543 | #clock-cells = <0>; | |
| 544 | clock-output-names = "stpro"; | |
| 545 | }; | |
| d9ffd583 UH |
546 | |
| 547 | /* Fixed factor clocks */ | |
| 548 | pllc1_div2_clk: pllc1_div2_clk { | |
| 549 | compatible = "fixed-factor-clock"; | |
| 550 | clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; | |
| 551 | #clock-cells = <0>; | |
| 552 | clock-div = <2>; | |
| 553 | clock-mult = <1>; | |
| 554 | clock-output-names = "pllc1_div2"; | |
| 555 | }; | |
| 556 | extal1_div2_clk: extal1_div2_clk { | |
| 557 | compatible = "fixed-factor-clock"; | |
| 558 | clocks = <&extal1_clk>; | |
| 559 | #clock-cells = <0>; | |
| 560 | clock-div = <2>; | |
| 561 | clock-mult = <1>; | |
| 562 | clock-output-names = "extal1_div2"; | |
| 563 | }; | |
| 564 | ||
| 565 | /* Gate clocks */ | |
| 566 | subck_clks: subck_clks@e6150080 { | |
| 567 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 568 | reg = <0xe6150080 4>; | |
| 569 | clocks = <&sub_clk>, <&sub_clk>; | |
| 570 | #clock-cells = <1>; | |
| 9f04e567 | 571 | clock-indices = < |
| d9ffd583 UH |
572 | R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 |
| 573 | >; | |
| 574 | clock-output-names = | |
| 575 | "subck", "subck2"; | |
| 576 | }; | |
| 577 | mstp1_clks: mstp1_clks@e6150134 { | |
| 578 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 579 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
| 580 | clocks = <&cpg_clocks R8A7740_CLK_S>, | |
| 581 | <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, | |
| 582 | <&cpg_clocks R8A7740_CLK_B>, | |
| b89ff7c3 | 583 | <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, |
| d9ffd583 UH |
584 | <&cpg_clocks R8A7740_CLK_B>; |
| 585 | #clock-cells = <1>; | |
| 9f04e567 | 586 | clock-indices = < |
| d9ffd583 UH |
587 | R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 |
| 588 | R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 | |
| 589 | R8A7740_CLK_LCDC0 | |
| 590 | >; | |
| 591 | clock-output-names = | |
| 592 | "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", | |
| 593 | "tmu1", "lcdc0"; | |
| 594 | }; | |
| 595 | mstp2_clks: mstp2_clks@e6150138 { | |
| 596 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 597 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
| 3ab84ee9 GU |
598 | clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, |
| 599 | <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, | |
| d9ffd583 UH |
600 | <&cpg_clocks R8A7740_CLK_HP>, |
| 601 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 602 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 603 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
| 604 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
| 605 | <&sub_clk>; | |
| 606 | #clock-cells = <1>; | |
| 9f04e567 | 607 | clock-indices = < |
| 3ab84ee9 GU |
608 | R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA |
| 609 | R8A7740_CLK_SCIFA7 | |
| d9ffd583 UH |
610 | R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 |
| 611 | R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC | |
| 612 | R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB | |
| 613 | R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 | |
| 614 | R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 | |
| 615 | R8A7740_CLK_SCIFA4 | |
| 616 | >; | |
| 617 | clock-output-names = | |
| 3ab84ee9 GU |
618 | "scifa6", "intca", |
| 619 | "scifa7", "dmac1", "dmac2", "dmac3", | |
| d9ffd583 UH |
620 | "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", |
| 621 | "scifa2", "scifa3", "scifa4"; | |
| 622 | }; | |
| 623 | mstp3_clks: mstp3_clks@e615013c { | |
| 624 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 625 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
| 626 | clocks = <&cpg_clocks R8A7740_CLK_R>, | |
| 627 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 628 | <&sub_clk>, | |
| 629 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 630 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 631 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 632 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 633 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 634 | <&cpg_clocks R8A7740_CLK_HP>; | |
| 635 | #clock-cells = <1>; | |
| 9f04e567 | 636 | clock-indices = < |
| d9ffd583 UH |
637 | R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 |
| 638 | R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 | |
| 639 | R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 | |
| 640 | >; | |
| 641 | clock-output-names = | |
| 642 | "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", | |
| 643 | "mmc", "gether", "tpu0"; | |
| 644 | }; | |
| 645 | mstp4_clks: mstp4_clks@e6150140 { | |
| 646 | compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 647 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
| 648 | clocks = <&cpg_clocks R8A7740_CLK_HP>, | |
| 649 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 650 | <&cpg_clocks R8A7740_CLK_HP>, | |
| 651 | <&cpg_clocks R8A7740_CLK_HP>; | |
| 652 | #clock-cells = <1>; | |
| 9f04e567 | 653 | clock-indices = < |
| d9ffd583 UH |
654 | R8A7740_CLK_USBH R8A7740_CLK_SDHI2 |
| 655 | R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY | |
| 656 | >; | |
| 657 | clock-output-names = | |
| 658 | "usbhost", "sdhi2", "usbfunc", "usphy"; | |
| 659 | }; | |
| 660 | }; | |
| aba07789 GU |
661 | |
| 662 | sysc: system-controller@e6180000 { | |
| 663 | compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; | |
| 664 | reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; | |
| 665 | ||
| 666 | pm-domains { | |
| 667 | pd_c5: c5 { | |
| 668 | #address-cells = <1>; | |
| 669 | #size-cells = <0>; | |
| 670 | #power-domain-cells = <0>; | |
| 671 | ||
| 672 | pd_a4lc: a4lc@1 { | |
| 673 | reg = <1>; | |
| 674 | #power-domain-cells = <0>; | |
| 675 | }; | |
| 676 | ||
| 677 | pd_a4mp: a4mp@2 { | |
| 678 | reg = <2>; | |
| 679 | #power-domain-cells = <0>; | |
| 680 | }; | |
| 681 | ||
| 682 | pd_d4: d4@3 { | |
| 683 | reg = <3>; | |
| 684 | #power-domain-cells = <0>; | |
| 685 | }; | |
| 686 | ||
| 687 | pd_a4r: a4r@5 { | |
| 688 | reg = <5>; | |
| 689 | #address-cells = <1>; | |
| 690 | #size-cells = <0>; | |
| 691 | #power-domain-cells = <0>; | |
| 692 | ||
| 693 | pd_a3rv: a3rv@6 { | |
| 694 | reg = <6>; | |
| 695 | #power-domain-cells = <0>; | |
| 696 | }; | |
| 697 | }; | |
| 698 | ||
| 699 | pd_a4s: a4s@10 { | |
| 700 | reg = <10>; | |
| 701 | #address-cells = <1>; | |
| 702 | #size-cells = <0>; | |
| 703 | #power-domain-cells = <0>; | |
| 704 | ||
| 705 | pd_a3sp: a3sp@11 { | |
| 706 | reg = <11>; | |
| 707 | #power-domain-cells = <0>; | |
| 708 | }; | |
| 709 | ||
| 710 | pd_a3sm: a3sm@12 { | |
| 711 | reg = <12>; | |
| 712 | #power-domain-cells = <0>; | |
| 713 | }; | |
| 714 | ||
| 715 | pd_a3sg: a3sg@13 { | |
| 716 | reg = <13>; | |
| 717 | #power-domain-cells = <0>; | |
| 718 | }; | |
| 719 | }; | |
| 720 | ||
| 721 | pd_a4su: a4su@20 { | |
| 722 | reg = <20>; | |
| 723 | #power-domain-cells = <0>; | |
| 724 | }; | |
| 725 | }; | |
| 726 | }; | |
| 727 | }; | |
| 755d57b2 | 728 | }; |